Abstract: A process and apparatus for generating an output signal whose frequency varies according to a modulation scheme, the process including the steps of providing a dither generator for receiving a first input signal representative of a clock frequency and for generating, according to the modulation scheme, a dithered output signal representative of the first signal at a dithered frequency; providing a DSP for receiving the following input signals: the signal at the dithered frequency and a second signal representative of a clock frequency, the DSP adapted to generate a processed output signal representative of the maximum frequency of the second signal; wherein the modulation scheme has a periodic ultrasonic modulating wave.

Abstract: In accordance with the present invention, a method of processing a sampled signal stream containing at least one spread spectrum signal is provided together with a receiver, computer, computer-readable storage medium and computer program for the same. The method comprises the steps of processing samples at a first bit level and, either in parallel or subsequently, processing samples at a second bit level, different from the first bit level.

Abstract: A system and method for improving the dynamic performance in an analog-to-digital converter (ADC) by randomizing the differential mismatch. The differential mismatch in an input analog signal is randomized by flipping the input signal and output signal randomly.

Abstract: An analog-to-digital converter (ADC) includes a multiplying digital-to-analog converter (MDAC) having a plurality of capacitors and a plurality of capacitor positions. The ADC generates a random number for a conversion cycle. The ADC configures each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number for the conversion cycle. The ADC converts, for the conversion cycle, a voltage of an analog signal to a digital value based on the capacitor configurations.

Abstract: According to one embodiment, a method for increasing resolution and accuracy of an analog to digital converter receiving an input voltage includes dithering a number of digital output values from the analog to digital converter to generate a number of dithered values. The analog to digital converter can be an 8-bit analog to digital converter, for example. The dithered values are then averaged to generate an average dithered value. For example, the dithered values can be averaged using a moving average technique. The average dithered value is then scaled down to generate a scaled value. Thereafter, the scaled value is mapped to a, for example, 10-bit digital output having higher resolution and higher accuracy than the raw 8-bit output of the analog to digital converter. In this example, the resolution of the analog to digital converter is increased by a factor of four.

Abstract: There is provided a digital-analog converter capable of easily extending the resolution that can easily extend the resolution by a simple circuit implementation when a 10-bit digital-analog converter is configured on the basis of an 8-bit digital-analog converter used in a display driving IC, and prevent an increase in area of the display driving IC.

Abstract: A method for increasing the resolution of analog to digital conversion made by a microcontroller. A resistive-capacitive network is connected between an input/output port of the microcontroller and a sense voltage to be converted. The sense voltage is measured (i.e. converted) using the port in input mode to obtain a nominal voltage. The port is then switched to output mode and driven high (or alternatively low) for a period of time to modify the sense voltage by an amount equal to a desired fractional resolution step size. The port is switched back to input mode and the modified voltage is measured. The steps of driving the port in output mode and measuring the modified voltage can be repeated with the modification to the sense voltage increasing in successively larger multiples of the desired fractional resolution step size. In one embodiment of the method, the successive measurements can be summed to give the converted original sense voltage expressed in fractional resolution step size.

Abstract: A method for generating at least one modulator input signal from at least one regulator signal is provided. The method comprising: generating at least one dither signal based on the periodic output of elements of a discrete dither sequence of the basic form DF=0, 1, 2 . . . 2(m?n)?1; and adding the at least one dither signal to the regulator signal. The regulator signal comprises a digital regulator signal with a length of m bits, and the modulator input signal comprises a digital modulator input signal with a length of n bits, where m>n.

Abstract: According to one embodiment, a method for increasing resolution and accuracy of an analog to digital converter receiving an input voltage includes dithering a number of digital output values from the analog to digital converter to generate a number of dithered values. The analog to digital converter can be an 8-bit analog to digital converter, for example. The dithered values are then averaged to generate an average dithered value. For example, the dithered values can be averaged using a moving average technique. The average dithered value is then scaled down to generate a scaled value. Thereafter, the scaled value is mapped to a, for example, 10-bit digital output having higher resolution and higher accuracy than the raw 8-bit output of the analog to digital converter. In this example, the resolution of the analog to digital converter is increased by a factor of four.

Abstract: In a method for suppression of even-numbered harmonic distortion which occurs in a non-linear element 4, a signal x(n) is linked to a pseudo random noise sequence r(n), and is thus spread, before passing through the non-linear element 4. After passing through the non-linear element 4, the signal y*(n) is once again linked to the pseudo random noise sequence r(n). The signal y*(n) is thus despread while, in contrast, even-numbered order harmonic elements are once again spread, and remain as broadband noise.

Abstract: A delta-sigma modulator circuit includes an n-level quantizer circuit that is configured to generate a quantized output signal responsive to an input signal. The n-level quantizer circuit includes n adder circuits that are configured to add a dither signal to n quantization levels to generate n dithered quantization levels, respectively and n comparator circuits that are configured to compare the input signal with the n dithered quantization levels to generate the quantized output signal.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: Techniques for performing ?? modulation with offset in order to reduce out-of-band quantization noise are described. In an exemplary oversampling DAC that implements ?? modulation with offset, an interpolation filter performs upsampling and interpolation filtering on data samples to generate input samples. A summer adds an offset to the input samples to generate intermediate samples. The offset alters the characteristics of the quantization noise from a ?? modulator and may be selected to obtain the desired quantization noise characteristics, to retain as much dynamic range as possible, and to simplify the removal of the offset. The ?? modulator performs upsampling and noise shaping on the intermediate samples and provides output samples. An offset removal unit removes at least a portion of the offset from the output samples in the digital or analog domain. A DAC converts the output samples to analog.

Abstract: An optical receiving device of the present invention receives optical signals from an optical transmitting device which uses a modulation format wherein an optical intensity waveform of each symbol is return-to-zero (RZ) pulse, and converts the received optical signals into digital signals by a conversion process of an analog to digital (AD) converter. A control-value calculating unit subsequent to the AD converter digitally processes the digital signals, retrieves an absolute value of the digital signals or a value corresponding one-to-one with the absolute value of the digital signals, estimates errors from an appropriate timing of a sampling timing in the AD converter based on the absolute value of the digital signals or the value corresponding one-to-one with the absolute value of the digital signals, and calculates a control value controlling the sampling timing based on the estimated errors.

Abstract: A multiplexing circuit uses parallel-configured pairs of resistors and signal sources in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one signal source. One circuit includes a microprocessor having an analog-to-digital (ADC) input; a memory communicatively coupled to the microprocessor; and a voltage divider network having an output coupled to the ADC input, wherein the network includes a plurality of resistors paired with a plurality of respective signal sources, and wherein the output is unique for each combination of states of the signal sources in accordance with a known relation that is stored in the memory. The signal sources are selected from two categories of sources: continuous sources and discrete sources, where discrete sources may be binary discrete or random discrete. In one embodiment, the first signal source is either a continuous source or a random discrete source, and the second signal is a binary discrete source.

Abstract: An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.

Abstract: A signal processor includes a sigma-delta modulator. The input signal to the signal-delta modulator may contain a dc component that generates spurious tones in the modulator output. An input signal to the signal processor is multiplied by an output of a waveform generator to produce an up-converted signal prior to processing by the sigma-delta modulator. Preferably, the waveform generator produces a random signal, which may be a pseudorandom signal. However, other waveforms such as a bipolar binary waveform can also be used. The output of the waveform generator is delayed and multiplied by the output of the sigma-delta modulator to produce a down-converted signal with reduced spurious tones. The delay matches the delay of the sigma-delta modulator. The down-converted signal is filtered with a low-pass filter.

Abstract: According to one aspect of the present invention, there is provided a dither circuit including a dither generating circuit generating a plurality of complementary signal pairs, and a dither input circuit generating a plurality of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, in which the plurality of complementary signal pairs have different frequencies with each other, the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs

Abstract: According to one embodiment, a method for increasing resolution and accuracy of an analog to digital converter receiving an input voltage includes dithering a number of digital output values from the analog to digital converter to generate a number of dithered values. The analog to digital converter can be an 8-bit analog to digital converter, for example. The dithered values are then averaged to generate an average dithered value. For example, the dithered values can be averaged using a moving average technique. The average dithered value is then scaled down to generate a scaled value. Thereafter, the scaled value is mapped to a, for example, 10-bit digital output having higher resolution and higher accuracy than the raw 8-bit output of the analog to digital converter. In this example, the resolution of the analog to digital converter is increased by a factor of four.

Abstract: Systems and methods for improving efficiency of a data converter. An example method generates a noise signal, alters the spectrum of the noise signal based on operation of an associated data converter, and supplies the altered spectrum noise signal to the associated data converter. The data converter is a digital-to-analog converter or an analog-to-digital converter. The altered spectrum noise signal is notched at frequencies of interest. The spectrum is altered by sending a signal generated by a random number generator to a delay device and adding the output of the delay device from the output of the random number generator. Also, the spectrum is altered by seeding first and second identical random number generators, delaying the operation of the first random number generator, and adding the output of the delayed first random number generator from the second random number generator.

Abstract: Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.

Abstract: An analog-to-digital converter (ADC) having integrator dither injection and quantizer output compensation reduces the probability of unchanging code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the dither reduces the probability of a stuck code sequence at startup. The effect of the dither is removed from the output of the ADC, either by subtracting an offset value from the result of filtering the quantizer output, or directly from the quantizer output itself.

Abstract: Aspects of the invention provide a method and system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: A method of generating a quantized signal in a Sigma-Delta modulator (25) comprises the steps of feeding a modulator input signal to a quantizer (15) via at least one integrator (12, 13); generating in the quantizer (15) a quantized signal; feeding back the quantized signal to be subtracted from the modulator input signal; and generating a dither signal to be applied to a point in the Sigma-Delta modulator. The dither signal is applied to a selected one of a number of different points (11, 14) in the Sigma-Delta modulator (25) in dependence of a control signal. In this way a method of generating a quantized signal in a Sigma-Delta modulator is provided which provides optimal results for different modes of the application, such as phase modulation mode and frequency modulation mode in a Bluetooth receiver.

Abstract: A system and method are provided for minimizing data-dependent power variations. The system and method can include summing an input with a dither signal, processing the summed signal, and substantially removing the effects of the dither signal from the output. The output is an approximation of processing to the input alone, while certain aspects of processing activity, such as temperature changes and current draw, are less dependent on input values. Variations in data-dependent activities are thus reduced. The effects of the dither signal may be removed by equivalently processing the dither signal alone, and using that result as a compensating signal to cancel components of the processed signal that result from the presence of the dither signal.

Abstract: An apparatus and method are described to increase the control resolution of an electronic device. In one embodiment, the invention includes a spread pulse modulation module to generate a first set of bits based on a second set of bits that is larger than the first set of bits. The spread pulse modulation module modulates the least significant bit (LSB) of the first set of bits based on information including the LSB modulation period and the LSB modulation duty cycle. The spread pulse modulation module also modulates the least significant bit of the first set of bits so that the least significant bit transitions at least twice from a high value to a low value during the modulation period. This embodiment of the invention also includes a digital-to-analog conversion module to generate an analog input signal to the electronic device based on the first set of bits.

Abstract: A first-order signal generator (135). The generator comprises a shift register (210?) having a number N of bit positions. Each bit position is operable to store a binary value, the shift register operable to shift the binary value at each of the bit positions. The generator also comprises circuitry for tapping selected ones of the bit positions and circuitry for applying a function (220?) to each binary value in the selected ones of the bit positions to provide a function output. The generator also comprises circuitry for coupling the function output as an input to one of the bit positions. Lastly, the generator also comprises circuitry (230?) for outputting a first-order noise signal by coupling, as a twos complement number, each binary value in a plurality of the bit positions.

Abstract: Aspects of the invention provide a system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.

Abstract: A sigma-delta converter having dynamic dithering that reduces or removes idle-channel tones and increase linearity of the converter. The dither is differentiated in multiple orders before being applied to the converter quantizer. The differentiation order and the amplitude of the dither are determined dynamically based on the input signal amplitude in order to obtain the most effectiveness of dithering. The dynamic dither can be used in both analog-to-digital and digital-to-analog converters.

Abstract: An analog to digital converter comprising a conversion engine having redundancy therein; and a dither device for applying a dither to the conversion engine; and a controller adapted to operate the conversion engine to perform a successive approximation conversion of the analog input, and wherein the dither is removed prior to completion of the analog to digital conversion.

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: A novel and useful apparatus for and method of improving the quantization resolution of a time to digital converter in a digital PLL using noise shaping. The TDC quantization noise shaping scheme is effective to reduce the TDC quantization noise to acceptable levels especially in the case of integer-N channel operation. The mechanism monitors the output of the TDC circuit and adaptively generates a dither (i.e. delay) sequence based on the output. The dither sequence is applied to the frequency reference clock used in the TDC which adjusts the timing alignment between the edges of the frequency reference clock and the RF oscillator clock. The dynamic alignment changes effectively shape the quantization noise of the TDC. By shaping the quantization noise, a much finer in-band TDC resolution is achieved resulting in the quantization noise being pushed out to high frequencies where the PLL low pass characteristic effectively filters it out.

Abstract: Method and arrangement for oscillation isolation by means of an air bearing. The electropneumatic valves (4) for the compressed-air supply to the air bearing are subjected to a dither signal. This causes additional vibration of the mass 1 to be isolated. A compensation signal transmitter (12) ensures that additional vibration of the mass (1) is suppressed, by controlling actuators (10). Overall, hysteresis effects are avoided in the control of the compressed-air flow.

Abstract: Improving signal-to-noise ratio (SNR) when using fewer bits than the number of output bits of an ADC as digital representation of the strength of the samples of an input signal. In an embodiment, an ADC generates digital values of H bits by sampling an input signal at corresponding time instances. An error signal representing the (H-N) least significant bits of the H-bit digital values is processed to determine respective filtered values, which are respectively added to the corresponding ones of the H-bit digital values. The (H-N) bits of the resulting added values are dropped to generate N bit values. The N bit values thus generated may have improved SNR at least in a band of interest, as desired.

Abstract: A self-calibrating continuous-time delta-sigma modulator determines whether time constants of its internal integrators are too large or too small by injecting a calibrating sequence into the modulator and examining a correlation between the calibrating sequence and a modulator output sequence. Then the time constants of the internal integrators are adjusted accordingly. In one embodiment, the correlation is exploited based on matching a noise transfer function of the modulator using an adaptive filter based on a least mean square (LMS) algorithm.

Abstract: A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.

Abstract: A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.

Abstract: Disclosed are an apparatus and a method for performing dithering in a communication system using an orthogonal frequency division multiplexing scheme. A method for adding dithering noise in a communication system employing an orthogonal frequency division multiplexing scheme includes receiving a signal, and generating dithering periodic noise and adding the dithering noise to the received signal.

Abstract: In an embodiment, a delta-sigma modulator is constructed from one or more stages of a first order low-pass filter, which has a modest gain compared to the integrator used in other embodiments of delta-sigma modulators. Delta-sigma modulators can be converted into low-pass filter based delta-sigma modulators according to an embodiment of the invention by replacing the ideal integrator building block with a first order low-pass filter and adjusting other loop parameters, such as gain factors, accordingly. In an embodiment, a dithering technique to suppress spurious tones can be used with the low-pass filter based, ideal integrator based, or near ideal integrator based delta-sigma modulator. In another embodiment, a noise cancellation technique can also be used to cancel the dithering noise.

Abstract: An apparatus and method for minimizing limit cycle oscillations within a switched power supply includes providing a programmable dither signal as an input to the digital control loop connected between an output and a control input of the switched power supply. The dither signal minimizes limit cycle oscillations from the output of the switched power supply.

Abstract: In an embodiment, a delta-sigma modulator is constructed from one or more stages of a first order low-pass filter, which has a modest gain compared to the integrator used in other embodiments of delta-sigma modulators. Delta-sigma modulators can be converted into low-pass filter based delta-sigma modulators according to an embodiment of the invention by replacing the ideal integrator building block with a first order low-pass filter and adjusting other loop parameters, such as gain factors, accordingly. In an embodiment, a dithering technique to suppress spurious tones can be used with the low-pass filter based, ideal integrator based, or near ideal integrator based delta-sigma modulator. In another embodiment, a noise cancellation technique can also be used to cancel the dithering noise.

Abstract: A system and method directed to using a dither signal during conversion of an analog input signal to a digital output signal without summing the dither signal to the analog input signal. Such conversion may include generating a digital dither signal with a pseudo-random noise generator and converting the digital dither signal to an analog dither signal. The analog dither signal is provided to an impedance network that responsively produces a set of reference dither signals proportional to the analog dither signal. A plurality of comparators compares the proportional dither signals to the analog input signal so as to generate a first output code. A dither signal reference code that indicates the effects of passing the dither signal through the analog-to-digital converter is subtracted from the first output code so as to produce a second output code that is a digital representation of the analog input signal.

Abstract: A multiplexing circuit uses parallel-configured switch/resistor pairs in a voltage divider network in such a way that a single analog-to-digital input can be used to specify the state of more than one switch or other component. One circuit includes a reference voltage node, a ground node, and an output node, wherein a switched voltage divider network is configured such that the voltage at the output node is unique for every given combination of switch states.

Abstract: A delta sigma modulator is provided. The delta sigma modulator comprises quantitizer circuitry configured to generate a digital signal using a first analog signal and dither control circuitry configured to use the digital signal to adjust an amount of dither applied to the first analog signal.

Abstract: A supplied analog signal is modulated by comparing the supplied analog signal with a noise signal. As a result of each comparison, an output signal is generated having a first value if the supplied analog signal is greater than the noise signal and generating an output signal having a second value if the supplied analog signal is lower than the noise signal. Such modulation is useful in applications such as analog-to-digital conversion. The transfer function of the modulator is a function of the distribution of the noise source.

Abstract: A delta-sigma modulator coefficient calibration method and apparatus provides for adjustment of the modulator coefficients, and thus the modulator noise transfer function (NTF), in operational environments. A noise signal is injected into the feedback loop of the delta-sigma modulator either before or after the quantizer and the output of the modulator is correlated with the noise signal. The delta-sigma modulator has adjustable coefficients that are adjusted in conformity with the correlator output to achieve a more desirable noise transfer function. The correlator may include a tapped delay line and multiple correlators for simultaneously measuring each modulator coefficient directly, or may include a variable delay and a single correlator for measuring each coefficient sequentially.

Abstract: A sigma delta digital-to-analog (D/A) converter system (10) includes a summing device (35) at an input of a D/A converter (30), and a low frequency low amplitude wave signal (31) injected at an input of the summing device that remains unfiltered and is used to suppress spurious tone artifacts. The D/A converter system can further include an amplitude control and a frequency control for selectively adjusting the frequency and the amplitude of the low frequency low amplitude wave signal being injected. Note, the low frequency low amplitude repeating wave signal generator can take the form of a digital signal processor (DSP) (37) having the appropriate software to generate such signals.

Abstract: An analog-to-digital converter (ADC) system that converts an analog input signal into a digital output circuit uses a method of shaping a pseudo-random signal such that the ADC system can be used with input signals having wider swings. The ADC system also includes a quantizer having a comparator offset of less than =/?¼ least significant bit (LSB) in a stage calibrated for gain errors. A method of operating an ADC circuit includes measuring an amplitude and polarity of an input signal voltage and changing characteristics of a pseudo-random signal to ensure that a subsequent stage of the ADC circuit is not saturated. An implementation of the ADC circuit alters the pseudo-random signal based on the amplitude of the input signal such that when the input signal goes close to a positive rail, the pseudo-random signal alternates between a first range, and when the input signal goes close to a negative rail, the pseudo-random signal alternates between a second range.

Abstract: A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated consecutively by a known phase. Two of these clock signals of consecutive phases are selected for interpolation for higher precision according to predetermined weights. The resulting interpolated clock signal has a phase offset that is intermediate between the selected clock signals in proportion to the predetermined weights. In one implementation, a second interpolated clock signal is created by selecting and weighting a second group of clock signals using independent selection and weights. The two interpolated clock signals are then combined by logic operations to provide a precise clock signal of predetermined duty cycle and phase.

Abstract: Aspects of the invention provide a method and system for a mixed analog-digital automatic gain control. The received analog signal is amplified by the analog amplifier and then converted to a digital value by an ADC. A clamp reference level of the converted signal is removed prior to applying a digital gain to a digital multiplied. Once the digital gain is applied, the clamp reference level is restored to the digital signal. A loop filter determines the system time response from the error between an amplitude parameter of the received signal and an AGC reference level. A gain separation circuit generates the system gain and separates it into a digital gain and an analog gain in a way to maximize the use of the analog amplifier. The analog gain is applied to the analog amplifier and the digital gain is applied to the digital multiplier.