Field Effect Transistor Patents (Class 341/136)
  • Patent number: 11308996
    Abstract: A sensing circuit includes a cell clock generator, a reference clock generator, a counter, a latching signal generator, a latch and a count-to-state conversion circuit. The cell clock generator receives a cell current from a selected memory cell, and converts the cell current into a cell clock signal. The reference clock generator converts a reference current into a reference clock signal. The count receives the cell clock signal, and generates a count value. When a pulse number of the reference clock signal reaches a predetermined count value, the latching signal generator activates a latching signal. When the latching signal is activated, the latch issues a latched count value. The count-to-state conversion circuit receives the latched count value, and issues a state value. A storage state of the selected memory cell is determined according to the state value.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: April 19, 2022
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventor: Che-Wei Chang
  • Patent number: 11018908
    Abstract: An optical communication system includes a transmission side system for multi-level pulse amplitude modulation (PAM) and a corresponding receiver side system, where the transmission side comprises a laser source providing an optical beam, a signal source of electrical signals to be modulated onto the optical beam, and a modulator coupled to the laser source and the signal source to modulate the electrical signals onto the optical beam using amplitude modulation and at least four signal levels, wherein the at least four signal levels are non-uniformly distributed. The receiver side includes a corresponding equalizer which is implemented as a filter of the form f1y+f2y2+f0, where y is the incoming signal and the parameters f0, f1 and f2 are obtained using an adaptive filter.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 25, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Nebojsa Stojanovic
  • Patent number: 10998915
    Abstract: A digital-to-analog converter circuit including one or more digital-to-analog converter cells and a separate voltage protection circuit connected by a common output node. A first digital-to-analog converter cell includes a first transistor which is configured to be switched to a conductive state when the first digital-to-analog converter cell is activated. A first terminal of the first transistor is coupled to a defined potential, wherein a second terminal of the first transistor is coupled to a common output node of the one or more digital-to-analog converter cells. The digital-to-analog converter circuit further includes a voltage protection circuit coupled between the common output node of the one or more digital-to-analog converter cells and an output node of the digital-to-analog converter circuit to regulate a voltage between the common output node and the defined potential.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 4, 2021
    Assignee: Intel IP Corporation
    Inventors: Jose Pedro Diogo Faisca Moreira, Joerg Fuhrmann, Patrick Ossmann, Harald Pretl
  • Patent number: 10992893
    Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 27, 2021
    Assignee: Cista System Corp.
    Inventors: Dennis Tunglin Lee, Guangbin Zhang
  • Patent number: 10944417
    Abstract: A DAC current steering circuit includes a first transistor whose: drain is coupled to a first output, source is coupled to a drain of a second transistor at a first node, and gate is coupled to a data input, and a third transistor whose: drain is coupled to a second output, source is coupled to a drain of a fourth transistor at a second node, and gate is coupled to a complement of the data input. The circuit further includes first and second shadow capacitors respectively coupled, via first and second switches, between the first and second nodes and ground, the first and second switches respectively controlled by the complement of the data input, and the data input.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventor: Abhirup Lahiri
  • Patent number: 10938403
    Abstract: An example device comprises a digital-to-analog converter (DAC) comprising first and second transistors coupled to a first amplifier, the second transistor coupled to a first output of the DAC and to an output of the first amplifier, and third and fourth transistors coupled to the first amplifier and to a second output of the DAC, the third and fourth transistors switchably coupled to a voltage supply and to the first transistor. The device also comprises a first node coupled to the first output of the DAC and to a resistor. The device further includes a second node coupled to the second output of the DAC, and a second amplifier coupled to the second node and to the first transistor and switchably coupled to the third and fourth transistors. The device also comprises a comparator coupled to the first node.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: March 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mustapha El Markhi, Erhan Ozalevli, Tuli Dake, Rohit Bhan
  • Patent number: 10915298
    Abstract: Methods of performing mixed-signal current-mode multiply-accumulate (MAC) operations for binarized neural networks in an integrated circuit are described in this disclosure. While digital machine learning circuits are fast, scalable, and programmable, they typically require bleeding-edge deep sub-micron manufacturing, consume high currents, and they reside in the cloud, which can exhibit long latency, and not meet private and safety requirements of some applications. Digital machine learning circuits also tend to be pricy given that machine learning digital chips typically require expensive tooling and wafer fabrication associated with advanced bleeding-edge deep sub-micron semiconductor manufacturing.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: February 9, 2021
    Inventor: Ali Tasdighi Far
  • Patent number: 10840927
    Abstract: Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 17, 2020
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Dan Shen, Balakishan Challa, Lorenzo Crespi
  • Patent number: 10819283
    Abstract: Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 27, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10812743
    Abstract: An image sensing device includes a pixel array suitable for generating a pixel signal, a tracking circuit suitable for generating a tracking signal whose voltage level gradually converges to a voltage level of the pixel signal by selectively using any one of a first convergence voltage where an amount of decrease in a voltage level gradually decreases during a plurality of tracking periods and a second convergence voltage where an amount of increase in a voltage level gradually decreases during the tracking periods for each tracking period, based on the pixel signal and first and second comparison result signals, and a signal generation circuit suitable for generating the first and second comparison result signals and an image signal based on the pixel signal and the tracking signal.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventor: Tae-Gyu Kim
  • Patent number: 10804923
    Abstract: A superposition operation circuit and a float-voltage digital-to-analog conversion circuit to superpose analog elements according to an indirect current superposition principle, where a voltage follower is implemented using a first operational amplifier such that an output end of the voltage follower is clamped to a voltage that is input to a positive-phase input end, namely, a to-be-superposed analog element. Then a current generation circuit converts a voltage signal to a current signal, a voltage drop for the current signal is generated on a first resistor coupled to an output end of the first operational amplifier, and the voltage drop is superposed on a voltage signal output by the first operational amplifier.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 13, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD
    Inventors: Yue Chen, Liang Chen, Jiake Wang
  • Patent number: 10804925
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: October 13, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10797915
    Abstract: An apparatus and method are provided for processing a received input signal comprising a sequence of data blocks. Counter circuitry within the apparatus is arranged to receive a digital representation of the input signal, and for each data block generates a count value indicative of occurrences of a property of the digital representation (for example a rising edge or a falling edge) during an associated data block transmission period. Quantization circuitry then maps each count value to a soft decision value from amongst a predetermined set of soft decision values, where the number of soft decision values in the predetermined set exceeds a number of possible data values of the data block. The output circuitry then generates a digital output signal in dependence on the soft decision values.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: October 6, 2020
    Assignee: ARM Limited
    Inventors: Paul Nicholas Whatmough, Shidhartha Das
  • Patent number: 10763888
    Abstract: A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Chenming Zhang, Lucien Johannes Breems, Muhammed Bolatkale
  • Patent number: 10756749
    Abstract: A DAC device includes a first DAC circuit and a second DAC circuit. The first DAC circuit includes multiple DAC portions, each of which includes multiple pMOSFETs. The second DAC circuit includes multiple DAC portions, each of which includes multiple nMOSFETs. For each of the first and second DAC circuits, bulk terminals of at least some of the MOSFETs of each DAC portion are for receiving a respective one of bulk voltages with different magnitudes, a gate terminal of each of the MOSFETs of the DAC portions is for receiving a gate signal, and voltage magnitudes of at least some of the gate signals received by each DAC portion switch between a respective one of different logic high levels and a respective one of different logic low levels.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 25, 2020
    Assignee: NOVATEK MICROELECTRONICS CORP.
    Inventor: Yen-Cheng Cheng
  • Patent number: 10707892
    Abstract: A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Zhang
  • Patent number: 10700699
    Abstract: A digital-to-analog converter (DAC) includes input circuitry to receive a digital word of N bits, and an array of N bit processing units disposed in parallel. Each of the N bit processing units includes first switch circuitry to generate a first output state based on a first value of a received one of the N bits, and second switch circuitry to generate a second output state based on a second value of the received one of the N bits. The DAC also includes selectively enabled third switch circuitry to generate a conditional third output state. A voltage-mode driver includes input circuitry to selectively receive one of N bits of a digital word. First switch circuitry generates a first output state based on a first value of the received one of the N bits. Second switch circuitry generates a second output state based on a second value of the received one of the N bits. Selectively enabled third switch circuitry generates a conditional third output state.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: June 30, 2020
    Assignee: Marvell Asia Pte, LTD
    Inventor: Joseph Briaire
  • Patent number: 10693687
    Abstract: Techniques are disclosed implementing a radio partitioning architecture using multiple data streams over a single coaxial cable that does not require external RF filtering. This provides a flexible frequency scheme (e.g., using IF frequency adjustment) that enables the avoidance of Wi-Fi and LTE harmonics. The techniques include leveraging baseband filtering, which may be integrated with the radio head in a common radio frequency intergraded circuit (RFIC).
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventor: Igal Kushnir
  • Patent number: 10608656
    Abstract: Facilitating a reduction in sensor system latency, circuit size, and current draw utilizing a group of continuous-time Nyquist rate analog-to-digital converters (ADCs) in a round-robin manner is presented herein. A sensor system can comprise a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system; a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors; a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; and a continuous-time Nyquist rate analog-to-digital converter of the group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: March 31, 2020
    Assignee: INVENSENSE, INC.
    Inventor: Vadim Tsinker
  • Patent number: 10541704
    Abstract: A pipelined analog-to-digital converter (ADC) using a multiplying digital-to-analog converter (MDAC) and two sub-range analog-to-digital converters (sub-range ADCs) is disclosed. The MDAC samples an analog input and performs multiplication on the sampled analog input based on control bits. The first sub-range ADC provides the MDAC with the control bits. The second sub-range ADC is coupled to the MDAC for conversion of a multiplied signal output from the MDAC. The first sub-range ADC samples the analog input to generate the control bits for the MDAC as well as pre-estimated bits for the second sub-range ADC. The second sub-range ADC operates based on the pre-estimated bits and thereby a first section of digital bits are generated by the second sub-range ADC. A second section of digital bits are provided by the first sub-range ADC. The first and second sections of digital bits represent the analog input.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 21, 2020
    Assignee: MEDIATEK INC.
    Inventor: Tzu-Chien Wu
  • Patent number: 10484000
    Abstract: A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 19, 2019
    Assignee: IMEC vzw
    Inventors: Ewout Martens, Benjamin Hershberg, Jan Craninckx
  • Patent number: 10466279
    Abstract: The analog signal detecting circuit comprises a reference voltage generator that outputs a plurality of reference voltages, the number of the reference voltages being varied depending on a voltage width between a minimum voltage value and a maximum voltage value of an analog signal; a plurality of comparators that compares a voltage of the analog signal with each of the plurality of reference voltages output from the reference voltage generator; a plurality of pulse generators that outputs a plurality of pulse signals having widths among the plurality of pulse signals varied depending on a frequency of the analog signal; and a combiner circuit section that outputs the pulse signals from the plurality of pulse generators by summing up.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: November 5, 2019
    Assignee: LSIS CO., LTD.
    Inventor: Jongkug Seon
  • Patent number: 10439631
    Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 8, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivasa Rao Madala, Rahul Sharma, Sandeep Kesrimal Oswal
  • Patent number: 10440303
    Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 8, 2019
    Assignee: Cista System Corp.
    Inventors: Dennis Tunglin Lee, Guangbin Zhang
  • Patent number: 10345841
    Abstract: A current source circuit includes a first variable resistor circuit. The first variable resistor circuit includes a resistive material and a first plurality of tap inputs configured to set a resistance of the first variable resistor circuit. The current source circuit includes an output configured to provide a current. The current is adjustable by varying the resistance of the first variable resistor circuit. The current source circuit includes a second variable resistor circuit. The second variable resistor circuit includes a resistive material of a same resistive material type as the resistive material of the first variable resistor circuit. The second variable resistor circuit includes a second plurality of tap inputs configured to set a resistance of the second variable resistor circuit. Each tap resistance of the second variable resistor circuit is proportional to a corresponding tap resistance of the first variable resistor circuit.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: July 9, 2019
    Assignee: NXP USA, INC.
    Inventors: Robert S. Jones, III, Xiankun Jin
  • Patent number: 10348319
    Abstract: Techniques to use reservoir capacitors in ADC to supply most of the charge to bit-trial capacitors as bit-trials are performed. An accurate reference voltage source, e.g., a reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC is ready to sample onto the residue amplifier. These techniques can ease the demands on the reference buffer circuit and requirement of external decoupling capacitors, for example.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Sandeep Monangi, Anoop Manissery Kalathil, Vinayak Mukund Kulkarni, Michael C. W. Coln
  • Patent number: 10334196
    Abstract: A semiconductor device that can extend the range of adaptable sampling rate when performing analog/digital conversion is provided. The semiconductor device includes a plurality of sample-and-hold circuits storing an analog signal and a plurality of converter circuits having a function of converting the analog signal stored in the sample-and-hold circuit into a digital signal. The sample-and-hold circuit includes a switch and a capacitor that is supplied with an analog signal through the switch. The switch includes an oxide semiconductor in a channel formation region.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Haruki Katagiri
  • Patent number: 10332471
    Abstract: Embodiments of the present disclosure provide a pulse generation device, an array substrate, a drive circuit and a driving method. The pulse generation device includes: a reset module making a pulse output end output low level, in response to a low level of a first input end or in response to a low level of a second input end and a low level of a third input end; a pulse generation module making the pulse output end output a high level, in response to a high level of the first input end, a high level of the second input end and a low level of the third input end or in response to a high level of the first input end, a low level of the second input end and a high level of the third input end.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 25, 2019
    Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Qiangcan Huang, Tao Peng
  • Patent number: 10311375
    Abstract: An analog implementation is proposed of an adaptive signal processing model of a kind requiring a plurality of randomly-set variables. In particular, following a digital to analog conversion of a digital input signal, analog processing is used to transform the data input to the model into data which is subsequently processed by an adaptively-created layer of the model. In the analog processing, multiplication operations involving the randomly-set variables are performed by analog circuitry in which the randomly-set variables are the consequence of inherent tolerances in electrical components. This eliminates the need for the randomly-set variables to be implemented in some other way, for example as random variables stored in memory.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 4, 2019
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Arindam Basu, Enyi Yao, Yi Chen
  • Patent number: 10297222
    Abstract: A driver and an electronic device include a capacitor driving circuit and a capacitor circuit having a plurality of capacitors provided between a plurality of capacitor driving nodes and a data voltage output terminal. The capacitor driving circuit has a plurality of driving units that output capacitor driving voltages, and in the case where a capacitance of one of the plurality of capacitors is the highest, after a driving unit that drives that capacitor has outputted a capacitor driving voltage, the next driving unit outputs the next capacitor driving voltage.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 21, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 10270462
    Abstract: A digital to analog conversion circuit is disclosed. In one example, the conversion circuit includes a selector unit and a differential amplifier. The selector unit includes a selector unit that selects nodes from a voltage dividing circuit based upon bit information of a higher order side of an input digital signal and outputs voltages of the selected nodes. The differential amplifier includes differential pairs to which the output voltages of the selector unit are input. When a voltage corresponding to the digital signal is output, after a correspondence relationship between the output voltages of the selector unit and the inputs of the respective differential pairs of the differential amplifier is allowed to have a short settling time, and is then controlled in accordance with the bit information of the lower order side of the input digital signal.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventor: Takeshi Aoki
  • Patent number: 10250139
    Abstract: According to one embodiment of this disclosure, an apparatus is disclosed. The apparatus includes a voltage regulator configured to produce a regulated voltage, a plurality of current circuits coupled in parallel between an output node and a power node, each of the plurality of current circuits including first and second transistors coupled in series, the first transistor of each of the plurality of current circuits being biased with the regulated voltage, and a control circuit configured to activate the second transistor of selected one or ones of the plurality of current circuits responsive, at least in part, to a voltage at the output node.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 2, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Yuanzhong Wan, Dong Pan
  • Patent number: 10142804
    Abstract: An all-group calling method, system, related device and computer storage medium, the method comprising: setting an all-group calling number at a terminal; and in an emergency, the terminal jointly establishes, according to the all-group calling number, an all-group call between terminals via a base station or the base station and a core network.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 27, 2018
    Assignee: ZTE Corporation
    Inventor: Chaowu Jiao
  • Patent number: 10073167
    Abstract: The disclosure provides a circuit. The circuit includes an amplifier and a digital to analog converter (DAC). The amplifier receives a reference voltage at an input node of the amplifier. The DAC is coupled to the amplifier through a refresh switch. The DAC includes one or more current elements. Each current element of the one or more current elements receives a clock. The DAC includes one or more switches corresponding to the one or more current elements. A feedback switch is coupled between the one or more switches and a feedback node of the amplifier. The DAC provides a feedback voltage at the feedback node of the amplifier.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: September 11, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jagannathan Venkataraman
  • Patent number: 10038454
    Abstract: Analog-digital converter configured for conversion of an input voltage, represented by a pair of input potentials, into a binary code using successive approximation. The analog-digital converter comprises a reference voltage generator (RVG) supplying a first pair of reference potentials and a second pair of reference potentials. The analog-digital converter further comprises a switched capacitor array (SCA) configured to receive the first and the second pair of reference potentials as well as a control unit (CTRL) coupled to the switched capacitor array (SCA) and configured to switch capacitors of the switched capacitor array (SCA) either to the first pair of reference potentials or to the second pair of reference potentials depending on a progress of the conversion.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: July 31, 2018
    Assignee: Synopsys, Inc.
    Inventors: Pedro Miguel Ferreira de Figueiredo, Paulo António Ribeiro Cardoso
  • Patent number: 10014874
    Abstract: A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 3, 2018
    Inventors: Yuan-Ju Chao, Ta-Shun Chu
  • Patent number: 10009039
    Abstract: A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 26, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, Daniel J. Allen, John L. Melanson, Aniruddha Satoskar
  • Patent number: 9985641
    Abstract: Exemplary embodiments of the present invention pertain to circuitry provided in a digital-to-analog converter (DAC) for carrying out measurements indicative of various performance characteristics of the DAC. In one exemplary implementation, a control circuit containing one or more switches is used to controllably route into a measurement system, a portion of a signal that straddles a boundary between a first digital data bit and a second digital data bit in a sequence of digital data bits that are received in a DAC cell of the DAC. The control circuit, which can be included in one or more DAC cells of the DAC, is connected to a branch of a differential circuit that is provided in each of the DAC cells of the DAC, in a manner that does not affect digital-to-analog conversion in the DAC cells.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: May 29, 2018
    Assignee: Keysight Technologies, Inc.
    Inventors: Sourja Ray, Jacky Kin Chi Liu
  • Patent number: 9970825
    Abstract: A delta-sigma modulator may be used to generate temperature information within an integrated circuit. The delta-sigma modulator may include a loop filter, a quantizer, and a feedback digital-to-analog converter (DAC). Temperature sensing elements may be incorporated into the feedback DAC of the delta-sigma modulator. Temperature information is then processed in the loop filter of the delta-sigma modulator and output in an average voltage value of a digital signal output from the delta-sigma modulator.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: May 15, 2018
    Assignee: Cirrus Logic, Inc.
    Inventors: Ramin Zanbaghi, John L. Melanson
  • Patent number: 9959833
    Abstract: A driver and an electronic device include a capacitor driving circuit and a capacitor circuit having a plurality of capacitors provided between a plurality of capacitor driving nodes and a data voltage output terminal. The capacitor driving circuit has a plurality of driving units that output capacitor driving voltages, and in the case where a capacitance of one of the plurality of capacitors is the highest, after a driving unit that drives that capacitor has outputted a capacitor driving voltage, the next driving unit outputs the next capacitor driving voltage.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: May 1, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 9953728
    Abstract: Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column line and a row line of the RRAM array. A first column line may be coupled to a first input of a first current-steering multiplexer and the first current-steering multiplexer may have an output coupled to a first current sense amplifier and a select input coupled to a first column select signal. A second column line may be coupled to a second input of the first current-steering multiplexer and coupled to a first input of a second current-steering multiplexer. The second current-steering multiplexer may have an output coupled to a second current sense amplifier and a select input coupled to a second column select signal. A third column line may be coupled to a second input of the second current-steering multiplexer.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 24, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Emmanuelle J Merced Grafals, Brent Buchanan, Le Zheng
  • Patent number: 9912289
    Abstract: The present disclosure proposes: a distributor measuring box designed to be installed on a photovoltaic solar module, having a housing with a support section embodied to be supported on the solar module, an encompassing side wall, and a cover, and string line feedthroughs and/or string line connectors, and having a string current measuring module that includes a measuring component and an evaluation unit for measuring the string current in the distributor measuring box; a photovoltaic solar module having a plurality of solar cells, in which a distributor measuring box is mounted to the back of the solar module oriented away from the sun; and a photovoltaic system having a plurality of photovoltaic solar modules, having a plurality of string lines, having a generator junction box, and having at least one inverter for supplying the electrical power produced by the photovoltaic generator.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 6, 2018
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventor: Carsten Thoerner
  • Patent number: 9882576
    Abstract: An analog-to-digital converter (ADC) and method of operation thereof are provided for converting an analog signal to a digital signal. The ADC utilizes Correlated Electron Material (CEM) devices that may contain a transition metal oxide (TMO), such as Nickel Oxide (NiO). The ADC may include an interconnect circuit that is operable to couple a power supply to the CEM devices. The power supply is controlled to program the resistance of the CEM devices and thereby control performance characteristics of the ADC.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: January 30, 2018
    Assignee: ARM Limited
    Inventors: Bal S. Sandhu, Piyush Agarwal, Akshay Kumar
  • Patent number: 9866234
    Abstract: Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Yi-Hung Tseng
  • Patent number: 9843336
    Abstract: A current steering converter fabricated using a predetermined integrated circuit technology includes a unary portion having one or more current sources and a binary portion including a plurality of switches controlled by a decoder, the switches coupled to a converter output; and a plurality of devices commonly connected at a first end and coupled to each respective switch at a second end, wherein each device size comprises (W/L)*M, where W/L is a width and length of the device and M is an integer representing multiple number.
    Type: Grant
    Filed: April 23, 2017
    Date of Patent: December 12, 2017
    Inventors: Yuan-Ju Chao, Ta-Shun Chu
  • Patent number: 9679529
    Abstract: In a display device including a driver that drives a load line of an electro-optical panel through capacitor charge redistribution, a data voltage will change in the case where an electro-optical panel-side capacitance changes, even when tone data is the same. Accordingly, by detecting a voltage at a data voltage output terminal, a connection state and outputs between the data voltage output terminal and the electro-optical panel can be detected.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 13, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Akira Morita
  • Patent number: 9634656
    Abstract: A current driver circuit includes: a current conversion unit including an input side transistor, in which a reference current is input, and multiple output side transistors, which output an output current corresponding to the reference current, and having an digital-analog conversion function for converting a digital control signal to an analog signal and a current amplifying function for amplifying the reference current according to an amplification ratio corresponding to the digital control signal; and an adjustment unit adjusting the digital control signal to be input into the output side transistors. When the adjustment unit adjusts the digital control signal, the current conversion unit changes the amplification ratio to gradually increase or decrease the output current, and controls a slew rate of the output current within a predetermined range.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: April 25, 2017
    Assignee: DENSO CORPORATION
    Inventor: Kenji Inazu
  • Patent number: 9584102
    Abstract: A system is provided for generating a ramping signal. The system includes a plurality of storage circuits each including an input and an output. The output of a previous storage circuit is connected to the input of a next storage circuit. The storage circuits are configured to propagate a first enable signal based on a first control signal. The system also includes a plurality of first current generating circuits. Each first current generating circuit is coupled to the output of a corresponding storage circuit to receive the propagated first enable signal. The first current generating circuits are configured to generate a first current signal based on the propagated first enable signal.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: February 28, 2017
    Assignee: Cista System Corp.
    Inventors: Dennis Tunglin Lee, Guangbin Zhang
  • Patent number: 9584151
    Abstract: Reducing distortions in a digital-to-analog converter is a challenge for circuit designers. For current steering digital-to-analog converters (DACs), a quad switching scheme has been used to remove code-dependent glitching which is otherwise present in dual switching schemes. However, due to various impairments in the circuit, e.g., mismatches in the transistors, some code-dependent distortions remain even when a quad switching scheme is implemented. To address this issue, the quad switching scheme can be randomized to improve dynamic linearity while relaxing driving circuitry design and power constraints. Advantageously, randomization reduces the code dependency of the distortions and makes the distortions appear more noise-like at the output of the DAC.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 28, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Gabriele Manganaro, Gil Engel
  • Patent number: 9450599
    Abstract: A current DAC circuit includes a reference current source, a current mirror, a decoder, and one or more current DAC units. The reference current source provides a reference current to a first node. The current mirror includes first and second PMOS transistors configured to provide a copy current generated by copying the reference current to a second node and coupled, at respective drains, to separate nodes. The current mirror may reduce noise of the first and second PMOS transistors through swapping the separate nodes to which the respective drains of the first and second PMOS transistors are connected periodically according to first and second clock signals. The decoder generates one or more enable signals based on a data input signal. One or more current DAC units generate separate positive currents and negative currents based on the copy current and separate enable signals of the one or more enable signals, respectively.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Woo Kwon, Myung-Jin Lee