Abstract: A digital to analog converter (DAC) that reduces sub-threshold leakage current in PLLsincludes three series connected transistors, a unity gain buffer, and a switch. The system is connected between the voltage-to-current converter and a current-controlled oscillator. The DAC receives and accurately mirrors a current signal generated by a voltage-to-current converter.

Abstract: An analog-to-digital (A/D) converter includes: a coarse A/D converter configured to convert, when converting an analog input signal into an N-bit digital signal, the analog input signal into a high-order m-bit digital signal; a fine A/D converter configured to convert the analog input signal into a low-order n-bit (where n=N?m) digital signal based on a conversion result of the coarse A/D converter; and a track-and-hold (TH) circuit configured to sample the analog input signal, to supply a comparison voltage compared with a coarse reference voltage to the coarse A/D converter, and to supply a comparison voltage compared with a fine reference voltage based on a conversion result of the fine A/D converter to the fine A/D converter. The TH circuit is configured to share a sampling capacitor in a selective input path for the analog input signal, the coarse reference voltage, and the fine reference voltage.

Abstract: An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit.

Abstract: Digital to analog converter (DAC) with ternary or tri-state current source. A DAC including a number of ternary or tri-state devices operates based upon codewords provided thereto. Generally, each respective codeword bit directs operation of one of the respective ternary or tri-state devices within the DAC. Each ternary or tri-state device operates in at least three respective operational states (e.g., based upon the respective values of +1, ?1, or 0 being provided thereto). In a current source implementation, each respective current source is implemented to deliver current, draw current, or neither delivered or draw current. In a voltage source implementation, each respective voltage source is implemented to provide a positive voltage, a negative voltage, or provide no voltage. A DAC coding table may be designed based upon characterization of codewords provided to one or more DACs (e.g., based upon a distribution, a probability density function (PDF), etc. of such codewords).

Abstract: Various embodiments of this disclosure may describe a two-stage ADC circuit, and a time-interleaved system based on the two-stage ADC circuit. The two-stage ADC circuit may include a SAR converter for the first stage and a charge based TDC for the second stage. The two-stage ADC circuit may be used in high performance serial I/O applications. Other embodiments may be disclosed and claimed.

Abstract: A digital-to-analog converter (DAC) uses thermometer coding over a certain code range. A switch array for the certain code range is implemented into a smaller area of the integrated circuit die so as to take advantage of the lower gradient inherent in the smaller area. By implementing the certain input code range into the smaller switch array area, further improved linearity in that input code range is achieved at the expense of worse linearity in the other input code ranges, but without increasing power consumption and/or chip-area of the integrated circuit die.

Abstract: A current-steering digital-to-analog converter may include a plurality of current cells. Each current cell may comprise a dual bias switched cascode output current source/sink, a bias source, complementary bias switching elements coupled between the bias source and the bias inputs of the switched cascode output current source/sink, and complementary switching signals coupled to the control inputs of the complementary bias switching element.

Abstract: A digital-to-analog converting device converts an N-bit digital input signal into an analog signal using M reference voltages, where N>3 and M=2(N?2)+1, and includes: a decoding unit operable based on third to Nth bits of the digital input signal and reference voltages to output first and second decoding voltages; and an output unit operable based on the first and second decoding voltages and first and second bits of the digital input signal to generate the analog signal. The decoding unit includes K first selectors and a second selector consisting of first and second decoding circuits, where K=2(N?3)+1.

Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.

Abstract: The present disclosure provides techniques for using an NMOS field effect transistor-based buffer to buffer a pair of complementary digital signals and output a pair of equivalently fast rising and fast falling complementary signals to simultaneously drive a differential pair of PMOS transistors of a unit cell that output an analog signal for a current steering DAC. Accordingly, a DAC comprises a latch circuit and a unit cell circuit. The latch circuit includes an NMOS field effect transistor-based buffer and is capable of receiving a first digital signal and a clock signal and outputting a second digital signal through the NMOS field effect transistor-based buffer according to the clock signal. The second digital signal is associated with the first digital signal. The unit cell circuit, coupled to the latch circuit, receives the second digital signal and outputs an analog signal representative of the first digital signal.

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: There is provided a digital-to-analog converter including: a mirror circuit including a first transistor to copy a reference current at a predetermined mirror ratio, and a second transistor cascade coupled with the first transistor; and an analog switch coupled with a gate of the second transistor, the analog switch being configured to be controlled, by a digital signal input from outside, so as to be turned on or off.

Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.

Abstract: An A-type converter circuit compares an input voltage with multiple threshold voltages, judges which segment it belongs to, and generates first and second voltages with the input voltage segment between them. The A-type converter circuit generates third and fourth voltages by amplifying the differences between the first and the input voltages and between the second and the input voltages. A B-type converter circuit divides the range between the third and fourth voltages into multiple segments, and judges which segment includes the common voltage. Subsequently, the B-type converter circuit generates fifth and sixth voltages with the common voltage segment between them. The B-type converter circuit generates a seventh (the next stage's third voltage) and an eighth voltage by amplifying the differences between the fifth and the common voltages and between the sixth and the common voltages.

Abstract: A digital signal power amplification apparatus with multiple digital amplification cells connected in series, each amplification cell processing a separate bit of the digital signal. The apparatus additively combines the output from each amplifier into a single amplified signal without the use of separate signal combining circuitry. The apparatus has high linearity, high efficiency, high bandwidth and high power.

Abstract: Disclosed herein is a sigma-delta modulator, including an integration circuit, a first DAC unit, and a second DAC unit. The integration circuit includes first and second terminals, and integrates a voltage supplied via the first terminal. The first DAC unit alternately supplies a first voltage obtained at one end of a first resistor to the first terminal and the second terminal. The second DAC unit alternately supplies a second voltage at the other end of a second resistor to the second terminal or the first terminal. The second DAC unit supplies the second voltage to the second terminal when the first DAC unit supplies the first voltage to the first terminal. The second DAC unit supplies the second voltage to the first terminal when the first DAC unit supplies the first voltage to the second terminal.

Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.

Abstract: A digital-to-analog converter converts a digital input signal into an analog output signal. The digital-to-analog converter includes an input selector configured to input the digital input signal and an output terminal configured to output the analog signal. An array of current source cells is provided. Each current source cell includes a current source transistor having a gate terminal and a source terminal, a current source switch for coupling the source terminal to the output terminal based on the digital input signal, and a compensation capacitor configured to compensate a capacitive feedback between the gate terminal and the source terminal when the source terminal is coupled to the output terminal. At least one of the current source cells further includes a calibration circuit configured to detect a voltage variation at the gate terminal and provide a compensation voltage for the compensation capacitor.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: High conversion rates are achieved in an analog to digital converter by tailoring the substrate type to specific operational elements of the converter. Embodiments place sample and hold processing circuitry on a substrate type having properties that allow for faster processing at high sampling/clock frequencies. Other operational elements of the converter are constructed on at least one other substrate type in keeping with the remainder of the circuitry for which the converter is being implemented. The sample and hold substrate may be implemented on any material which is capable of faster processing, such as silicon germanium, gallium arsenide, silicon bipolar, BiCMOS, and the like. Other portions may be implemented on a more CMOS substrate. Such systems and methods are able to implement analog-to digital conversion for broadband signals at high speeds without the need for extensive timing compensation, while also avoiding problems due to noise from further digital processing circuitry.

Abstract: A system for implementing a cyclic digital to analog converter (c-DAC) is capable of supporting a large size liquid crystal display. The system includes an upper DAC stage configured to output a first voltage between a lower voltage supply (HVDD) and an upper voltage supply (AVDD). The system also includes a lower DAC stage configured to output a second voltage between the lower voltage supply (HVDD) and a ground. The upper DAC stage includes a single PMOS switch and the lower DAC stage includes a single NMOS switch.

Abstract: An N-bit digital-to-analog converting device includes: a decoder for converting an N-bit binary digital signal into a multi-bit thermometer code during each cycle of a clock signal alternating between first and second states, N being an integer not less than two; a random number generator for generating a reset signal having at least one high logic level bit and at least one low logic level bit that are equal in number and that have a random, time-varying arrangement; and a converting module coupled electrically to the decoder and the random number generator, and configured to convert the thermometer code into an analog voltage corresponding to the digital signal when the clock signal is in the first state, and to reset the analog voltage to a reset value according to the reset signal when the clock signal is in the second state.

Abstract: A current cell array includes a number of current cell groups arranged such that they extend in a first direction. Each of the current cell groups is identified by a first identifier that increases in a direction of a gradient across the current cell array. A number of current cells are included in each of the current cell groups. Each of the current cells is identified by a respective second identifier that increases in the direction of the gradient across the current cell array. The current cells are positioned in the current cell groups based on the first and second identifiers.

Abstract: In order to reduce a current mismatch by laying-out the bias circuit of current cells adjacent to each other in a common current centroid manner or connecting the output lines of the current cells in a tournament manner, there is provided a digital-analog converter in which a plurality of current cells are two dimensionally and symmetrically disposed according to a previously determined order, the digital-analog converter including: a first current cell group including a portion of the plurality of current cells; and a second current cell group including the rest of the plurality of current cells, not included in the first current cell group, the outputs of each current cell of the first current cell group being connected to the outputs of each current cell of the second current cell group in a tournament manner, wherein each of the plurality of current cells includes: a switch circuit switching the output and block of a unit current according to an input signal; and a bias circuit mirroring current supplied

Abstract: The present invention provides an analog to digital converter by using an exponential-logarithmic model. The exponential-logarithmic analog-to-digital converter includes an exponential circuit which acquires an analog input voltage and generates an analog output voltage that is an exponential function of the input voltage. A positive feedback circuit that succeeds the exponential circuit exhibits a natural logarithmic characteristic. A comparator is connected to the positive feedback circuit to compare an output voltage of the positive feedback circuit with a reference voltage. Via the exponential-logarithmic conversion technique, the time interval or pulse produced by the positive feedback circuit is a linear function of the magnitude of the input voltage. Based on the comparator output, a counter is employed to translate the analog input signal to its digital representation.

Abstract: [Means for Solving the Problem] In a current switch circuit A used for a current steering D/A converter, a current switch basic circuit 1 includes first and second transistors Tr121 and Tr122 included in a differential switch 12. A threshold voltage control circuit 5 has an output terminal Vbout controlling the substrate voltage to be outputted to the substrate terminal of each of the two transistors Tr121 and Tr122 included in the differential switch 12 for controlling the threshold voltage of the two transistors of the differential switch. Accordingly, the present invention improves the decrease in the dynamic range of the current switch basic circuit 1 dependent on the threshold of each of the two transistors in the differential switch 12 and realizes a wider output voltage range without causing deterioration in properties even in a case that the power voltage is reduced in the current switch basic circuit 1.

Abstract: Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.

Abstract: Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative to each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided.

Abstract: A phase interpolator is described. The phase interpolator can have a code-to-bias converter, and a phase interpolation interface. In an embodiment of a code-to-bias converter, a single digital-to-analog converter is provided to generate bias signaling associated with phase signals. A bleeder current source is provided to generate a bleeder current, where the bleeder current is selected responsive to phase so the phase signals do not reach zero current.

Abstract: A background self-calibrated DAC is presented. A virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized.

Abstract: According to one embodiment, an A/D converter includes a determination circuit configured to determine whether a first analog signal is greater than a second analog signal or not, the first analog signal being a present A/D conversion target, the second analog signal being an immediately preceding A/D conversion target, a calculation circuit configured to add a reference voltage to a difference obtained by subtracting the second analog signal from the first analog signal, a generation circuit configured to generate a comparison voltage, a comparator configured to compare a calculated value of the calculation circuit with the comparison voltage, and a conversion circuit configured to convert a period into a digital signal, the period being required until the calculated value is identical with the comparison voltage by the comparator.

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract: Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Additionally, or alternatively, while the portions of the digital signal are being buffered, there can be a determination, based on the buffered portions of the digital signal, of when one or more system related parameters can be adjusted to temporarily reduce power dissipation. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa.

Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.

Abstract: A D/A conversion circuit in accordance with the present invention, which is provided with a switch swD, allows a writing operation of a voltage (a true gradation voltage) to be performed at a higher speed by first applying a first voltage (a voltage close to the true gradation voltage), which is supplied without passing through a resistor element, to an output line and then applying a second voltage (the true gradation voltage), which is supplied via the resistor element, to the output line. Thus, the present invention can provide a D/A conversion circuit capable of writing display data to liquid crystal cells with higher precision at higher speed, and a semiconductor device utilizing such a D/A conversion circuit.

Abstract: A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.

Abstract: An analog-to-digital converter includes a sample and hold unit, a successive control unit, a look-up memory, and a calibrating comparator, which further includes a positive input end, a negative input end, a timing signal input end, a data port, a latch unit, an enable switch, a first controllable resistor, a second controllable resistor, a reset switch assembly, a controllable capacitive device, and an output end.

Abstract: A multi-input operational amplifier circuit operable with a high degree of accuracy and in a small area, a D/A converter using the multi-input operational amplifier circuit, and a drive circuit or driver for a display device, using the D/A converter. In embodiments of the multi-input operational amplifier circuit, a constant current source of a third differential amplifier circuit that causes a doubled constant current i×2 to flow with respect to constant current sources of first and second differential amplifier circuits by application of two types of bias voltages thereto is configured using PMOS of the same number and size. Therefore, operations equivalent to those of a conventional circuit may be realized by the three constant current source PMOSs, and a smaller chip size may be required.

Abstract: An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. The decoder may be used to decode digital values to non-linear GAMMA corrected analog output voltages.

Abstract: An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator.

Abstract: Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled, outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided.

Abstract: In a current steering D/A converter, a 1LSB current source 1 and a 2LSB current source 2 are binary code current sources for outputting currents with current values weighted by ½, and a 4LSB current source 3 is one of a large number of current sources designed as thermometer code current source with the same structure. In first circuits A1, A2 and A4 for respectively determining constant current values of the current sources 1 through 3, a plurality of MOS transistors with a channel length L3 and a channel width W3 are cascode-connected to one another with gate terminals thereof shared. In second circuits B1, B2 and B4 respectively used for setting high output impedance of the current sources 1 through 3, a plurality of MOS transistors with a channel length L4 and a channel width W4 are cascode-connected to one another with gate terminals thereof shared.

Abstract: A differential switch circuit includes a first differential switch basic circuit (1) and a second differential switch basic circuit (2). The first differential switch basic circuit (1) has a first common source node (N1) shared by a plurality of transistors (TP121 and TP122), and the second differential switch basic circuit (2) has a second common source node (N2) shared by a plurality of transistors (TP131 and TP132). The first common source node (N1) and the second common source node (N2) are alternately reset to a predetermined voltage in each clock cycle.

Abstract: The present invention relates to a decoding circuit for a flat panel display, and more particularly to a decoding circuit for a flat panel display wherein a miniaturization is possible by reducing an area of the circuit. There is provided a decoding circuit comprising: a first decoder for selecting a predetermined number of gradation voltages from a plurality of gradation voltages according to a least significant bit or least significant bits of an image data; a second decoder for selecting one of the selected gradation voltages to be outputted to an output terminal according to a plurality of selection signals; and a third decoder for outputting the plurality of the selection signals according to a most significant bit or most significant bits of the image data, wherein a minimum length of gates of a plurality of MOSFETs included in the first decoder is shorter than that of a plurality of MOSFETS included in the second decoder.

Abstract: Portions of a digital signal are buffered prior to being provided to a sub-system (e.g., a segmented DAC of a LDD) that is responsive to the digital signal. While being buffered, there is a determination, based on the buffered portions of the digital signal, of when one or more portions of the sub-system and/or another sub-system can be switched from a first state to a second state, where the second state results in less power dissipation than the first state. Additionally, or alternatively, while the portions of the digital signal are being buffered, there can be a determination, based on the buffered portions of the digital signal, of when one or more system related parameters can be adjusted to temporarily reduce power dissipation. Based on results of the determination(s), the state of one or more portions of the sub-system and/or another sub-system is/are selectively switched from the first state to the second state, or vice versa.

Abstract: A DA converter includes an IV conversion amplifier with output voltage having good linearity, to thus improve total harmonic distortion (THD) characteristics. In the DA converter, a first current path in which current flows due to differential switches being in the ON state in a differential switch section, and a second current path in which current flows due to differential switches being in the OFF state in the differential switch section are connected to the output side of the IV conversion amplifier. A first current flows in the first current path and a second current flows in the second current path. A current equal to the first current plus the second current that is of fixed current amount is drawn by an amplifier stage of the IV conversion amplifier.

Abstract: This disclosure relates to a compensating for nonlinearity resulting from a capacitance feedback in current cells of a single ended digital to analog circuit.

Abstract: Systems and methods to achieve a logarithmic digital-to-analog converter (DAC), which is easy to be implemented, and requiring reduced chip space have been disclosed. The logarithmic DAC is created by a simple and easy to scale linear DAC, which is linearly scaling a predefined voltage range. The output voltage of the linear DAC is converted to a logarithmic current value directly by the voltage-current characteristic of an integrated diode.

Abstract: A method for reducing current consumption of digital-to-analog conversion includes: monitoring logical states of a set of differential digital inputs, wherein the set of differential digital inputs are utilized for controlling at least one tri-state current Digital-to-Analog Converter (DAC) cell of a tri-state current DAC, and the tri-state current DAC cell has a positive output current state, a zero output current state and a negative output current state; and when the logical states of the set of differential digital inputs instruct the tri-state current DAC cell should output no positive/negative current, controlling the tri-state current DAC cell to switch to the zero output current state, temporarily decreasing a direct current passing through a middle path of the tri-state current DAC cell. An associated tri-state current DAC is also provided, where the tri-state current DAC includes: the at least one tri-state current DAC cell; and a control device.

Abstract: A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.