Abstract: Circuits and techniques for controlling gain while performing analog frequency-selective filtering of electronic signals are provided. In particular, these circuits and techniques control gain and filter electronic signals in a way that significantly reduces input-referred noise as the gain increases to accommodate smaller input signals, while operating within reasonable power constraints and employing a minimum amount of die space. Such circuits also significantly reduce the circuitry necessary for performing the combined steps of controlling gain and doing analog frequency-selective filtering of electronic signals.

Abstract: A floating type analog-to-digital converter which is capable of converting an analog signal into a digital signal in a wide dynamic range, while exhibiting stable frequency characteristics due to the presence of symmetric pre-echo and post-echo in the impulse response waveform. An analog signal level adjusting device adjusts the level of an analog signal with different first gains, so as to generate a plurality of analog signals of different levels for analog-to-digital conversion. A plurality of analog-to-digital converters convert respective ones of the plurality of analog signals generated from the analog signal level adjusting device, into respective digital signals, and output the digital signals. A digital signal level adjusting device adjusts the levels of the digital signals with different second gains corresponding to respective inverses of the first gains, and generates the adjusted digital signals, which are then delayed and generated by a delay device.

Abstract: A plurality of amplifiers having different amplification factors are provided and a received signals and amplified output signal are all sampled by A/D converters. A selector selects, from the sampled signal, a signal from which accuracy can be attained exceedingly and is not saturated upon sampling, so that there can be provided an A/D conversion apparatus which does not require AGC control and conversion calculation of data and can obtain desired accuracy. Selection logic can use comparison of maximum values and logical sums of absolute values of the sampled values, levels which are not amplified or the like.

Abstract: Analog-to-digital and digital-to-analog converters are described which have internal reference voltage generators. These voltage generators include circuitry which senses the magnitude of the power supply voltage applied to the chip. The internal reference voltage generators then select one of two internal reference voltages as a reference voltage for the conversion operations depending on the magnitude of the power supply voltage.

Abstract: An apparatus for wide bandwidth analog to digital and digital to analog signal conversion is disclosed. An input/output stage (40) is coupled to an external analog system and includes reference voltages for calibration of the analog to digital (A/D) conversion process. A conversion stage (46), comprising a plurality of A/D converters (ADC) (48, 50) and a digital to analog converter (52), is coupled to the input/output stage and to a digital signal conditioning stage (54) which is coupled to an external digital system. Offset and gain errors in the outputs of each ADC are corrected by the application of appropriate correction parameters in the digital signal conditioning stage. The sampling intervals for each ADC are phased to allow the digital outputs of the ADCs to be interleaved and form a resulting digital data stream with a sampling rate a multiple of that of any one ADC.

Abstract: A code string having a changed compression ratio is regenerated at a high speed. A quantizing accuracy and a normalizing coefficient to be changed are calculated by a quantizing-accuracy and normalizing-coefficient determining circuit without needing to dequantize the generated code. Then, the previously generated code is requantized by a quantized-spectrum calculating circuit in accordance with the calculated quantizing accuracy and the normalizing coefficient.

Abstract: Upon the power-on, a digital signal processing circuit supplies an AGC signal to an AGC amplifier to squelch it substantially, thereby prohibiting an analog signal from being input to an A/D converter 6 via a DC level setting circuit. In this state, a DC level that is set by the DC level setting circuit is A/D-converted by the A/D converter and a resulting value is input to the digital signal processing circuit. The digital signal processing circuit calculates and stores, as a DC offset value, a difference between the received DC level and the center value of the dynamic range of the A/D converter. In a stationary state, the AGC amplifier is caused to operate normally and the offset value is subtracted from data that is supplied from the A/D converter. Resulting data is output from an output terminal.

Abstract: A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter.

Abstract: A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.

Abstract: A method of extending the dynamic range of a receiver in a digital radio transmission system, wherein the receiver receives a radio signal sent from a transmitter and includes an A/D-converter. Exemplary methods according to the present invention include the steps of selecting an upward limit value for the dynamic range of the A/D-converter, determining a minimum accepted signal quality for a radio signal process in the receiver, overextending the A/D-converter so as to exceed the upper limit value, generating a signal quality value downstream of the A/D-converter, comparing the generated signal quality value with the minimum accepted signal quality and limiting the overextension so that the minimum accepted signal quality will be exceeded when the A/D-converter is overextended.

Abstract: A digitizer with increased dynamic range is provided by applying varying gains/attenuations to an input signal and feeding the resulting scaled signals to several conventional analog-to-digital converters to be digitized. The digitized version of the largest scaled signal which does not result in its respective analog-to-digital converter from saturating is selected by a multiplexer to be fed through as the digitizer output. Each of the gains(attenuations) differ by multiples of approximately 6 dB, since one bit in an ADC represents this value. The multiplexer outputs a digital sample size which is larger than that of the analog-to-digital converters and with the selected digitized version being output as the appropriate subset of the larger sample size to account for the gain(attenuation) of the selected signal. Preferably, this is used in a wideband receiver to increase the dynamic range of the receiver.

Abstract: In a high speed video capture and display system including an N.sub.channels channel sensor for producing N.sub.channels parallel analog video signals, N.sub.channels signal processing channels for processing the analog video signals, each of the N.sub.channels signal processing channels including an analog-to-digital converter (ADC) having gain and offset which are controlled by controlling the common mode and differential voltages across each ADC ladder network; and a central processing unit for controlling the gain and offset by means of digital control signals; the method of calibrating the system to produce a uniform image comprising the steps of.a) illuminating the sensor with a broadband and spatially uniform light source to determine L.sub.max ;b) initially setting the common mode and differential voltages of each ADC to nominal settings;c) illuminating the sensor with a spatially uniform broadband illumination N.sub.

Abstract: A simple down converting A/D converter utilizing predictive coding principles. By placing the sampler inside the predictive loop, the predictive loop filter can be implemented using DSP techniques, thus eliminating the complexities introduced by use of discrete-time analog circuitry. Then, by re-mapping the output of the predictive loop filter into the analog domain using a D/A converter, the predictive filter output signal is subtracted from the input analog signal to generate the prediction error signal. Therefore, through directly sampling the prediction error signal and converting the output of the predictive loop filter into analog representation using a low-cost multiple bit D/A, the use of discrete-time analog circuitry is eliminated and the complexity of the converter design is greatly reduced. Various features of the invention are disclosed.

Abstract: A method of breaking up idle tones in a converter is used for gain scaling and summing of digital input signals. The invention achieves this object by introducing dither. Further, the invention optimizes the dither introduced by adapting the magnitude of the dither based on the value of the feedback gain factor of the converter. By adapting the dither in this way, the output idle channel noise can be essentially constant and independent of the scaling factor of the converter.

Abstract: The invention relates to an A/D conversion device intended to supply at the output a digital signal Vout[0:7] resulting from the conversion of an analog input voltage Vin and receiving a control signal CRS used for defining the transfer characteristic of the device by way of comparison with the output signal Vout[0:7]. According to the invention, such a device comprises a reference module (AO, CMP2) which allows adjustment of the digital value of the output signal Vout[0:7] at a predetermined value when the analog input voltage Vin is zero, and means (Mx, Vact) for substituting for said voltage Vin a reference voltage Vref having a predetermined value when the device is in its control mode.

Abstract: A signal processing apparatus includes a device for inputting an analog signal which includes digital information, a converter for converting the analog signal to a digital form, an adder for combining one output of the converter with another output of the converter, a detector for detecting an off-set of the analog signal based on an output of the adder, and a compensator for compensating for the off-set of the analog signal based on an output of the detector.

Abstract: The digital-to-analog conversion apparatus operates to convert an digital input into a corresponding analog output. A digital filter is provided for oversampling the digital input having a varying value represented in the form of multiple bits. A delta-sigma modulator operates to effect delta-sigma modulation of the oversampled digital input to reduce a number of the multiple bits for requantizing the oversampled digital input with a certain S/N ratio. A low-pass filter is provided for converting the requantized digital input into an analog output. A level detecting circuit is provided for detecting when the value of the digital input falls below a predetermined level. A shifting circuit is disposed upstream of the delta-sigma modulator and is responsive to the detected results for increasing the value of the digital input so as to improve the S/N ratio in the delta-sigma modulator.

Abstract: A gain control arrangement for use in analog-to-digital conversion includes a current generator that generates gain currents as a function of externally applied resistances. The gain currents are sequentially provided to the analog-to-digital converter, enabling the converter to use a single set of externally applied resistances to set differentiated gain factors in each of its channels.

Abstract: A tracking analog-to-digital converter (ADC) which incorporates an input device, such as a superlattice, which produces a pulsating output current corresponding to the voltage level of an analog input voltage and an encoding device to provides a unique digital code which can be read to yield an approximation of the analog input voltage level. By simultaneously tracking the analog input voltage, the device operates at higher speeds than previously attainable. The resolution of the new ADC is increased by composing the input device to respond to narrow voltage ranges. When the input device is a superlattice, narrow response ranges are accomplished by composing the superlattice to have an increased number of resonances or by vertically stacking a plurality of superlattices.

Abstract: Apparatus and methods are provided for encoding, storing and decoding auxiliary information on an analog source signal in a way which has minimal impact on the human perception of the source information when the source signal is applied to an appropriate output device, such as a speaker or a display monitor. The autocorrelation function of a host signal is modulated according to the value of an auxiliary information signal by adding a host modifying signal to the host signal. The auxiliary signal is decoded by generating the autocorrelation function of the encoded signal and extracting the auxiliary signal according to well-known signal extraction techniques.

Abstract: In a signal processor according to the present invention, an analog output signal of a measurement apparatus is first amplified by an amplifier, where the gain can be changed. The amplified analog signal is then sampled and converted by an A/D converter to a digital data. When the value of the digital data is smaller than a preset reference value, a gain determining element determines the gain at a larger value, which will be used for the next sampled data. When, conversely, the value of the digital data is larger than another preset reference value, the gain determining element determines the gain at a smaller value so that a signal saturation in the A/D converter will be prevented in the next data sampling.

Abstract: Then circuit includes an analog-to-digital converter (ADC); and one or more switched capacitor amplifier stages connected together in series with a first switched capacitor amplifier stage for receiving the analog input signal, and a last switched capacitor amplifier stage connected to the ADC. Moreover, each of the plurality of switched capacitor amplifier stages preferably has a selectable gain to permit control of an overall gain of the analog input signal upstream of the ADC. In addition, the first stage may also serve as a sample and hold circuit for the ADC. In one embodiment, the circuit may comprise an integrated circuit substrate on which the ADC and the plurality of switched capacitor amplifiers are formed so that the analog-to-digital converter is a monolithic integrated circuit. The circuit may also control the gain of each of the plurality of switched capacitor amplifier stages based upon a digital gain control word.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: An autoranging apparatus and method for an analog-to-digital converter (ADC) which uses a proposed gain detector including a peak of absolute detector and a quantizer to determine a proposed gain, and a amplifier gain setting rule processor in parallel with an anti-aliasing (AA) filter. The rule processor generates a current gain from inputs including the current gain, proposed gain, and a resolution bandwidth (RBW) value. The current gain is used to set a variable amplifier before the signal is sampled & held, and then converted to a digital word via the ADC. A variable bandpass filter can additionally be used before the AA filter to produce a pre-filtered signal. The pre-filtered signal would similarly be processed by the proposed gain detector. The resulting digital word is scaled down again through values stored in a look-up table. The look-up table is generated via a calibration routine which determines with certain precision the variable gain levels for the particular amplifier device used.

Abstract: A system which performs automatic gain control on received audio data. The system comprises an analog adjustable gain amplifier coupled to a digital gain control loop which is preferably a digital signal processor, with an A/D converter and D/A converter interposed between the amplifier and control loop. The invention thus advantageously amplifies the analog input signal before being converted into a digital signal. This results in better performance than prior art system which amplify an already converted to digital signal which may have already been clipped before the signal could be attenuated. The combined digital/analog method provides improved detection of silence to avoid amplifying background noise. The gain control loop comprises a long-term energy averager and gain calculator as well as a short-term energy averager and gain calculator which receive the digital audio output signal.

Abstract: A system which performs automatic gain control on received audio data. The system comprises an adjustable gain amplifier coupled to a gain control loop which is preferably a digital signal processor. The gain control loop comprises a zero-crossing detector which receives the audio output signal and generates a zero crossing output upon detection of a zero crossing. The gain control loop further comprises a gain adjustment scheduler which receives the zero crossing output and a gain adjustment signal. The gain adjustment scheduler advantageously adjusts the gain of the output signal in incremental steps near zero crossings so as to minimize distortion and the possibility of clipping of the input signal. The gain control loop further comprises a voice activity detector which detects substantial voice activity, wherein the automatic gain control system amplifies the audio input signal only during the substantial voice activity.

Abstract: An electronic method and apparatus for signal encoding and decoding to provide ultra low distortion reproduction of analog signals, while remaining compatible with industry standardized signal playback apparatus not incorporating the decoding features of the invention, and wherein the improved system provides an interplay of gain, slew rate and wave synthesis operations to reduce signal distortions and improve apparent resolution, all under the control of concealed control codes for triggering appropriate decoding signal reconstruction compensation complementing the signal analysis made during encoding. In addition, signals lacking the encoding process features of the invention are likewise compatible with playback decoders which do embody the invention, to provide some overall restoration enhancement.

Abstract: The invention relates to a digital processing circuit comprising an analog/digital converter (1) situated at the input of the circuit, a device (2) for the digital processing of the signal emanating from the analog/digital converter and a digital/analog converter (3) situated at the output of the processing circuit. The digital processing circuit comprises means (A2, A3, T, RS, R1) making it possible to control its gain from a single voltage reference (VB). Preferably, the single voltage reference is a bandgap voltage and the circuit is made in CMOS technology. The invention applies to any type of audio or video equipment using such circuits.

Abstract: A multi-range analog-to-digital converter for encoding rundown times into a single channel of pulse width encoded data which may be conveyed to a remote equipment room over a single inexpensive, low quality digital cable. An input charge pulse is divided into multiple charge pulses and rundown times of the divided charge pulses are combined and encoded into a single channel of encoded data. A digital value representation of the input charge pulse is derived from the most accurate rundown times selected from the single channel of encoded data.

Abstract: An high speed apparatus and method for extending a dynamic range of a signal processing device which receives an analog input signal. A peak indicator uses a 90.degree. phase shifter and zero crossing detector to indicate when the analog input signal is at a peak amplitude within each of its cycles, and an analog to digital converter (ADC) samples input signal amplitude when each peak amplitude is indicated to provide a digital control word for each sampled peak. A gain controller adjusts the gain of the analog input signal provided to the signal processing device in response to the digital word. Preferably the ADC calculates log.sub.2 of the sampled peak amplitude so that the digital word is a power-of-two operator, the gain controller compresses the analog input signal by a factor of one over the power-of-two, and the output signal from the signal processing device is thereafter expanded by a data shifter which shifts the output by an amount corresponding to the power-of-two.

Abstract: A method and apparatus for encoding input signals, such as digital data, by so-called high-efficiency encoding, in which pre-echo and post-echo are suppressed. A gain control position decision circuit detects an attack portion and a release portion of an audio signal entering an input terminal. An acoustic model application circuit finds a masking level based on a psychoacoustic model of the input signal. A gain control decision circuit determines the gain control value adaptively selected in accordance with the masking level. A gain control circuit controls the gain of the audio signal entering the input terminal in meeting with the gain control value.

Abstract: The magnitude of analog audio input signal to an analog to digital converter in a digital audio processing system is increased or decreased in response to the magnitude of a sample of the digitized audio signal being found below or above, respectively, an acceptable range of magnitudes of the analog audio input signal. The magnitude of an audio output signal is correspondingly decreased or increased, after a delay equal to the processing delay. Additionally the increase of the magnitude of the audio input signal is delayed by a predetermined period, e.g., five to thirty seconds, during which the magnitude of the audio input signal remains below the acceptable input magnitude range.

Abstract: A gain varying device includes a zero-cross detector for detecting a zero cross or a vicinity thereof in an input analog or digital signal, an analog gain varier for varying the gain of the input analog signal, and a digital gain varier for varying the gain of the input digital signal. In this device, the timing to vary the gain of the analog or digital signal in the individual gain varier is determined in accordance with the zero-cross detection timing, so that smooth switching can be realized in the gain varying operation without generation of any audible noise.

Abstract: A displacement amount detection apparatus detects the displacement amount of an object by utilizing two input signals which have a predetermined phase difference therebetween and are output in correspondence with a displacement of the object. The apparatus includes an amplifier which can arbitrarily set the amplification gains of the input signals, and a gain memorizer for dividing the two input signals obtained upon displacement of the object over a predetermined displacement range of the object into a plurality of displacement periods, and for memorizing the partial amplification gains of the amplifier in units of displacement periods on the basis of signals in the respective displacement periods. In addition, a controller selects the gains memorized in the gain memorizer and sets the selected gains in the amplifier when the amplifier amplifies the two input signals.

Abstract: Analog-to-digital (ADC) output bits are partitioned in a way that simplifies the gain error calculations. Simplification of the gain error calculations allows a reduction in the complexity of the circuits needed to implement automatic gain control (AGC).

Abstract: In an adaptive A/D converting device for adaptively converting an input analog signal (Vin) into an output digital signal (Dout), a reference voltage generating unit (11) generates lower and higher limit reference voltages (Vrl, Vrh) with a predetermined difference voltage (Vd) kept therebetween. A main A/D conversion unit (12) converts the input analog signal into an original digital signal (Dor) having a constant quantizing error. A control section (13) controls the lower and the higher limit reference voltages so that the input analog voltage always lies in an observation allowable range defined therebetween. A modifying section (14) modifies the original digital signal into the output digital signal having the constant quantizing error.

Abstract: A digitizer includes a reference level generator for generating a reference level, a comparator for comparing a signal level of the analog input with the reference level to provide a digitized output, a first detecting circuit for detecting a moderate change in the signal level of the analog input so as to change the reference level in accordance with the detected moderate change in the signal level of the analog input, and a second detecting circuit for detecting a rapid change in the signal level of the analog input so as to change the reference level in accordance with the detected rapid change in the signal level of the analog input.

Abstract: A digital to analogue converter having a plurality of output stages 46. Each output stage 46 includes a tri-state buffer 54 that outputs an on-signal, an off-signal or a pulse width modulated signal PWM that is selected by a multiplexer 52 that operates under control of a chord decoder 50 that is responsive to exponent bits within the input digital signal value. If a pulse width modulated signal is selected, then its duty cycle is controlled by a pulse width modulated decoder 48 that is responsive to mantissa bits within the input digital signal value. A further output provides a pulse width modulated signal of a predetermined duty cycle that may be used as a reference signal to compensate for variations in the operation of the rest of the digital to analogue circuit.

Abstract: A method and apparatus for removing low frequency noise and any offsets common to a plurality of samples of a signal, for calibrating an offset level to be added to the signal to reference the signal to a desired reference level at an output of the apparatus, and for clamping an input voltage level to the apparatus to a desired voltage within an operating range of the apparatus. The apparatus includes a correlated double-sampling circuit which takes a first sample and a second sample of the analog signal, takes a difference between the first sample and the second sample to remove low frequency noise and any offsets common to both sample and which outputs a difference signal. In addition, the apparatus includes a black level correction circuit which adds an offset level to the difference signal to calibrate the offset level to be added to the difference signal so that the difference signal is at a desired reference level at an output of the apparatus.

Abstract: This analog-digital conversion device comprises switching means (CS) having two close and centered triggering thresholds; a NOR logic gate (PL) which, when the conversion device is not being used, receives a standby command signal and delivers a zero digital output signal (NOUT) imposed on the input (NIN) of the switching means (CS); preamplification means (PS); and amplification means (AS) receiving a standby command signal and delivering either the digital output signal (NOUT), in the absence of a standby command, or a zero-value signal in the event of a standby command.

Abstract: A hybrid monolithic IC that is standardized for controlling various types of electrical equipment, such as circuit breakers, motor controllers and the like. The IC is a hybrid monolithic IC, fabricated in CMOS technology. The shortcomings of utilizing CMOS technology for linear or analog circuitry is overcome by the implementation of the IC to provide a hybrid monolithic IC that is relatively less expensive than using multiple IC's or a single IC fabricated from biCMOS technology. Also, by utilizing a single IC, such control and monitoring circuitry can be located in existing electrical equipment. The IC includes an on-board microprocessor, an A/D subsystem and various input/output devices which make it adaptable for use in various types of electrical equipment.

Abstract: A sub-ranging analog to digital converter utilizes open loop differential gain amplifiers and analog switches to implement a pipeline. Each stage of the converter contains two fine range transfer amplifiers, sampling switches and hold capacitors, a low resolution sub-range analog to digital converter and a resistive ladder. The sampling switches behave as a digital to analog converter. Each stage then converts the held analog value to a digital code, which is used to operate the transfer switches to select the proper sub-range result for the next stage. The transfer switches are analog switches that perform the function of both the sampling and the sub-range transfer. The interstage amplifiers are simple open loop differential amplifiers with a rather imprecise absolute gain. Because the reference and the signal are both amplified by this imprecise gain, both the reference and the signal are amplified by the same amount.

Abstract: System for analog-digital conversion of signal using at least two less highly resolving AD converters, each having a different preamplification, wherein the AD converter having the most favorable resolution of the momentary signal is utilized to compute therefrom the digital output signal of the system. The preamplifications do not have to be precisely known, but are determined by means of the digital signals formed by the conversion. Preamplification errors, such as offset errors or transmit time errors, are eliminated by choosing the appropriate computation algorithm.

Abstract: A current/voltage configurable I/O module is provided for a programmable logic controller. The I/O module includes first and second D/A converters which are cascaded together such that a data stream provided to the first D/A converter flows through to the second D/A converter. Each of the D/A converters includes a respective current output, a voltage output and range/mode select inputs. A serial to parallel shift register is coupled between a microprocessor data output and the data input of the first D/A converter such that information from a data stream supplied by the microprocessor is passed in serial fashion to the first and second D/A converters. The shift register also includes parallel outputs, namely range/mode select outputs, to which range/mode select information from the data stream is provided.

Abstract: An analog-to-digital (A/D) converter circuit in which an extracted envelope of an input signal is used as a reference signal on an analog-to-digital converter, providing a wide dynamic range while avoiding the need for automatic gain control. Specifically, the A/D converter circuit includes a rectifier for rectifying an analog input signal, a filter for filtering a rectified analog signal output from the rectifier to provide a signal envelope used as the reference signal, and an analog-to-digital converter for converting the analog input signal into a digital signal within a range, the range being dynamically set in accordance with the reference signal provided by the filter.

Abstract: A voltage mode digital-to-analog converter (DAC) with an output buffer operational amplifier is provided with a rail-to-rail output voltage capability by reducing the DAC's output voltage swing to a range that is within the amplifier's permissible input signal range, and connecting the amplifier in a multiplier configuration to produce a corresponding multiplication of its input signal. The DAC output reduction is preferably achieved by delivering an n-bit input digital signal to an n+m bit DAC, and holding the DAC's m most significant bits OFF. The m most significant bits are dummy bits that are impedance matched with the DAC, while the amplifier is an operational amplifier with a feedback circuit that is also impedance matched to the DAC.

Abstract: A gain compensating differential reference circuit that is used to match the gain of an input differential amplifier, and track and hold circuit at the input of an analog-to-digital converter. The gain compensating differential reference circuit includes a single-to-differential converter to convert a V.sub.REF signal into a V.sub.REF+ and a V.sub.REF- signals whose difference equals the full-scale range of the differential analog input to the A/D converter, a gain matching differential amplifier to process to the differential output of the single-to-differential converter, and a gain matching track and hold circuit to process the output of the differential amplifier. The output of the gain matching track and hold circuit has the same gain and full-scale range as the analog signals processed by the input circuitry of the A/D converter along the analog path.

Abstract: A symbol detector (110) includes an analog-to-digital converter (115) for converting signal voltages to digital values and peak and valley counters (310, 315) for tracking the digital values to determine peak and valley values associated with high and low voltages of the signal. The symbol detector (110) further includes calculation circuitry (356) for calculating upper, lower, and center thresholds based on the peak and valley values and a decoder (125) for generating data symbols in accordance with the upper, lower, and center thresholds.

Abstract: Before actually reading a document image, white reference data corresponding to a pure white document image is found in an AGC processing unit 32, and is set in a register 32a. In a CPU 33, data corresponding to the white reference data set in the register 32a is produced. The produced data is set in a register 32b. The set data is applied to a D/A converting unit 34, where the data is converted into analog data, after which the analog data is applied as a low reference voltage V.sub.ref L to an A/D converting unit 31. As a result, the maximum amplitude range of the analog image data becomes approximately the same as the input voltage range. Accordingly, AGC processing can be realized in a digital manner, thereby to make it possible to simplify the circuit arrangement, as compared with the conventional circuit arrangement, and to easily make fine adjustment.

Abstract: Receiver dynamic range is improved while maintaining system processing fidelity by placing a processor control attenuator in front of the synchronous detector or other circuitry and A/D converter circuits. This is followed by a digital circuit which reinserts the attenuation that was taken out previously to maintain signal processing fidelity. The control for the attenuator function is from the processor and is determined by looking at the prior pulse repetition intervals (PRIs) of the radar system data and determining from that data what attenuator value to use for the next PRI. This is done for each range bin to be processed.