Abstract: The subject invention addresses the problem of aliasing in subsampled data by adding dither to the timing of the subsampling of the data. The subject invention solves a speed problem caused by delays in modifying (i.e., dithering) the A/D converter sampling clock. It is herein recognized that to maintain a high acquisition rate one should randomly select (i.e., dither) samples after demultiplexing the data into a wider and slower stream of samples, rather than attempting to modify the high speed A/D converter sampling clock.

Abstract: An interface module includes a high density analog interface (HAI) for electrical interconnection between a programmable logic controller (PLC) and an analog to digital converter (ADC) or a digital to analog converter (DAC). The HAI includes a single application specific integrated circuit having a data scaling function block, a diagnostics function block configured to verify functionality of said scaling function block, a self-calibration function block configured to compensate for drift in said ADC, and a shared interface function block configured to electronically connect said module with a programmable logic controller (PLC).

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

Abstract: A method and apparatus for processing pulse code modulation (PCM) data that do not reach the full dynamic range of a transmission bus. The method and apparatus provide an output processed PCM data having the maximum peak signal allowable by a transmission bus. The output signal limitation is also dependent on a sampling or recording frequency of input signals. In view of the sampling or recording frequency, the invention scales the processing of the PCM data accordingly.

Abstract: The most appropriate data of a plurality of level-converted digital data, obtained by level conversion of the input digital data by different conversion factors, is selected based on a signal quality of each of the level converted digital data. The other data of the level-converted digital data is attenuated to or below a predetermined noise level. Switching between previously selected data and newly selected data is effected by cross-fading. The level-converted digital data are D/A converted to respective analog signals.

Abstract: An optical sensor array with zone-programmable gain and offset prior to A/D conversion for reducing quantization noise. The circuit comprises a register file which contains digital words for controlling gain and offset according to multi-pixel zones.

Abstract: A digital-signal forming circuit demodulates a time-divisionally received signal, and shapes the demodulated signal by comparing the demodulated signal with a reference voltage. When a non-receiving time slot has a small interference signal, the digital-signal forming circuit uses, as the reference voltage, a direct-current voltage obtained by averaging the demodulated signal. When the non-receiving time slot has a large interference signal, the digital-signal forming circuit uses a predetermined direct-current voltage as the reference voltage.

Abstract: A servo controller for correcting a read position of a head when reading data recorded on a recording medium. In accordance with the amplitude ratio of data signals read from each segment of a servo section defined on a recording medium, the servo controller generates an AGC signal corresponding to the next segment before reading the next segment. The data signal read from a phase detection segment of the servo section is amplified to an amplitude greater than the predetermined determination range. The amplified data signal is converted to a two-value digital signal in accordance with the determination range. The phase used during servo control is calculated in accordance with the digital signal.

Abstract: A PLC device of the invention includes an input part 11 that can be connected to a temperature sensor 30, which can output an voltage value depending on a temperature of an target object. A voltage amplifier 12 is connected to the input part 11. A switch 13 can be selectively connected to one of the input part 11 and the voltage amplifier 12 to be switched to one of a voltage value from the input part 11 and a voltage value from the voltage amplifier 12. An A-D converter 14 is connected to the switch 13 in such a manner that the one of the voltage value from the input part 11 and the voltage value from the voltage amplifier 12 is inputted to the A-D converter 14 and converted into a digital value by the A-D converter 14. A temperature obtaining part 15 is connected to the A-D converter 14 and can obtain a temperature of the target object from the converted digital value.

Abstract: A mode selection method for signal analyzers having alternative swept and Fast Fourier Transform (FFT) modes of operation enables tradeoffs between measurement speed and dynamic range to be optimized in selecting between the alternative operating modes. The method includes setting the signal analyzer to either a manual state or an automatic state according to a first input to a user interface. When the manual state is set, the analyzer is operated in either the swept operating mode or the FFT operating mode according to a second input to the user interface. When the automatic measurement state is set, a third input to the user interface determines whether measurement speed or dynamic range is optimized. Measurement speed is optimized according to a first optimization scheme and dynamic range is optimized according to a second optimization scheme.

Abstract: A digitizer with increased dynamic range is provided by applying varying gains/attenuations to an input signal and feeding the resulting scaled signals to several conventional analog-to-digital converters to be digitized. The digitized version of the largest scaled signal which does not result in its respective analog-to-digital converter from saturating is selected by a multiplexer to be fed through as the digitizer output. Each of the gains(attenuations) differ by multiples of approximately 6 dB, since one bit in an ADC represents this value. The multiplexer outputs a digital sample size which is larger than that of the analog-to-digital converters and with the selected digitized version being output as the appropriate subset of the larger sample size to account for the gain(attenuation) of the selected signal. Preferably, this is used in a wideband receiver to increase the dynamic range of the receiver.

Abstract: An auto-ranging digital densitometer, for determining the optical density of a test sample, includes a photodetector and a digital logarithmic converter. Within the logarithmic converter, an amplifier circuit is adapted to produce an output signal proportional to intensity of light incident on the photodetector. The amplifier circuit has multiple gains that successively increase, one to the next, by a ratio between 2.3:1 and 5.7:1. Gain select logic selects the gain to provide good density resolution and avoid amplifier saturation. An analog-to-digital converter is adapted to convert the output signal of the amplifier circuit to digital format. A lookup table address is formed at least in part from the output of the analog-to-digital converter. The lookup table outputs at least the lower-order digits of the density value corresponding to the gain and the amplifier output. Density range is extended, resolution improved, and the requirement for a second lookup table is eliminated.

Abstract: The invention relates to a method and an apparatus for implementing automatic gain control in a system where an analog signal is converted into a digital signal. The apparatus comprises means (208) for performing automatic gain control of the adjustable signal in an analog manner using a gain control step of predetermined size and means (446, 448) for performing inverse gain control of the digitized signal in such a way that, after the digital adjustment, the power of the signal is the same as before the analog adjustment. To enable an accurate gain control, the apparatus further comprises means (410, 412, 214, 420) for determining the maximum energy of the signal during a predetermined measurement period, means (426, 428) for comparing the determined maximum energy to preset threshold values (430, 432), and means (436) for performing an automatic gain control of the analog signal and a compensation for the gain control to the digital signal, if the measured value exceeds the threshold.

Abstract: A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g. ADCs and DACs) in the CMOS integrated circuit.

Abstract: Systems and methods for providing analog to digital conversion with improved dynamic range. Multiple low cost analog to digital converters may be used in parallel to provide the dynamic range of a single high resolution analog to digital converter that would otherwise be available only at very high cost. One application is an orthogonal frequency division multiplexing (OFDM) digital receiver which requires high dynamic range analog to digital conversion for accurate reception.

Abstract: A signal processor circuit which receives an input signal and two control words and is programmable to vary the level and the output voltage range of the output signal is provided. The signal processor includes a converter circuit and a level circuit which provide the output circuit with intermediate signals based on input control signals, e.g., input digital words. The output circuit receives an additional control signal and the intermediate signals and is programmable to modify the output voltage range and level of the output signal based on the additional control signal, e.g., a digital word.

Abstract: A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.

Abstract: An analogue frontend, such as is used, for example, in receivers for communications equipment, comprises a plurality of analogue components (1-3) which are connected upstream of an analogue/digital converter (4). In order to control the drive level of the individual analogue components (1-3) precisely, the input of the analogue/digital converter (4) can optionally be connected via a switch-over device (8) to the output of any one of the analogue components (1-3) and a drive level control signal for the respective analogue component (1-3) can be generated by a digital control device (5) by evaluating the sampled value which is then supplied by the analogue/digital converter (4).

Abstract: An interface circuit for converting a digital signal to an analog signal. The interface circuit includes a time response adjustment circuit, a modulator, and a filter. The time response adjustment circuit receives the digital signal and generates an adjusted signal. The modulator couples to the time response adjustment circuit, receives the adjusted signal, and generates a modulator signal. The filter couples to the modulator, receives the modulator signal, and generates the analog signal. The analog signal has a time response that is modified by the time response adjustment circuit. In an embodiment, the time response adjustment circuit includes a gain element, a delay element, and a summer. The gain element receives and scales the digital signal by a scaling factor. The delay element receives and delays the digital signal by a time delay.

Abstract: An automatic gain control circuit for an analog to digital converter is provided. The automatic gain control circuit includes an input, coupled to an output of the analog to digital converter, to receive samples output by the analog to digital converter. The automatic gain control circuit also includes a digital to analog converter that is coupled to selectively adjust a magnitude of an input signal for the analog to digital converter. The automatic gain control circuit also includes a microcontroller. The microcontroller is coupled to the input and the digital to analog converter. The microcontroller is programmed to generate a feedback signal for the digital to analog converter to control the amplitude of the input to the analog to digital converter.

Abstract: A signal processing apparatus having: a plurality of circuit blocks each circuit block including a signal source and an output transistor adapted to receive a signal generated by the signal source at a control electrode region and output a corresponding signal from a main electrode region; and an analog/digital converter circuit adapted to sequentially process the signal from each of the plurality of circuit blocks, wherein the analog/digital converter circuit includes a reference transistor for receiving a reference level at a control electrode region and outputting a corresponding signal from a main electrode region and a digital output circuit for outputting a digital signal in accordance with a signal output from the output transistor and a signal output from the reference transistor, and wherein the output transistor and reference transistor constitute an input unit of a differential amplifier circuit including the output transistor and reference transistor.

Abstract: An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis.

Abstract: An analog-to-digital converter circuit has pre-sample and hold circuit for acquiring and temporarily storing a supplied analog input signal, and for outputting the temporarily stored input signal, at least two signal paths, which are arranged downstream relative to the pre-sample and hold circuit and which are switched in parallel with one another, the temporarily stored input signal sample from the pre-sample and hold circuit being subjected to respective fixed amplifications, which are different from one another, in said signal paths and a selection circuit arranged downstream relative to the signal paths for through-connecting only one of the signal paths, dependent on the respective signal levels, to an analog-to-digital converter that is arranged downstream relative to the selection circuit.

Abstract: A D/A conversion system includes means (18) for arranging a stream of digital samples into frames, each frame including a guard time period. Means (52) are provided for determining a measure of the overall magnitude of digital samples in each frame. Means (50) increase the magnitude of all samples of frames that have a measure that falls below a predetermined threshold by shifting the samples a common number of bits. A D/A converter converts frames with shifted and frames with unshifted samples. An attenuator (54) attenuates the D/A converted samples of frames with shifted samples to compensate for the magnitude increase.

Abstract: The present invention relates to an automatic gain control circuit in which the automatic gain control function is performed entirely in the digital domain. In an illustrative embodiment, the digital automatic gain control circuit for an image sensor having associated therewith an analog-to digital (A/D) converter for converting analog electrical signals from the image sensor to corresponding digital codes, includes a min/max detector for determining minimum and maximum electrical signal values from the digital codes of the A/D converter for each frame of image. A filter coupled to the min/max detector dampens instantaneous changes of the minimum and maximum values by filtering to provide filtered minimum and maximum values.

Abstract: A gain ranging AD converter is provided having two separate gain paths. There is provided a low-gain path and a high-gain path. The low gain path is processed through an analog modulator (333) and then through a filter section to provide on an output of a high-pass filter (339), a low-gain signal which is then compensated for in an equalizer section (347). This equalizing section (347) calibrates the output signal to ensure that the difference between the calibrated signal and the high-gain signal differs only by the fixed gain between the two paths. The high-gain path also includes a modulator (335) for processing through a filter section to provide on the output of a high-pass filter section (343) a high-gain signal. A calibration generator (361) is utilized to generate the parameters for performing the equalization.

Abstract: An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Abstract: A/D conversion of a current input is performed with integrate-and-fire spiking neurons. Techniques that upcount or downcount the number of spikes fired by one neuron in a time period established by another neuron yield quantized estimates of analog charge residues created by the input current. Recursive application of alternate upcounting and downcounting operations yields successively finer quantization estimates that are terminated by an error-correction operation to obtain the least significant bit of the conversion. A spike-based hybrid state machine (HSM) employing both analog and digital elements is configured to create a 2-step or a successive-subranging analog-to-digital converter. The speed of the conversion is augmented in a pipelined topology. In the HSM, a spike-triggered finite state machine (FSM) controls the input currents to the spiking neurons and is in turn controlled by spikes arising from these neurons.

Abstract: A method and apparatus for adjusting the amplitude of a received discrete multi-tone analog signal contaminated by radio frequency interference from radio stations in the AM band are described. The amplitude is adjusted by controlling an analog gain controller in order to utilize substantially all of a dynamic input range of an analog-to-digital converter to reduce the quantization noise of the output digital signal. Data discrimination is truly improved and the capacity of usable discrete multi-tone channels is increased.

Abstract: A sigma-delta analog-to-digital (A/D) converter has an analog modulator, and an adjustable reference voltage circuit that provides a reference voltage to the analog modulator along a feedback path during A/D conversion. The reference voltage circuit includes a reference voltage generator that provides a plurality of positive and negative polarity signals to a gain multiplexer. The gain multiplexer selectively supplies a pair of positive and negative polarity signals to the analog modulator based on a select signal produced by a gain register and a microprocessor interface bus that together allow adjustment of the range of operation and performance of the sigma-delta A/D converter. This adjustment is made based on a particular application in which the converter is implemented; as the relative input power of an input signal changes, the sigma-delta A/D converter as dynamically adjusted, realizes higher performance.

Abstract: A variable gain coder-decoder is provided. The variable gain coder-decoder includes a variable gain amplifier in which the amplification gain may be adjusted in one-decibel steps. An analog to digital converter is connected to the variable gain amplifier. The analog to digital converter receives the amplified output of the amplifier, and performs an analog to digital conversion of the amplified output.

Abstract: A circuit is provided for rectifying and amplifying an AC input waveform to optimize the dynamic range of downstream circuitry, such as an analog-to-digital converter. The circuitry includes an inverting amplifier and a non-inverting amplifier. The inverting amplifier includes a selectable resistance network in a feedback loop that permits the gain to be adjusted by appropriate selection of conductive states of solid state switches. The non-inverting amplifier includes a selectable resistance network on an input line. A control circuit, such as a microprocessor, monitors the output of the A/D converter and controls the conductive state of switches in the feedback and input networks to maintain the digital output within a desired portion of the dynamic range of the A/D converter. Several discrete gains may be provided and programmed in accordance with a predetermined selection scheme.

Abstract: Device (200; 500) for minimizing the quantization noise in conversion between analogue and digital form of a multi-carrier signal comprising an AC component (VAC) with a particular RMS value (VRMS). The device comprises means (230; 530) for converting between analogue and digital form with a limited number (b) of bits within a quantization range (±VQR), means (215,235,245,255; 520) for minimizing the noise by creating an ideal ratio (VQR/VRMS) between the quantization range and the RMS value of the AC component, and means for reducing unwanted DC components in the signal and centering the signal by the wanted DC components being placed in the centre of the quantization range.

Abstract: A mixed signal codec includes: a multiplexer amplifier 24 having an analog output signal; a sigma-delta analog to digital converter 26 having an input coupled to the analog output signal; and a clipping circuit 40 and 42 coupled to the input of the analog to digital converter for clipping the analog output signal.

Abstract: An automatic gain controller for reducing the required code size and processing burden of a digital signal processor (DSP) chip. The automatic gain controller includes an automatic gain control (AGC) amplifier and an A/D converter for converting an analog signal output from the AGC amplifier to a digital signal. A power estimator estimates a power of a signal input from the A/D converter. An infinite impulse response (IIR) filter filters the power output from the power estimator to attenuate noises and interferences. A comparator receives the filtered power output from the filter and generates an AGC control gain. A dB-to-D/A input converter converts the AGC control gain output from the comparator to a D/A input signal. A D/A converter converts the D/A input signal output from the dB-to-D/A input converter to an analog AGC control signal and provides the AGC control signal to the AGC amplifier.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: A clock generator for a PRML read channel for producing a clock signal with minimal jitter from an input signal subject to baseline wandering. The clock generator including a VGA amplifier, a low pass filter, an ADC, a baseline wander correction circuit, a timing offset detector and loop filter circuit, a DAC and a VCO. The VGA amplifier amplifies the input signal to produce a first analog signal. The low-pass filter filters the first analog signal to produce a second analog signal. The ADC converts the second analog signal into a first digital signal, operating synchronously with the clock signal. The baseline wander correction circuit reduces jitter in the clock signal caused by baseline wandering of the input signal. The baseline wander correction circuit produces a second digital signal from the first digital signal, operating synchronously with the clock signal. The second digital signal experiences substantially less baseline wandering than the first digital signal.

Abstract: Analog modulator circuitry 401 includes an integrator 707. First switched capacitor circuitry 710, 711, 713, 714 selectively samples a first amount of charge from a feedback signal and couples that first amount of charge to the first and second inputs of the integrator. Second switched capacitor circuitry 711, 714, 716, 717 selectively samples a second amount of charge from the feedback signal and couples that second amount of charge to the first and second inputs of the integrator stage to selectively compensate for an offset of an input signal to the integrator with respect to a reference voltage.

Abstract: A D/A conversion apparatus includes a DSP which receives and converts input digital data with different conversion factors, to generate a plurality of digital data having different levels, selects one of the plurality of the generated digital data, depending upon the signal quality of the input digital data, while attenuating the other digital data to be lower than a predetermined noise level. A plurality of D/A converting devices convert the respective generated digital data into corresponding analog signals. A re-converting device converts the level of each of the analog signals into an original level, based on a corresponding one of the conversion factors with which the input digital data is converted by the DSP. An adding device adds the re-converted analog signals.

Abstract: A system and a method for calculating a value for the “Band Zero” (B∅) contribution to the processing of a digital signal by processing the separate parts of the signal at separate times. The method increases operating speed of a feedback circuit, for example, by providing a processing path (402f) that is not on the main high-speed processing path of a system such as a read channel of a disk drive. By processing the most time-consuming determination “in parallel,” the high-speed portion of processing is able to maintain an optimum throughput. The method also lends itself to processing in those applications where more than one mode is used. For example, when used in a read channel (113) of a disk drive (100) employing a FIR filter, three modes are desired: FIR-bypass, acquisition, and data tracking.

Abstract: Disclosed is an analog to digital converter with several cascade-connected interpolation and selection circuits. The function of an interpolation circuit is to produce five pairs of output signals from three pairs of input signals and select three pairs from among the five pairs to apply them to the next stage. Each pair comprises two interpolation signals that vary symmetrically and monotonically as a function of the voltage Vin, the signals of one pair being equal when the voltage Vin is equal to a reference voltage associated with this pair. There are five reference voltage associated with the five pairs. Among these five reference voltages, the three reference voltages (and therefore also the three corresponding pairs of signals) that most closely surround the input voltage Vin are selected. The reference voltages are increasingly closer together as the operation progresses in the succession of cascade-connected stages.

Abstract: The analog-to-digital converting circuit apparatus of the invention is intended to realize both low voltage operation and high speed operation of an analog-to-digital converting circuit without impairing the precision characteristic. In plural boosting circuits, voltages higher than each supply voltage are generated. These plural boosting circuits are controlled as the control timing is sequentially shifted by the controller. The boosted voltages delivered from the plural boosting circuits are accumulated in the capacitor, and supplied into the analog-to-digital converter. In the analog-to-digital converter, at the timing other than the changeover timing of the converting action of the analog-to-digital converter, the plural boosting circuits are changed over sequentially, and the boosted voltages are converted from analog to digital values.

Abstract: A target specific folded analog to digital converter (ADC) is provided, such as for use in a data detection channel in a direct access storage device (DASD). The high speed analog to digital converter (ADC) includes a digital signal decoder for decoding specific target levels of an analog signal. An analog to digital converter section of the ADC converts an analog error signal of the analog signal to digital decoder outputs representing the analog error signal.

Abstract: A circuit checks the value and the existence of an external load of a digital-to-analog current converter. A first comparator compares a digital word to be converted, with a comparison data word. The output signal of the first converter indicates during which periods the digital data word is greater and during which periods it is smaller than the comparison data word. A second comparator compares the voltage at the output of the converter with a reference voltage. The output signal of the second converter indicates during which periods the output voltage is greater and during which periods it is smaller than the reference voltage. A comparison circuit checks the existence and the value of the output load by comparing the time periods indicated by the output signals of the two converters. Thus, a conclusion about the existence and the value of the output load is possible at any time.

Abstract: A non-linear digital-to-analog converter includes: a k bit parallel input; a decoding circuit having M inputs connected to M most significant bits of the parallel input, the decoding circuit being arranged to connect first and second consecutive reference inputs among 2.sup.m +1 reference inputs to first and second outputs, respectively, where M>m; and a variable resolution linear digital-to-analog converter having first and second reference inputs connected to the first and second outputs of the decoding circuit, respectively, and further having N digital inputs connected to N least significant bits of the parallel input, where (M+N)>k.

Abstract: A trimming circuit for a gain stage in a pipeline analog-to-digital converter includes an amplification stage (30) having associated therewith on one input thereof a coupling capacitor (38). In parallel with the coupling capacitor is provided a trimming network. The trimming network includes a series configuration of a coupling capacitor and a plurality of trimming capacitors, which trimming capacitors can be disposed in parallel with each other. Each of the trimming capacitors has associated therewith a switch which allows them to be selectively disposed in series with a coupling capacitor (42) and in parallel with each other. This trimming network is connected in parallel with the sampling capacitor (38). The input to the amplifier is isolated from the trimming network with a buffer (62) which is operable to isolate the impedance of the trimming capacitors from the input and from preceding stages.

Abstract: A receive path implementation for an intermediate frequency (IF) transceiver is disclosed that provides increased signal processing integrity and accuracy with an efficient and improved design. A complex filter for a bandpass delta-sigma analog-to-digital converter (ADC) provides efficient complex noise shaping with a combination of real and complex filters. An automatic gain control (AGC) amplifier provides a constant bandwidth and zero variation phase shift for all gain levels. Clock adjust circuitry provides a clock signal with a jitter-free edge and a high percentage duty cycle. A fixed-gain input amplifier provides a matched input impedance. A method for choosing design specifications provides improved anti-aliasing properties.

Abstract: The present invention is an apparatus and method for blind automatic gain control in a digital communications device. The present invention includes a maximum error detector (MED) (142) which includes a gain error evaluator (GEE) (144) and a maximum value detector (MVD) (146). Also included is a decision gain adjustor (DGA) (148) which includes a gain value controller (GVD) (150) and an initial value buffer (IVB) (152). The GEE (144) is operable to generate a gain error signal in accordance with an input baseband signal (x) and a sliced version of the input baseband signal (x'). The MVD (146) is operable to generate a renew signal in accordance with the sliced version of the input baseband signal (x') and a first predetermined reference value. The GVD (150) is operable to converge the gain error signal (.DELTA.x) in a first state using a first convergence technique and to converge the resultant signal in a second state using a second convergence technique.

Abstract: The invention provides methods and apparatus for improving the full-scale accuracy of an oversampling analog-to-digital converter. In particular, an improved switched-capacitor subtractor/integrator circuit is described that effectively provides a desired capacitor ratio by using N+M distinct unit capacitors that each sample an input signal a first predetermined number of times and sample one or more reference signals a second predetermined number of times, where the ratio of the first predetermined number to the second predetermined number is the desired capacitor ratio N/M.

Abstract: A D/A converting apparatus for converting a digital signal into an analog signal, wherein the reference signals of the maximum value and the minimum value of a main D/A converter are generated by the other two D/A converters, whereby the output voltage can be digitally adjusted and the accuracy of the output signal is improved.