Abstract: In an analog/digital converting circuit, when an analog input voltage exceeds a reference voltage, the analog input voltage is modified into analog voltages not exceeding the reference voltage, and comparison voltages generated by dividing the reference voltage are compared with the modified analog voltages.

Abstract: A resolution enhancer circuit provides an increased resolution capability for an A/D converter. The resolution enhancer circuit receives as input an analog input signal having a range greater than the effective range of the A/D, and prescales the input signal to a range that is within the common mode range of op amps used within the resolution enhancer circuit. The input signal can also have a range much less than the effective range of the A/D, and then it would be increased by the prescaler to be within an operable range of the A/D. The prescaled signal is provided to a sampling circuit, which samples the prescaled signal at times determined to be near-saturation conditions of the A/D. A magnified difference between the prescaled signal and the sampled signal, biased to the sampled signal, is then input to the A/D, which determines a number of A/D counts based on that value.

Abstract: An apparatus converts m-bit digital data having a scale factor of K.sub.1 to n-bit digital data having a scale factor of K.sub.2. The apparatus comprises a digital to analog converter which receives the m-bit digital data, for outputting a first analog signal representative of a value associated with the m-bit digital data. An amplifier receives the first analog signal multiplies it by a factor, and outputs a second analog signal. The factor of the amplifier is K.sub.2 /K.sub.1, such that the second analog signal has a value with the scale factor of K.sub.2 associated therewith. An analog to digital converter receives the second analog signal, and converts the second analog signal to the n-bit digital data. The n-bit digital data has the scale factor of K.sub.2 associated therewith, the value representative of the n-bit digital data being essentially equal in the example of the present application to the value representative of the m-bit digital data, however, this is not always a requirement.

Abstract: This invention relates to a circuit for converting an analog audio signal to a highly resolving bit stream. An audio signal (U.sub.In) is converted on several parallel paths (1, 2) having different amplitude sensitivities into a data stream, where the offset of the individual paths (1, 2) is compensated for individually. Subsequently the amplification difference produced by the different amplitude sensitivities is determined and compensated for, so that one of the two data streams is made available as a bit stream for further processing. The selection of the data stream which is made available as a bit stream for further processing, is determined based on the amplitude of the audio signal (U.sub.In).

Abstract: In order to digitize with sufficient resolution an analog signal, which may be generated by a photodetector in a spectrophotometer, an improved analog to digital conversion system is provided having an integrator stage, an analog to digital converter, a microprocessor and interface circuits for providing communication between the microprocessor and a host computer. The integrator may include an operational amplifier with a capacitor in feedback relationship therewith for providing an output which varies linearly as function of time. The microprocessor operates the analog to digital converter to sample the integrator output at successive increments of time which increase in accordance with a binary relationship to an increment corresponding in binary value to the desired upper end of the resolution range. The digitized samples from the analog to digital converter are compared with a predetermined value in the upper end of the amplitude range of the converter.

Abstract: A method and circuit for improved digitization of waveforms having a large dynamic range, including selecting a signal threshold value which partitions the dynamic range of the waveform into a small signal region and a large signal region; sampling the waveform to obtain a sampled signal therefrom at a given sampling frequency; for each sampled signal, comparing the sampled signal with the signal threshold value to determine whether the sampled signal is within the small signal region or the large signal region; and directly digitizing the sampled signal if the sampled signal is within the small signal region or differentially digitizing the sampled signal if the sampled signal is within the large signal region, wherein differentially digitizing the sampled signal includes digitizing a value representing the difference between the sampled signal at a present sampling instant and a previous sampling instant.

Abstract: A high frame rate camera includes;a multi-channel sensor array for producing a plurality of parallel analog image signals representative of a sensed image;a plurality of analog-to-digital converters (ADC) for converting each of the parallel analog image signals to parallel digital image signals, wherein each of the ADCs has a fine gain parameter which is a function of a top ladder potential and also has a fine offset parameter which is a function of a bottom ladder potential; anda control for controlling the fine gain and offset parameters of each of the ADCs by means of fine gain and offset control signals which are a function of desired average output black and gray levels of the image signal.

Abstract: A successive approximation A/D having dual comparators for allowing a larger range of analog input signals to be converted into digital form. One comparator is an N-channel device, and the other comparator is a P-channel device. The A/D switches to either the N-channel device or the P-channel device based upon whether the first two comparisons determine the most-significant bit and the next-most significant bit are a "11", in which the N-channel device is selected, or anything else, in which the P-channel device is selected. Switching circuitry is included to output the proper comparator based on these two comparisons.Control circuitry is also provided to allow for successive conversions using only a single address read. A one-half clock cycle reset occurs at the start of every MSB comparison for every n-bit read, and this reset goes to every component in the A/D except the latch for the LSB, which must be held for at least one more clock cycle before since it has not yet been output to the data bus as yet.

Abstract: In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.

Abstract: A data storage apparatus and method that allows the signal processing circuit to be in integrated form, so that the magnetic storage system may be reduced in size with increased performance is described. The apparatus includes a reproducing head that reproduces information stored on a recording medium, a preamplifier that amplifies the output of the reproducing head, and a low-pass filter. An A/D converter converts the output for the low-pass filter to a digital signal and has a reference voltage. A discriminator is coupled to an output of the A/D converter and discriminates the digital signal. A circuit, coupled to the discriminator, provides negative feedback control of the reference voltage of the A/D converter as a function of the digital signal before the discrimination by the discriminator and the digital signal that has been discriminated by the discriminator.

Abstract: For converting a high-frequency analog signal, which is modulated by a modulation signal, an analog-to-digital converter circuit included a first analog-to-digital converter which is preceded by an amplifier having controllable gain, and which is followed by a controllable divider. A quantization unit generates control signals from the analog input signal for setting the gain of the controllable gain amplifier and for setting the divisor of the controllable divider. The quantization unit includes a second analog-to-digital converter which digitizes the analog input signal a rate approximately corresponding to the sampling rate of the first analog-to-digital converter. The second analog-to-digital converter is followed by a rectification unit which rectifies the signal digitized by the second converter. The rectification unit is followed by a coder which generates an output which increases with increasing momentary amplitude of the rectified signal.

Abstract: The invention concerns a processing circuit (2, 120) for producing a variable output signal in response to a variable quantity picked up or received as input. The processing circuit is associated with a stage or has an input sensor (4, 100) furnishing a signal with a variable amplification/attenuation factor, and further exhibits response characteristics which depend in particular from state variables. The processing circuit includes a suppression circuit (FIG. 5, FIG. 6) for suppressing transients normally produced by modification of the amplification/attenuation factor, this suppression circuit functioning by modifying the value of the state variables in direct proportion to the modification of the amplification/attenuation factor.

Abstract: An electronics circuit for accurately digitizing an analog audio, video or ike data signal into a fourteen bit digital equivalent signal/words having thirteen data bits and a sign bit and then introducing a dither component into the digital equivalent signal. The circuit includes a first Electrical Erasable Programmed Read Only Memory which generates a dither component to be added to a selected, five, six, seven or eight bits of each fourteen bit digital equivalent sample. The circuit also includes an automatic gain control circuit and a data selector circuit which, in combination, select the five, six, seven or eight data bits of the thirteen data bits of each digital equivalent sample to supply to a binary adder. The binary adder then adds the dither component to the selected data bits of each digital equivalent sample. The five, six, seven or eight selected bits of each fourteen bit sample provide optimum video, audio or like information for the sample.

Abstract: A high resolution gain response correction circuit. The inventive circuit (10) is adapted for use with a first circuit for providing a first analog input signal and includes a second circuit (R.sub.p, R.sub.ref) for providing a second input signal in response to the first input signal. A third circuit (12) is included for providing an analog output signal in response to the first and second input signals. In a particular implementation, the third circuit is a digital-to-analog converter (12). The digital-to-analog converter (12) is adapted to adjust the output signal level in response to an individual pixel correction reference signal. A digital potentiometer (R.sub.p) allows for the first input signal to be scaled and used to adjust the level of the second input signal. By adjusting the setting of the potentiometer, the dynamic range of the output to the digital-to-analog converter may be adjusted.

Abstract: An electronics circuit for accurately digitizing an analog audio, video or ike data signal into a fourteen bit digital equivalent signal/words having thirteen data bits and a sign bit and then introducing a dither component into the digital equivalent signal. A Read Only Memory which generates an eight bit dither component to be added to a selected eight bits of each fourteen bit digital equivalent sample. The combination of an automatic gain control circuit and a data selector circuit is provided which selects eight of the thirteen data bits of each sample to supply to a binary adder which adds the dither component to each sample. The eight selected bits of each thirteen bit data sample provide optimum video, audio or like information for the sample. A binary adder is also provided to add the dither component to each bit sample before providing the resultant signal to a missile's telemetry system.

Abstract: An A/D circuit to convert an analog signal to a digital signal. The circuit includes a low noise analog-to-digital conversion chip and a precision voltage reference source. The voltage reference source includes a diode with two terminals and a passive attenuation circuit. The attenuation circuit and the diode are coupled in parallel between the two terminals to provide a voltage reference signal for use by the analog to digital conversion chip. The analog to digital chip uses the voltage reference signal to set the full scale input range for the signal conversion, and the voltage reference signal is attenuated to correspond to the full scale range of the analog signal. The A/D converter circuit has a passive temperature compensation feature to substantially eliminate or reduce the effects of thermal drift and of operating at different temperatures.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: One-bit analog-to-digital converters (ADCs) and digital-analog-converters (DACs) employ an adaptive filter. The filter has two regimes of operation: variable gain within the passband of the filter under low-level signal conditions and fixed gain but a variable filter cutoff frequency (sliding band) under high-level signal conditions. Thus, excessive low-frequency gain under no-signal conditions is avoided and, when implemented using a voltage controlled amplifier (VCA), the arrangement does not demand less offset from the VCA under low-level signal conditions.

Abstract: Two automatic gain control (AGC) loops are connected by a feedforward signal. An intermediate frequency (IF) filter may be located between the output of the front-end loop and the input of the back-end loop. Stability and responsiveness are improved because neither AGC loop includes a narrowband filter. The front-end loop may include an analog gain-controlled element, but the remainder of the invention may be implemented digitally. The front-end loop prevents overloading of the A/D converter that feeds the gain-controlled signal to the remainder of the invention, and the back-end loop compensates for actions taken in the front-end loop.

Abstract: Apparatus and method for asynchronous gain adjustment are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) having a normal operating range and a filter, gain and timing control coupled to the ADC. A plurality of samples are detected from the ADC. Each of the detected samples are sequentially compared with predetermined threshold values. The predetermined threshold values include a zero value, and a minimum value and a maximum value of the normal operating range of the ADC. An absolute value of each of the detected samples are sequentially compared with a forth predetermined threshold value. A gain adjustment correction value is determined utilizing the sequentially compared values.

Abstract: A digitizer suitable for digitizing input signals having a high dynamic range. The digitizer is microprocessor controlled and comprises an input stage, a multi-channel attenuator or amplifier bank, a multiplexer and a analog-to-digital (A/D) converter. The function of the multi-channel bank is to move the input signal within the range of the A/D converter. The input signal to be digitized is fed through the input stage to each of the channels in the attenuator bank. The signal is scaled by each respective channel in the attenuator bank. The multiplexer is used to switch the scaled signal which is within the range of the A/D converter for digitizing. The digitized sample is then corrected according to the attenuation or gain factor of the scaled channel. The digitizer includes a comparator bank which is used to determine the channel with the widest signal range within the range of the A/D converter. The digitizer also includes a channel calibrator for calibrating the actual gain or attenuation of each channel.

Abstract: An analog signal having an input level is provided. The analog signal is converted into a digitized representation of the analog signal in an analog to digital converter (105) that uses an operating range. The digitized representation of the analog signal is processed (107) to determine the input level for the analog signal. The input level for the analog signal is compared (109) with a reference signal to provide a comparison signal. The comparison signal is manipulated (111) to adjust the operating range.

Abstract: A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.

Abstract: An output circuit for use with an array of analog energy detectors includes a system for digital companding which is capable of providing output signals with an enhanced dynamic range. A digital compressor is provided for converting the output signals of the analog detectors into compressed digital values. Accumulators are provided for holding the output signals of the digital compressor. An expander is provided to expand the digital output signals held in the accumulators to determine the energy patterns impinging on the array of analog detectors.

Abstract: An analog-digital processing unit including an amplifier with amplification that is adjustable in stages, and a quantizer outlet connected downstream of the amplifier. The output of the quantizer acts as actual value to control the amplification of the amplifier. With the assistance of the instantaneous value output from the quantizer, and the instantaneous prevailing amplification, the signal values, compensated by the instantaneous amplification, are defined and are output in a memory and scaling unit.

Abstract: An A/D circuit to convert an analog signal to a digital signal. The circuit includes a low noise analog-to-digital conversion chip and a precision voltage reference source. The voltage reference source includes a diode with two terminals and a passive attenuation circuit. The attenuation circuit and the diode are coupled in parallel between the two terminals to provide a voltage reference signal for use by the analog to digital conversion chip. The analog to digital chip uses the voltage reference signal to set the full scale input range for the signal conversion, and the voltage reference signal is attenuated to correspond to the full scale range of the analog signal.

Abstract: Circuitry for converting analog signal voltages to digital values comprises an analog-to-digital (A/D) converter (170) for receiving an analog signal voltage and analog reference voltages and for generating in accordance therewith a first digital value. The circuitry further comprises first and second digital-to-analog (D/A) converters (175, 180) coupled to the A/D converter (170) for providing the analog reference voltages to the A/D converter (170). A controller (120) coupled to the first and second D/A converters (175, 180) and the A/D converter (170) receives the first digital value and generates therefrom at least a second digital value for subsequent transmission to at least one of the first and second D/A converters (175 or 180), in response to which the at least one of the first and second D/A converters (175 or 180) adjusts at least one of the analog reference voltages provided to the A/D converter (170).

Abstract: An A-D converter of an image signal comprises a weighing circuit for performing a different weighing for each quantization step of A/D conversion. The different weighing is performed in accordance with gamma or white compression characteristics of the image signal.

Abstract: Analog data which enters an analog/digital converter 401 is converted into corresponding digital data. The resulting digital data is outputted upon being shifted by a bit shifting circuit. The latter shifts the digital by a number of bits set in a bit-shift quantity setting register. As a result, automatic gain control can be performed by relying on simple processing without using an amplifier consisting of complicated analog circuitry. For example, by setting a "+1" bit in the bit-shift quantity setting register, the data resulting from the A/D conversion can be doubled. The data can be multiplied by eight if a "3" bit is set, and by 1/4 if a "-2" bit is set.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A D/A converter divides an input digital data into at least two overlapping digital ranges. The data in the two ranges are converted separately from digital to analog by a low-range and a high-range DAC. The resulting analog signals are then added with a weighting that maintains the proper loudness relationships in the final combined analog output. In a low range of amplitudes, only the low-range DAC performs D/A conversion. Above a predetermined amplitude threshold, some of the high significant bits to the low-range DAC are frozen, while a remaining low significant bits of the low-range DAC are permitted to vary with the input digital data. Above the predetermined amplitude threshold, a digital value is subtracted from the data fed to the high-range DAC. The subtracted value is equal to the frozen value in the low-range DAC. In some embodiments, one or more supplementary bits are developed to smooth the transition between ranges.

Abstract: A window tracking analog to digital convertor (10) and method of signal conversion is disclosed. A sample and hold amplifier (16) samples an analog input signal and passes the sampled signal to a window comparator (20). The window comparator (20) analyzes the analog input signal to determine if its amplitude falls between upper and lower reference levels which establish a tracking "window." If the amplitude of the signal falls outside of the window, a control processor (34) and window reference tracker (24) adjusts the reference levels in the direction of the reference level which was exceeded until the analog input signal falls within the window, the adjusted reference level in the direction of adjustment representing the level of the sampled signal. A continuous interval timer (38) counts the amount of time that the analog input signal remained within the window.

Abstract: An apparatus and method of calibrating a digital to analog converter including means for establishing and storing a minimum and maximum analog endpoint value slightly in excess of the desired operating range of the DAC and then scaling each respective raw data point of the DAC within the established endpoint values.

Abstract: There are provided 2.sup.n -number of data latches (2), 2.sup.n -number of dynamic range setting latches (7) and 2.sup.n -number of output dynamic range change circuits (8) in correspondence to 2.sup.n -number of D/A converters. Controlled by the outputs of AND gates (4), the respective dynamic range setting latches (7) output dynamic range setting data DR to the corresponding output dynamic range change circuits (8). The output dynamic range change circuits (8) change dynamic ranges for the analog outputs of the corresponding D/A converters (5) as a function of the dynamic range setting data DR to output the changed analog outputs from corresponding output terminals (26).This enables the dynamic ranges for the plurality of D/A converters to be set individually without the provision of further external terminals.

Abstract: A dual range A/D converter includes means for appending a predetermined number N of random noise bits to the N least significant bits of the digital signals output from one of the dual A/D converters, thereby providing a total output bit resolution that is independent of the input analog signal.

Abstract: In order to decide on the logic value of the output signal corresponding to a received multivalued digital signal, the receiver includes a comparator circuit (3) for comparing the amplitude of the output signal with a plurality of decision thresholds produced by an integrator (24). Based on such comparison, a regenerated signal is produced having the decided logic value and an amplitude which is proportional to the decision thresholds. An adaptation circuit (17) compares the regenerated signal amplitude with that of the output signal, and based on such comparison produces a control signal (z) for either increasing or decreasing the decision thresholds so as to conform the regenerated signal with the output signal, such adaptation being effected by selectively supplying either a positive or a negative voltage to the input of the integrator (24).

Abstract: A delta sigma analog-to-digital architecture assures that all channels in a multi-element receiver follow the same compression and/or time-gain variation curve. This is accomplished by varying the reference voltage as a function of time so that the full scale range and associated quantization noise are large at the beginning of the receiving interval and become smaller as more distant echoes arrive. All channels follow the identical gain curve since all channels have the same reference voltage at the same time. The distribution of time-varying reference voltages may be done by using analog buses or by employing a timevarying digital code that specifies the reference voltages derived from a digital-to-analog (D/A) converter. In the latter case, corrections can be applied to the code at each channel.

Abstract: A method and apparatus for non-linear quantization of a signal that utilizes two or more lowresolution analog to digital converters (ADCs) to allow selective increased quantization levels at desired portions of a signal. This is accomplished by using a primary ADC which provides digital output signals over a first predetermined range, and at least one secondary ADC which provides digital output signals over a smaller predetermined range for the same input values. Accordingly, any secondary ADCs have a smaller quantization step size than the first, and are utilized when finer resolution is desired. The ADCs are kept in alignment by periodically comparing the digital values produced by the ADCs for a known input analog value.

Abstract: A D/A converter includes a D/A conversion part for converting a digital input signal into an analog output signal, a parameter setting part for generating a plurality of circuit parameters which define a voltage range of the analog output signal, and a setting control part for selecting desired circuit parameters from the plurality of circuit parameters in accordance with data supplied from an external device, so that the D/A conversion part generates the analog output signal having a voltage based on the desired circuit parameters.

Abstract: An automatically gain controlled multiple approximation analog to digital converter including a gain controlled amplifier responsive to the difference between an analog input signal and an analog version of a digital approximation of the analog input signal for providing a gain controlled analog residue signal, a quantizer for converting the gain controlled analog residue signal to a gain controlled digital residue signal, a digital divide circuit for dividing the gain controlled digital residue signal by a factor representative of the gain contained therein to provide a restored digital residue signal representative of the analog residue signal before it was amplified by the gain controlled amplifier, and a summing circuit for adding the restored digital residue signal and the digital approximation to provide the output of the gain controlled analog to digital converter.

Abstract: An infrared Fourier transformation spectrometer comprising a non-linear analog-to-digital converter device having at least one amplifier and one sample and hold circuit connected downstream thereof, as well as an an analog-to-digital converter following the latter, wherein an input signal to be converted is to be supplied to one input of the amplifier and the gain of the input signal is a function of the magnitude fo the input signal, and wherein the output signal of the analog-to-digital converter is evaluated giving regard to the respective gain, is characterized by the fact that at least two analog-to-digital converters are provided whose outputs are connected to a first controllable switching arrangement for supplying selectively the output signals of one of the said analog-to-digital converters to another evaulation means and that the input signal is supplied to each of the said analog-to-digital converters amplified by a different amplification factor.

Abstract: An analog to digital converter circuit and technique including a peak detector circuit for generating a reference potential corresponding to a peak amplitude of the analog signal to be converted, a level shifting circuit for shifting the dc level of the analog signal in response to the reference potential, and an analog to digital converter for converting the shifted analog signal relative to the reference potential to provide automatically high bit resolution digital signals, independent of the magnitude of the input signal. Preferably, the level shifter sums one half the analog signal and one half the reference potential to produce the shifted signal, and the shifted signal is converted using a ratiometric analog to digital converter having a reference signal input of one half the reference potential. The reference potential is periodically updated by detecting a new peak.

Abstract: A delta sigma analog-to-digital (A/D) converter includes a digitally-controlled multiplying digital-to-analog converter (MDAC) in a feedback configuration. The MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter. An incremental feedback quantum to the first stage integrator is a function of the input values that immediately precede it. In the most general implementation, a table look-up permits an arbitrary relation between the input values and feedback quantum size. In another implementation, the A/D converter output (or intermediate output) signal drive the MDAC and the compression curve of the A/D converter bears a square-root relationship to the input analog signal; a linear relationship is restored by squaring the output signal. In a third implementation, the MDAC is driven by a digital signal obtained from the output (or an intermediate output) of the A/D converter together with an added small positive constant number.

Abstract: A circuit for analog-to-digital conversion is disclosed comprising multiplexed ADCs. Dithering is introduced into the circuit before conversion and subtracted out of the resulting digital output stream. Gain control feedback loops are employed to eliminate non-unity gain error of the dither signal and multiplexed ADC differential gain errors. Correlation between the digital output stream and the dither signal is used to detect a non-unity condition and derive gain control feedback. Correlation with the dither signal is also used to detect gain differences between multiplexed ADCs and generate corrective feedback.

Abstract: The invented auto-ranging device has a signal measuring A/D converter, a range-switching A/D converter of a faster processing speed, a range-switching amplifier with variable amplification capabilities, and a processing controller which utilizes the variable amplification factors to alter the output signals from the switching A/D converter to generate signals appropriate for a scale range of a multi-range measuring A/D converter.

Abstract: Disclosed is an apparatus for the reception of video signals with a variable gain amplifier to hold the video signal between pre-determined limits. To control the gain of the amplifier, there is provision for a circuit that keeps the amplitude of the line synchronization pulse substantially constant. This circuit has, for example, an analog/digital converter with an output, one bit of which represents the sign of the difference between the line synchronization pulse and its prescribed value.

Abstract: The present invention relates to a measurement circuit for providing the digital value of an analog electrical signal. The digital measurement circuit for measuring an analog electrical signal produces a measurement signal (M) and includes an amplifier (1) which receives said electrical signal (I), followed by an analog-to-digital converter (2) which delivers digital data (N). The gain of the amplifier (1) is controlled by a control signal (C) and said gain can take up at least two values. The measurement circuit further includes a control unit (3) producing said control signal (C) and storing the digital data corresponding to different gain values, and includes means for producing the measurement signal (M) on the basis of said digital data (N).

Abstract: A digital multimeter having automatic function selection capability includes a signal type detector and an analog-to-digital converter formed as an application specific integrated circuit. The signal type detector has a comparator circuit that compares the analog input signal to be measured with predetermined thresholds and stores the resulting values, which are related to the type of analog input signal, in a memory that is also a part of the signal type detector. A controller executes an automatic function selection program that causes the controller to read the stored values and generate a corresponding function code, which causes an analog-to-digital converter to be configured to perform an appropriate conversion function on the analog input signal. When a change in the type of analog input signal is sensed, the controller aborts the present measurement cycle and proceeds with a next measurement cycle in which the changed analog input signal is measured.

Abstract: A system for coding and decoding an audio signal by using an orthogonal and inverse orthogonal transformation of a block unit, includes a coding unit having a circuit for obtaining a power level of the audio signal of a segment unit having a predetermined time interval shorter than the block unit, a circuit for generating a gain control signal from the power level, a circuit for performing a predetermined adaptive gain control responsive to the gain control signal to generate and output the adaptive gain control signal to a decoding unit, thereby performing a pre-treatment, and a coding portion for coding the adaptive gain control signal by using the orthogonal transformation to generate and output a coded signal; and the decoding unit having a decoding portion for decoding the coded signal, dequantizing and inversely and orthogonally transforming a decoded audio signal, and a circuit for performing an inverse gain control for the decoded audio signal responsive to the adaptive gain control signal from the ad

Abstract: Parallel low-level and high-level quadrature demodulators (60,62) are provided, each including high speed analog-to-digital converters (82,84) with a nominal number of bits. A signal limiter (56) upstream of the low-level demodulator (60) limits the amplitude of an input analog signal (IF IN) to a value corresponding to a predetermined signal level. An attenuator (58) upstream of the high-level demodulator (62) attenuates the input signal (IF IN) by a predetermined factor, so that the signal level into the high-level demodulator (62) is correspondingly lower than the signal level into the low-level demodulator (60). When the amplitude of the input signal (IF IN) is below a predetermined value, a digital switching and scaling unit (72) selects the output signals from the low-level demodulator (60) and extends the digital output to a larger number of bits.