Abstract: The disclosure is directed to a mobile communication device that includes automatic gain control (AGC) circuitry. Every n samples of the broadcast signals, an energy estimate of the AGC output signal is used to calculate and update a gain control value. Instead of using all n samples occurring subsequent to a previous gain control value update, only a subset of those n samples are used. In particular the first half of the n samples may be discarded in the energy estimate calculation while only the second half of the n samples may be used.

Abstract: A system comprises a gain control module that selectively generates a gain locked signal based on a wireless input signal. A sync detect module that selectively generates a sync detect signal based on the wireless input signal. An interference detection module that selectively generates a wireless interference detection signal based on the gain locked signal and the sync detect signal.

Abstract: A gain control method is provided. In one embodiment, an amplifier amplifies a first signal according to a gain to obtain a second signal, and a converter converts the second signal to a digital signal. First, the gain is sequentially set to a plurality of gain values. A plurality of entropy values of the digital signal corresponding to the gain values is then calculated. A picked entropy value of the entropy values is then determined. The gain value corresponding to the picked entropy value is then determined as a picked gain value. Finally, the gain is set to the picked gain value for amplifying the first signal.

Abstract: An integrated circuit device includes an amplifier circuit that receives an input signal and performs an offset adjustment corresponding to a DC offset of the input signal and a gain adjustment corresponding to an amplitude of the input signal, a filter that is provided in a subsequent stage of the amplifier circuit, a cut-off frequency of the filter being variably set corresponding to a frequency band of the input signal, an A/D converter that is provided in a subsequent stage of the filter and performs an A/D conversion process on a signal amplified by the amplifier circuit, and a control circuit that sets an offset adjustment of the amplifier circuit, a gain adjustment of the amplifier circuit, and the cut-off frequency of the filter.

Abstract: A receiver uses a sigma delta ADC (126) and an adaptable digital filter (132). Detector circuitry detects information about unwanted parts of the signal from an oversampled digital signal, before the filtering, and feeds forward the detected information to the filter, to adapt the filter. By feeding forward the detection information, rather than feeding back an output of the filter, the adaptation can respond much more quickly to rapid changes in the unwanted interference. This enables reduced filtering to save power when interference is low, without risking a sudden increase in interference causing an avalanche of errors before the filter can be adapted correctly. The filter receives the oversampled digital signal combines decimation and channel filtering in one stage.

Abstract: An A/D conversion circuit includes an amplifier circuit that includes a plurality of amplifiers that are cascaded, a selector that selects one of output signals output from the plurality of amplifiers and outputs the selected output signal as a selector output signal, an A/D converter that A/D-converts the selector output signal output from the selector, a determination circuit that determines whether or not a voltage of the output signal output from each of the plurality of amplifiers is within a determination voltage range specified by a high-potential-side determination voltage and a low-potential-side determination voltage, and a control circuit that instructs the selector to select one of the output signals output from the plurality of amplifiers based on the determination result of the determination circuit.

Abstract: Gains and offsets of the input-output characteristic of a second side reading unit are controlled so as to match input-output characteristic of a first side reading unit on the basis of image data of a gray chart read by the first side reading unit and the second side reading unit. Then, on the basis of image data of a color chart read by the first side reading unit and the second side reading unit, offsets of the input-output characteristic of the second side reading unit are controlled for individual color components such that differences between color read by the first side reading unit and color read by the second side reading unit are reduced.

Abstract: A receiver module includes an automatic gain control module having a gain that varies from a nominal value in response to the receiver module receiving an input signal. The automatic gain control module is configured to generate a first signal in response to the gain settling at a value different from the nominal value. A peak detector module is configured to generate a second signal in response to the gain deviating from the nominal value by a predetermined amount. The peak detector module generates the second signal prior to the automatic gain control module generating the first signal. A control module is configured to receive each of the first signal and the second signal and reset the receiver module to halt processing of the input signal in response to the control module not receiving the first signal within a predetermined amount of time subsequent to the control module receiving the second signal.

Abstract: A signal is received and whether a signal mode of the signal is a first signal mode or a second signal mode is determined. A gain of a variable gain amplifier is adjusted to a first gain value if the signal mode of the signal is determined to be the first signal mode or a second gain value if the signal mode of the signal is determined to be the second signal mode. The signal is amplified with the variable gain amplifier by the first gain value or the second gain value. The signal is converted to a digital signal with an analog to digital converter after the signal is amplified with the variable gain amplifier by the first gain value or the second gain value.

Abstract: A reference voltage generating unit generates a plurality of analog reference voltages, and an A/D converting unit converts the analog reference voltages thus generated and an analog input voltage input from an external device to digital reference values. A CPU generates, based on the analog reference voltages and the digital reference values converted from the analog reference voltages, an equation for correcting the analog input voltage to be converted to a digital value falling in a range of the digital reference values. With the equation generated, the CPU calculates the analog input voltage for the digital value obtained by conversion.

Abstract: Techniques for performing automatic gain control are described. In some aspects, the gain control is achieved with an apparatus having an analog-to-digital converter (ADC) and a digital variable gain amplifier (DVGA), the DVGA configured to receive a digital signal from the ADC, the DVGA having a processor configured to compute a gain using a base n logarithm based on the power of the digital signal output from the ADC, the processor being further configured to apply the gain to the digital signal.

Abstract: A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.

Abstract: A method for detecting saturation in a cascaded ?? ADC can include receiving an output of the cascaded ?? ADC, determining a magnitude of the output, and squaring the magnitude. The squared magnitude can be added to a feedback signal, wherein the sum represents a saturation signal. The saturation signal can be filtered and then amplified, wherein the amplified, filtered saturation signal is the feedback signal. The saturation signal can then be compared to a threshold to determine whether the cascaded ?? ADC is in saturation.

Abstract: A digitizer for digitizing a magnetic resonance (MR) signal is hereby disclosed, the digitizer comprising at least two analog amplifiers (1021, 1022 . . . 102n) electrically connected in parallel and configured to amplify the MR signal, wherein each analog amplifier has a different analog gain value, a measuring unit configured to measure a characteristic of the MR signal, a sample selection module (108) configured to generate a selection signal (SS) based on the measured characteristic, and a first analog-to-digital converter (104) configured to digitize the amplified MR signal from one of the at least two analog amplifiers, based on the selection signal.

Abstract: In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Abstract: The management of unit element selections in a system that includes multiple unit elements. The system includes an element selection component that is configured so that each of the multiple elements is used the same number of times over a certain number of selection cycles. This preserves the first order noise shaping of the mismatch noise thereby keeping a high signal to noise ratio. In addition, the selection of the unit elements is not done in a periodic fashion. This allows the system to avoid tones within the signal band.

Abstract: This disclosure describes techniques for detecting or predicting saturation of an analog-to-digital converter. The techniques analyze digital samples following analog-to-digital conversion, and count occurrences of specific values associated with a subset of bits within the digital samples. The specific subset of bits that are used detect or predict saturation may vary depending on the analog-to-digital converter and the number of bits in the digital samples. However, the techniques avoid the need to consider every bit in the digital samples, and rely only on a subset of bits (one or more), which can simplify the counting algorithms used in the saturation detection or prediction. Upon identifying a probable saturation state of the analog-to-digital converter based on the counting, the techniques may de-boost the gain of an analog amplifier. This can effectively extend the dynamic range of the analog-to-digital converter.

Abstract: Disclosed herein is a signal level conversion circuit for increasing the dynamic range of an Analog-to-Digital Converter (ADC). A comparison and calculation unit compares the value of an input signal Vin and the value of a first reference signal Vref1 and compares the value of the input signal Vin and the value of a second reference signal Vref2, and calculates and outputs respective differences therebetween. A signal leveling circuit unit converts signal levels of the respective output signals of the comparison and calculation unit so that the output signals fall within the dynamic range of an ADC. The ADC digitizes the output signal Vo of the signal leveling circuit unit and the output signals Vack1 and Vack2 of the comparison and calculation unit.

Abstract: A device is described herein that performs a digital-to-analog conversion on a digital multimedia signal in a manner that enhances the human perceptual quality of the resulting analog multimedia signal (e.g., musical passage). In one embodiment, the device operates as follows: (1) divides the bitstream of a digital multimedia signal into several distinct multimedia bitstreams; (2) applies the most effective signal processing (filtering and noise shaping) to each distinct multimedia bitstream; (3) performs the most appropriate digital-to-analog conversion (using a multi-bit DAC, a bitstream DAC, a over-sampled bitstream DAC, or a hybrid of these DACs) to each distinct multimedia bitstream; and (4) combines all of the analog multimedia signals which are outputted by the DACs into a single analog multimedia signal.

Abstract: A system for detecting interference includes an automatic gain control (AGC) module, a peak detection module, and a control module. The AGC module selectively generates a gain-locked signal when an input signal is received. The peak detector module communicates with the AGC module and selectively generates a peak-detect signal. The control module communicates with the AGC module and the peak detector module and generates a control signal when the control module does not receive the gain-locked signal within a predetermined time after receiving the peak-detect signal.

Abstract: A signal processing circuit has an analog to digital converter (31) for providing a digital signal to a processor (15) from an analog input signal that is susceptible to variations in signal power, e.g. from a radio front end (12). The device has a variable gain amplifier (13) controlled by a gain control signal based on detected signal strength. The analog to digital converter has a loop comprising a loop filter for processing the input signal. A signal strength detection circuit (32) is provided for generating the gain control signal, which signal strength detection circuit has loop signal detector for detecting the signal strength from the loop. Hence a received signal strength indicator RSSI is directly coupled to the analog to digital converter (31), avoiding the delay of signal strength detection in the digital processor.

Abstract: An analog-digital converting apparatus includes: an analog-digital converting unit that performs a conversion from an analog input signal into a digital output signal; a buffer unit that temporary stores the digital output signal for a plurality of samples and outputs the samples in time-series; a clipping detecting unit that detects a first sample having a signal value corresponding to a clipping level of the analog-digital converting unit from among the samples of the digital output signal; and an interpolating unit that rewrites the signal value of the first sample stored in the buffer unit into an estimated signal value that is obtained by estimating a signal value at a time corresponding to a time of the first sample by an interpolation using at least one of (1) a set of second and third samples that are samples previous to the first sample and (2) a set of fourth and fifth samples that are samples subsequent to the first sample.

Abstract: An optical receiving device of the present invention receives optical signals from an optical transmitting device which uses a modulation format wherein an optical intensity waveform of each symbol is return-to-zero (RZ) pulse, and converts the received optical signals into digital signals by a conversion process of an analog to digital (AD) converter. A control-value calculating unit subsequent to the AD converter digitally processes the digital signals, retrieves an absolute value of the digital signals or a value corresponding one-to-one with the absolute value of the digital signals, estimates errors from an appropriate timing of a sampling timing in the AD converter based on the absolute value of the digital signals or the value corresponding one-to-one with the absolute value of the digital signals, and calculates a control value controlling the sampling timing based on the estimated errors.

Abstract: Apparatuses, methods, and systems for compensating baseline offset in a read channel of an analog storage device. The apparatus generally includes an AC-coupling circuit configured to transfer an analog signal from an analog storage device to the read channel, a configurable current device coupled to the AC-coupling circuit, comparator coupled to the AC-coupling circuit, and logic coupled to the configurable current device and the comparator, wherein the logic is adapted to configure said current device in response to an output of at least one of the AC-coupling circuit and the comparator.

Abstract: A signal processing system for changing a level of an input signal to generate an output signal is disclosed. The signal processing system includes a shifter, a sigma-delta modulator, and a level adjuster. The shifter is utilized for receiving the input signal and for bit-shifting the input signal according to a first predetermined gain to generate a first adjustment signal. The sigma-delta modulator is utilized for generating the output signal according a second adjustment signal and the first adjustment. The level adjuster is utilized for adjusting a level of the output signal according to a second predetermined gain to generate the second adjustment signal.

Abstract: A system and a method are provided for receiving analog and digital audio input via a single audio input connector. The method includes receiving an input signal from a single audio input connector, splitting the received input signal into a first input signal and a second input signal, filtering the first input signal to pass a digital signal, filtering the second input signal to pass an analog signal, digitizing the filtered analog signal, and multiplexing the filtered digital signal and the filtered digitized analog signal.

Abstract: This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.

Abstract: A technique to utilize digital gain control to fine adjust gain for one or more analog gain steps of an analog circuit. A gain step calibration procedure is utilized to set the digital gain within acceptable limits established for the analog gain at a particular operating gain level for the analog circuit set by an analog gain step.

Abstract: A device is for digitally processing an input signal that is susceptible to variations in signal strength. The signal (48) is analog to digital converted into a bitstream signal (47), the bitstream signal representing the input signal by consecutive digital values. The device has a signal strength detection circuit (32) for generating a control signal indicative for an overload condition in which the signal strength exceeds a input range of the analog to digital converter, e.g. a sigma-delta modulator. The signal strength detection circuit detects, in the bitstream signal, a sequence (49,50) of adjacent and equal digital values, the sequence having at least a predetermined length. The circuit detects the overload condition effectively and fast, avoiding the delay of signal strength detection in a digital processor.

Abstract: The invention discloses an analog front end device includes a calibration unit and at least a conversion circuit. The conversion circuit includes a clamper, a multiplexer, an voltage buffer and an analog to digital converter. The clamper receives an image signal and resets the DC voltage level of the image signal to generate a clamped signal. The multiplexer receives the clamped signal and a test signal and outputs the clamped signal or the test signal according to a selecting signal. The voltage buffer amplifies the clamped signal or the test signal to generate a buffer signal. The analog to digital converter converts the buffer signal into a digital signal. The calibration unit generates a gain correction value according to the test signal and calibrates the gain offset of the digital signal according to the gain correction value.

Abstract: A gain matching method for a single bit gain ranging analog to digital converter including selecting, in response to a gain setting, a number of gain elements to be enabled in a multi-element gain controlled array interconnected between an analog input and an analog to digital converter, and patterning the enablement of the selected number of gain elements among the gain elements for matching the gain of the analog to digital converter for a range of gain settings of the converter to reduce in-band gain error due to gain element mismatch.

Abstract: An inverter system includes a comparator unit receiving an analog input voltage signal and compared with at least one threshold voltage value to determine a voltage range of the analog input voltage signal. An amplifier unit receives and amplifies the analog input voltage signal. A feedback-controlling gain unit adjusts a voltage gain of the amplifier unit according to the voltage range of the analog input voltage signal. An analog-to-digital converter unit converts an analog signal outputted from the amplifier unit into a digital count. A microcontroller unit is electrically connected with the analog-to-digital converter unit and the comparator unit. The microcontroller unit receives an indicating signal outputted from the comparator unit to know the voltage range of the analog input voltage signal. The microcontroller unit receives a digital count outputted from the analog-to-digital converter unit to correctly calculate an original value of the analog input voltage signal.

Abstract: An automatic power level control circuit provides output power control of a transmitter device as used in wireless LAN applications in that an output signal is detected and a corresponding control voltage of a DAC in the base band section is corresponding adjusted. Preferably, the measurement of the output power is carried out during a first transmit cycle and the DAC is adjusted after completion of the first transmit cycle and prior to the begin of a subsequent transmit cycle. Thus, a reliable output level control is obtained with a minimum number of radio frequency components, wherein the control loop shows an enhanced stability due to the time-discrete control operation.

Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Abstract: A method for continuously determining the required dynamic range for an analog-to-digital converter by determining the received signal strength and using this received signal strength value in combination with the overall dynamic range for the ADC and the target resolution of the ADC to decode a radio channel in the absence of interference, wherein the target resolution is also related to the type of decoding to be performed subsequent to analog-to-digital conversion. The method allows for a reduction in power consumption associated with the ADC, especially when the incoming signal is received with few interfering radio channels and with a relatively high signal strength. The present method can be combined with gain control and analog alert detection.

Abstract: An image sensor and digital gain compensation method thereof. The image sensor comprises a variable amplification device for amplifying an inputted analog image signal as a variable first gain value, an analog-to-digital conversion unit for converting the amplified analog image signal into a digital image signal, and a digital gain compensation device for comparing the first gain value with a reference gain value and compensating the digital image signal as a digital second gain value when the first gain value is less than the reference gain value.

Abstract: Voltage values at a high-voltage side and a low-voltage side of a reference voltage are generated on the basis of a current outputted from a current source circuit having an adjustable current value, and an impedance element having an adjustable impedance value which is connected to an operating amplifier, analog-to-digital conversion is carried out on the basis of the reference voltages, whether gain adjustment for the analog-to-digital conversion is necessary or not is judged according to the conversion result, and the output current of the current source circuit and/or the impedance value of the impedance element are adjusted on the basis of the judgment to adjust the generated voltage values at the high-voltage side and the low-voltage side of the reference voltage. The gain of the analog-to-digital conversion is made variable by adjusting the voltage values at the high-voltage side and the low-voltage side of the reference voltage.

Abstract: A selecting circuit having minimal signal distortion caused by non-linearity of semiconductor switching elements includes a plurality of circuit groups each comprising an input terminal (INa); serially connected resistors (R1a, R2a) having a first end connected to the input terminal; a semiconductor switching element (SW1a) having a first end connected to a node between the resistors; and semiconductor switching elements (SW2a, SW3a) having first ends connected to a second end of the resistors (R1a, R2a). The circuit further includes an operational amplifier (OP) having an inverting input terminal to which second ends of semiconductor switching elements (SW1a, SW1b, . . . , SW1n) in respective ones of the circuit groups are connected in common, and an output terminal to which second ends of semiconductor switching elements (SW2a, S2b, . . .

Abstract: In an analog receiving section of a receiving device, the level of a received signal is adjusted by a first correction factor corresponding to a first digital level correction signal. Following this, the level-adjusted received signal is converted into a digital received signal. In a digital receiving section of the receiving device, the digital received signal is changed in accordance with a second digital level correction signal, in such a manner that a number of partial level adjustments are generated in successive time intervals in dependence on the level adjustment generated in the analog section. Thus, coarse level jumps produced in the analog receiving section can be split into individual small level jumps in the digital receiving section and stretched in time so that they can be processed in the subsequent demodulator.

Abstract: A self-adapting analogue-to-digital converter includes a forward path with a voltage divider coupled to a digital integrator. In a feedback path, a scaler is connected to a digital-to-analogue converter. A control unit provides control signals for the voltage divider and the scaler in response to the output word of the digital integrator.

Abstract: An automatic clock generation system is used for automatically outputting a sampling signal and a holding signal to an analog front end circuit and for sampling the analog signal. The clock generation system comprises a clock generator generating a plurality of clock signals and a comparing module. According to the plurality of clock signals, the comparing module compares the analog signal with a first reference signal and outputs a first comparison signal. The comparing module further compares the digital signal outputted by the analog front end circuit with a second reference signal and outputs a second comparison signal. The clock generator selectively outputs a first clock signal, corresponding to the first comparison signal, of the plurality of clock signals as the sampling signal when the first comparison signal received by the clock generator is at a high state.

Abstract: A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using one or more reference capacitor(s) that have been charged with a net charge corresponding to a quantizer-controlled reference voltage in a preceding clock phase. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high input impedance. The reference capacitor(s) may be discharged in a third clock phase, so that input-signal-dependent voltages are discharged from the capacitor(s). An additional sampling capacitor can be discharged in the first clock phase and coupled in parallel with the reference capacitor during the second clock phase, to set the gain with respect to the input voltage.

Abstract: The present invention provides an OFDM receiver having a level control section comprising comparators which respectively compare a first signal outputted from an ADC with threshold values, counters which respectively count the frequencies with which the level of the first signal exceeds the threshold values, based on second and third signals corresponding to the results of comparison by the comparators, a moving average unit which calculates an average value of the level of the first signal lying in a predetermined period, based on fourth and fifth signals corresponding to the frequencies counted by the these counters, and a DAC which generates a gain control signal for controlling an AMP in such a manner that the average level of the first signal outputted from the ADC becomes a predetermined value, according to a sixth signal calculated by the moving average unit.

Abstract: An up-converter 124 frequency-up-converts an analog signal Sm. A down-converter 121 frequency-down-converts analog signal Sm. A signal selection block 125 selects one of the frequency-up-converted signal Sfu and frequency-down-converted signal Sfd. The signal Se selected by the signal selection block 125 is provided to the primary winding of a transformer 127. A signal induced in the secondary winding of the transformer 127 is provided to an A/D converter 128 to produce a digital signal Dm. For example, if the analog signal Sm has DC or a low frequency close to DC, the signal Sfu is selected as the signal Se. If the analog signal Sm does no have DC nor a low frequency close to DC, the signal Sfd is selected as the signal Se.

Abstract: A power-to-digital converter (PDC) converting a signal power to digital code. The PDC comprises a power detector, an analog-to-digital converter (ADC), and a timing and logic control circuit. The power detector receives the signal power and generates a DC output and a first determined number of bits. The ADC is coupled to the power detector and receives and converts the DC output to a second determined number of bits. The timing control logic circuit is coupled to the power detector and the ADC and sequentially enables the power detector and the ADC. The first and second predetermined numbers of bits are respectively most significant bits (MSBs) and least significant bits (LSBs) of the digital code. The bit resolution of the digital code is the sum of the first and second numbers.

Abstract: A readout circuit is adapted for receiving a line analog image signal from an image sensor array of an image sensor. The readout circuit includes an amplifying unit, an m-bit analog-to-digital converter, and an m-to-n bit digital converting unit. The amplifying unit is adapted for amplifying and correcting amplitude of the line analog image signal, and outputs an amplified and corrected analog signal. The m-bit analog-to-digital converter is coupled to the amplifying unit, and is operable to convert the amplified and corrected analog signal into a corresponding m-bit digital signal. The m-to-n bit digital converting unit is coupled to the m-bit analog-to-digital converter, receives the m-bit digital signal from the m-bit analog-to-digital converter, and is responsive to a k-bit control signal for converting the m-bit digital signal into an n-bit digital signal, wherein m is greater than or equal to n.

Abstract: The present invention provides a read channel and a drive capable of suppressing deterioration in performance of a PLL and a Viterbi decoder by using a DC component eliminating means capable of higher-speed operation than hitherto. The location of an edge is determined by using differential of a read signal, and a DC component is detected from the midpoint level of the edge. Detection of a pseudo-edge due to a long mark or space signal is prevented by limiting the absolute value of a maximum or minimum of a differential coefficient when the location of the edge is determined from the differential coefficient of the read signal. Internal operation of a DC component detector is controlled according to the state of the PLL and the magnitude of the DC component.

Abstract: An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Abstract: Amplifier comprising an input signal node for conveying an input signal having an input signal value and an output signal node for conveying an output signal having an output signal value. Amplifier circuitry is coupled to the input signal node and provided with a plurality of intermediate output signal nodes, each for conveying an intermediate output signal having an intermediate output signal value. The intermediate output signal value in each intermediate output signal node relates to the input signal value in accordance with predetermined signal gains. A signal selector selects one of the intermediate output signals and feeds the selected one to the output signal node. The amplifier may be comprised in an analogue to digital converter. The amplifier may be incorporated in a down hole tool. The method of amplification may be used in a method of producing a mineral hydrocarbon fluid.

Abstract: A low-power, high-dynamic range, analog-to-digital (A/D) conversion circuit for converting an analog signal to a digital signal having a controllable amplifier for amplifying the analog log signal received at an input of the amplifier in response to a first control signal and for generating an amplified analog signal, a low dynamic range A/D converter for converting the amplified analog signal to an intermediary digital signal, a controllable bit shift register for scaling the intermediary digital signal in response to a second control signal to generate the digital signal, and a gain control component (AGC) for generating the first control signal to cause the amplified analog signal to be within the dynamic range of the A/D converter and for generating the second control signal to cause the scaling to compensate for the amplification by the amplifier.