Abstract: An electronic device includes a processor coupled to a memory device, through a data bus to receive and transmit bits on the data bus. The processor is configured to transmit a message including a first bit indicative of controlling the data bus, address bits indicative of an address identifying the memory device, and a second bit indicative of whether the processor intends to read data from or write data to the memory device; and transmit a third bit indicative of a mode of operation of the memory device.

Abstract: A discrete-time (e.g., digital) filter can be used as an interpolation filter for processing an oversampled input signal, such as included as a portion of a sigma-delta digital-to-analog conversion circuit. An interpolation filter control circuit can be configured to adjust a filter order of the discrete-time interpolation filter at least in part in response to information indicative of an envelope signal magnitude. For example, higher-level input signals might be processed using an interpolation filter having a stop-band attenuation that is more stringently-specified (e.g., having greater attenuation) than a corresponding attenuation used for lower-level input signals. The filter order can be variable, such as varied in response to a detected envelope magnitude of the input signal to achieve power savings as compared to a filter having fixed parameters.

Abstract: The DA converter according to the present invention includes: first and second analog segment units a plurality of capacitors of sampling capacitor groups charged according to signal levels of digital signals input in a sampling phase; and a calculation unit that outputs an analog signal according to a charged voltage of each capacitor of the sampling capacitor group of the first or second analog segment unit in an integral phase, wherein, when one analog segment unit of the first and second analog segment units is in the sampling phase, the other analog segment unit is in the integral phase.

Abstract: A non-linear gamma compensation current mode digital-analog converter includes: a first digital-analog converter block configured to: receive a digital signal, a first reference voltage, and a gamma adjustment voltage, and provide a reference current to a ground, wherein a first current flowing to a first current output terminal is determined according to the digital signal and the gamma adjustment voltage; and a second digital-analog converter block configured to: receive the digital signal, a second reference voltage, and a ground voltage, and provide the first current to the first digital-analog converter, wherein a second current flowing to a second current output terminal is determined according to the digital signal and the first current.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.

Abstract: The present invention discloses a DAC circuit and a weight error estimation/calibration method thereof. In the method, an output switching circuit dynamically selects several conversion cells (at least containing know weight conversion cells (KWCC)) as a reference conversion cell group (RCCG) from all conversion cells, and dynamically selects at least one unknown weight conversion cell (UWCC) from all UWCCs. An ADC digitalizes the difference of the output of RCCG and the sum of the outputs of the UWCCs, and inputs the result to a digital controller. The digital controller controls the input of the RCCG according to the output of the ADC to make the output of the RCCG approximate the output of the UWCC. The digital controller uses the outputs of the ADC to work out the actual weights of the UWCCs and stores the actual weights in a calibration memory.

Abstract: According to some embodiments, a digital to analog converter comprises an array of input data streams. An array of differential MOS switches are all biased by a common tail current source. A data stream combiner combines and selects at each clock cycle the correct bit. Only one transistor from the switches conducts current at any time. The duration during which a switch conducts current is independent upon the fronts of the bits from the input data streams, thus rendering the switching code independent.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: An analog-digital conversion system comprising at least one variable gain amplifier amplifying an input signal e, an analog-digital converter CAN digitizing said signal e, an interference-suppressing digital processing module, processing the digitized signal, also comprises a first automatic gain control AGC loop, called the analog AGC loop, that compares an estimate of the output power of the CAN converter with a control setpoint g1 called the control setpoint of the analog AGC loop, a gain ga used to control the variable gain amplifier being deduced from this comparison. The system also comprises a second automatic gain control AGC loop called the digital loop, said digital loop comparing an estimate of the power after the interference-suppressing digital processing with a predetermined control setpoint gn, the analog AGC loop being controlled by a control setpoint deduced from this comparison.

Abstract: A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform digital-to-analog conversions, such that an internal digital signal received from the switch fabric may be converted to an analog output signal on the switch. The converted analog output signal may then be transmitted to an external destination in accordance with a serial data protocol.

Abstract: An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital signals associated with the one or more data converters are routed through the switch fabric; and a signal processing engine coupled to the control logic, wherein the signal processing engine performs on-chip processing of digital signals received from the transceiver block and the data converter physical interface.

Abstract: A DAC for converting a sequence of digital words into a corresponding analog signal. The DAC includes: a thermometer code generator fed by the sequence of digital words for providing N parallel outputs, each one of the outputs having one of two discrete levels; and an amplifier section having a plurality of N amplifiers, each one of the N amplifiers being fed by a different one of the M outputs. Each one of the amplifiers is driven into saturation in response to one of the two discrete levels or pinched-off in response to the other one of the two discrete levels. A combiner sums outputs of the N amplifiers producing a sequence of analog signals having levels related to the decimal values of the sequence of the digital words. An interconnection network interleaves connections between the thermometer code generator and the plurality of amplifier sections.

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The transmitter includes a plurality of current cells. Each cell is configurable for operating in different modes. The method includes determining a first probability associated with transmitting data at a particular symbolic level and determining a second probability associated with each cell being used during a transmission at the particular symbolic level. Next, one of the modes for each cell is selected in accordance with anticipated performance requirements. An average current of the transmitter is then calculated based upon the determined first and second probabilities and the selected modes.

Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.

Abstract: In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-??) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC), a second DAC, and a control circuit to select which DAC to use for digital-to-analog conversion of a digital signal. Concerned with the noise level produced at a given out-of-band frequency, the control circuit bases its selection of DACs, at least in part, on a frequency distance between the given out-of-band frequency and the digital signal's frequency. The control circuit, for example, may select the DAC producing the lowest noise level at that frequency distance, or, if both DACs are able to reduce noise to a level below a noise tolerance specified for the frequency distance, the DAC consuming the least power. To reduce the chip area required for the digital-to-analog conversion circuit, the first and second DACs advantageously have topologies that permit them to share common components (e.g., DAC unit elements).

Abstract: A system for converting an analog signal to a digital signal may include a plurality of converter stages. One of the converter stages may include a multiplying digital-to-analog converter (MDAC) and an analog-to-digital subconverter (ADSC). The MDAC may be configured to (i) receive from a previous stage a first residue analog signal and a first idealized digital signal representing a first portion of the digital signal and corresponding to the first residue analog signal; (ii) convert the first idealized digital signal to an idealized analog signal; and (iii) output a second residue analog signal based on the difference between the first residue analog signal and the idealized analog signal. The ADSC may be configured to convert the second residue analog signal into a second idealized digital signal representing a second portion of the digital signal and corresponding to the second residue analog signal, the ADSC comprising a sloping analog-to-digital converter.

Abstract: A serial communication circuit for performing full duplex serial communication with a microcomputer includes a counter and a timer. The counter is incremented by each pulse of a serial clock signal output from the microcomputer. When the counter reaches the number of bits of serial data output from the microcomputer, the counter outputs a load signal to a receiving register. The timer starts to count after the counter outputs the receiving load signal for the first time and continues to count during the serial communication. The timer expires at a predetermined time interval. Each time the timer expires, the timer outputs a timer signal. In response to the timer signal, a synchronous signal is output to the microcomputer, the counter is cleared to zero, and data to be output to the microcomputer is loaded into a sending register.

Abstract: An A/D conversion device including a first A/D conversion section and a second A/D conversion section that each include a D/A converter that has a plurality of bit capacitors corresponding to bits of input data, a comparing section that compares a reference voltage with a difference voltage obtained by subtracting an analog input voltage from an output voltage of the D/A converter, and a control section that detects a data value of the input data at which the difference voltage is substantially the same as the reference voltage and outputs the data value as digital data according to the input voltage, and an adjusting section that serially connects the bit capacitors of the D/A converter of the first A/D conversion section and the bit capacitors of the D/A converter of the second A/D conversion section that correspond to the same bits, and adjusts a capacity of at least one of the bit capacitors so that a voltage between the two bit capacitors approaches a middle point of voltages of the two bit capacitors.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: A method reading bank register values is provided. Register values are stored in a readback bank. The register values are output sequentially from the serial bank. An indicator is received by the serial bank. A determination is then made as to whether the indicator was received by the serial bank prior to completion of the outputting of the register values. If the indicator was received prior to completion of the outputting of the register values, the register values are loaded into the serial bank from the readback bank.

Abstract: A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (MSB) thermometer sub-converters. A binary converter can also be added. The LSB and MSB thermometer sub-converters include cell pairs with a main cell and a dummy cell. The main cell switches according to actual data, drawing power from a voltage source at each transition. To maintain a consistent voltage level at the output, the dummy cell creates a transition to draw power from the voltage source responsive to a lack of transition in the main cell. Each cell pair has a dedicated voltage source. Also, the MSB thermometer sub-converter can include a load matching circuit to match the parasitic capacitance of the LSB thermometer sub-converter at an output.

Abstract: A voltage divider for high precision voltage measurement has one or more pair of potentiometers. The wipers of each pair of potentiometers are ganged so that the sum of their resistances relative to a first end of the respective potentiometer is a constant. An output potentiometer or a pair of resistors provide an output for measuring the output voltage. The resolution of the voltage divider is the product of the resolution of each potentiometer pair and the output potentiometer.

Abstract: An audio processor chip includes a DSP for decoding audio data, a first DAC for performing a D/A conversion to the digital data obtained from the DSP, a PLL circuit for generating a clock signal for the first DAC to supply it to the first DAC and a clock output external terminal for outputting the clock signal obtained from the PLL circuit to a second DAC of an AFE. The first DAC 142 outputs an analog signal obtained from the D/A conversion to an analog mixer and the analog mixer performs a mixing process to the analog signal to output.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: Provided is a method and system for controlling current characteristics in a transceiver having a transmitter. The method includes identifying a phase control signal from an adjacent current cell preceding the particular current cell in time and logically ORing the phase control signal from the preceding cell with a phase control signal from the particular current cell.

Abstract: A digital to analog converter (DAC) circuit operates over an upper range and a lower range. An upper voltage node is designated AVDD; a middle voltage node is designated HVDD; and a lower voltage node designated ground. An upper DAC stage has at least one NMOS transistor that produces an output to an upper range output node when the output is in the upper range. A lower DAC stage has at least one PMOS transistor that produces an output to a lower range output node when the output is in the lower range. A body bias control circuit couples the body of the upper NMOS transistor to a voltage source equal to HVDD?Vbe and connects the body of the lower PMOS transistor to voltage source equal to HVDD+Vbe.

Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.

Abstract: A fast, high resolution digital-to-analog converter (DAC) is described herein. The DAC comprises a pulse generator, decay circuit, controller, and sample circuit. The pulse generator serially outputs pulses representing digits of a digital word least significant digit first. Each pulse generates a response in the decay circuit that decays over time according to a known decay response. One exemplary decay circuit comprises an RC circuit having an exponential decay response. The controller controls the timing of the pulses output by the pulse generator such that the period of each pulse relates to a predetermined decay amount. The sample circuit samples an output of the decay circuit at a sample time after the decay circuit receives the pulse for the most significant digit. The sampled output represents the analog value corresponding to the input digital word. The digital word may have any length, radix, or format.

Abstract: In a signal processing arrangement, a digital-to-analog converter (DAC1) of the finite impulse response type converts a serial bitstream (BSL) into an analog output signal (AL). The digital-to-analog converter (DAC1) comprises at least two current source arrays (CCA1, CC A2). In a first current source array (CCA1), a current definition cell (CD1) generates a first basic current, and a plurality of first current copy cells ( . . . , CC40, CC41, . . . ) provide respective scaled copies of the first basic current to constitute first filter coefficient currents ( . . . , IP40, IP41, . . . ). In a further current source array (CCA2), a further current definition cell (CD2) generates a further basic current, and a plurality of current further copy cells (CC1, CC2, . . . , CC80) provide respective scaled copies of the further basic current to constitute further filter coefficient currents (IP1, IP2, . . . , IP80).

Abstract: A mixed signal device, e.g., digital-to-analog converter (DAC) device has a serial interface communication protocol that accesses volatile and/or nonvolatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DAC devices, DAC devices with non-volatile memory may need special interface communication protocols for effective operation of the DAC device and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC device so that the MCU may access the DAC device's memories (non-volatile and/or volatile memories).

Abstract: A cyclic digital to analog converter (CDAC) in a pipeline structure includes a first CDAC block and a second CDAC block. The first CDAC block receives a first digital signal and converts the first digital signal to a first analog value. The first CDAC block includes a charging capacitor for charging according to the first digital signal and a first storing capacitor for storing the first analog value. The second CDAC block receives a second digital signal and converts the second digital signal to a second analog value. The second CDAC block includes the charging capacitor for charging according to the second digital signal and a second storing capacitor for storing the second analog value. The first CDAC block and the second CDAC block share the charging capacitor.

Abstract: Provided is a digital/analog converter including a voltage dividing unit that includes a plurality of voltage dividing elements and divides a reference voltage by voltage division; a first decoder that selects a plurality of voltages among the voltages divided by the voltage dividing unit; a first voltage output unit that is connected to nodes among adjacent voltage dividing elements of the voltage dividing unit and the first decoder, and outputs a plurality of voltages selected by the first decoder; a second decoder that selects any one of the plurality of voltages output from the first voltage output unit; and a second voltage output unit that is connected to the first voltage output unit and the second decoder and outputs the voltage selected by the second decoder.

Abstract: A multi-stage digital-to-analog converter has been presented. The multi-stage digital-to-analog converter may include a first digital-to-analog stage to output a first voltage and a second voltage in response to a first portion of a digital value, the first voltage being greater than the second voltage by a predetermined value, and a second digital-to-analog stage coupled to the first digital-to-analog stage to receive the first voltage and the second voltage and to generate a third voltage in between the first and the second voltages in response to a second portion of the digital value.

Abstract: A common-mode noise reduction circuit (20) adapted to receive a DIN input (?1, 0, +1), such as from a sigma-delta modulator (12), and provide alternating outputs (DoutP, DoutM) such as to reduce the common-mode noise of an H-bridge (14). A zero detect circuit (26), a pattern generator (28) and a level generator circuit (24) provide that the outputs DoutP and DoutM are either both logic 1 or both logic 0, such as to lower the common-mode noise level by a device, such as a H-bridge (14). This circuitry (20) places a zero in the transfer function of the H-bridge (14) to reduce the common-mode noise, whereby high pass filters shape the noise out-of-band in an over sampled system.

Abstract: Disclosed is a serial data conversion apparatus comprising: a video signal packet conversion unit for converting a characteristic signal of a video signal into a video signal characteristic packet and simultaneously converting a video signal into a video signal packet by the characteristic signal of a video signal, horizontal/vertical synchronization signals, and a video clock signal; an audio signal packet conversion unit for converting a characteristic signal of an audio signal into an audio signal characteristic packet and simultaneously converting an audio signal into an audio signal packet by the characteristic signal of an audio signal, left/right control signals, and an audio clock signal; a control signal packet conversion unit for converting a control signal into a control signal packet by an informing signal which informs a generation of a control signal; and a multiplexer for switching and selecting the video signal characteristic packet, the video signal packet, the audio signal characteristic pac

Abstract: A signal processing apparatus includes a first signal processor which processes a first channel of signal; and a second signal processor which processes a second channel of signal independently from the processing by the first signal processor.

Abstract: A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2.

Abstract: A machine used for analog-to-digital (A/D) conversion in which an analog input is compared to a piece-wise non-linear analog reference waveform. A digital count is recorded indicative of when the difference between the two becomes zero. Alternative mappings such a linear correspondence between analog input values and digital output values can be implemented via digital processing of each recorded count. The invention is particularly intended for use with sinusoidal reference waveforms to enable low-cost, high-precision A/D conversion at speeds much higher than are possible with piece-wise linear analog reference waveforms such as saw-tooth or triangle waveforms. The invention can be implemented with multiple A/D converters sharing a piece-wise non-linear analog reference waveform, with conversion cycles using increasing or decreasing waveform segments, and with compensation of comparator-induced errors.

Abstract: A circuit includes a switched-capacitor array for converting a digital signal into a corresponding amount of electric charge, a switching circuit, and a continuous-time reconstruction filter circuit. The switched-capacitor array includes a plurality of capacitors and a summing node to which the plurality of capacitors are connected. The switching circuit is coupled between the summing node and the continuous-time reconstruction filter circuit, and supplies a pulsed current signal to the continuous-time reconstruction filter circuit. The circuit may further include a gain stage coupled between the summing node and the switching circuit, for controlling a gain of the pulsed current signal. The gain stage may include a coupling capacitor. A digital signal is supplied to the switched capacitor array and converted into a corresponding amount of electric charge. The electric charge is supplied as a pulsed current signal to the continuous-time reconstruction filter circuit without converting into a voltage signal.

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.

Abstract: A serial-deserializer converts a high speed serial data input to a lower speed parallel output. By including this circuit on a chip, connections to the chip are made more easily. A gated voltage controlled oscillator provides clock signals to sample the data input at a high rate. The output signals are thus provided at a slower rate.

Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal.

Abstract: D/A-conversion of a Gray coded digital input signal is performed according to an inventive recursive Gray code-to-analog conversion algorithm. According to the recursive algorithm, the Gray code bits of the digital input are successively applied in the recursions of the algorithm, one Gray code bit for each recursion, and the analog output signal is generated by recursively updating an intermediate signal. In each recursion, the intermediate signal is selectively inverted in dependence on the particular Gray code bit that is applied in the recursion. The selective inversion of the intermediate signal is an inherent property of the Gray code-to-analog algorithm, and it is a key factor to reduce the accumulation of errors in a D/A-conversion. In a D/A-converter architecture based on the algorithm, the accumulation of offset errors will be low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations, further improving the performance of the D/A-converter.

Abstract: A signal processing system receives and mixes a plurality of analog input signals having a maximum frequency. Each analog input signal is connected to an input of a modulator producing a high frequency oversampled digital signal. Each high frequency oversampled signal is connected to an input of a first decimation filter which produces an intermediate frequency oversampled multiple bit signal. Each of the intermediate frequency oversampled signals is connected to a respective input of a first digital mixer which produces a single mixed multiple bit output signal. The single mixed multiple bit output signal is connected to a second decimation filter which produces a final digital output signal, at a frequency suitable for representing the mixed analog input signals.

Abstract: An analog-to-digital converter circuit is disclosed that is capable of converting both positive and negative analog input signals, and that is capable of operating as either an analog-to-digital converter or a digital-to-analog converter. The converter includes a modifying filter, a series of substantially identical converter stages, and a restoring filter. An original reference signal is provided, coupled to a resistor array to provide a stage reference signal to each converter stage that is equivalent to the value of the bit of an N-bit binary word corresponding to that stage. An incoming analog signal is modified to ensure that it is positive before applying it in parallel to the converter stages. Each converter stage compares the modified analog signal to the sum of its own reference signal and the value of all stage reference signals for prior converter stages where the digital output of the stage was a binary "1.

Abstract: A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage.

Abstract: In a switched capacitor type digital-to-analog (D/A) converter, a group of n bits of the binary word are applied to n parallel branches of the D/A converter, respectively. In a given branch, the corresponding bit is applied to a control terminal of a corresponding switch associated with a corresponding switched capacitor. Depending on the logic level of the bit, the switched capacitor is charged to a reference voltage or remains discharged. Then, the switched capacitor of the given branch is coupled by a transfer switch in parallel with a summing capacitor to provide for charge redistribution. The capacitances of the switched capacitor and of the summing capacitor are equal. The time allocated for either discharging the switched capacitor or charge redistribution is made shorter than the time allocated for charging the capacitor. Charging/discharging the capacitor is accomplished via a common transistor.