Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

Abstract: A circuit configuration for converting a one-bit digital signal at a given sampling frequency into an analog signal, includes a multiplication device having one input receiving the digital signal, another input receiving a reference signal and an output. A delay device receives the digital signal, delays the digital signal by one period of a sampling frequency and has an output. A further multiplication device has one input connected to the output of the delay device, another input receiving the reference signal and an output. An adding device has inputs each being connected to the output of a respective one of the multiplication devices and an output at which the analog signal is available.

Abstract: An N bit (where N is an integer) converter having separately formed voltage dividing resistance regions includes a semiconductor substrate of a first conductivity type. (N+1) well regions of a second conductivity type are each formed separately on the semiconductor substrate and an input resistance region of the first conductivity type having a high concentration of impurities is formed in a first well region of the (N+1) well regions. (N-1) ladder resistance regions of the first conductivity type having a high concentration of impurities respectively are formed in (N-1) well regions, each resistance of the (N-1) ladder resistance regions being approximately two times greater than a resistance of the input resistance region. An output resistance region of the first conductivity type having a high concentration of impurities is formed in an (N+1)th well region of the (N+1) well regions, a resistance of the output resistance region being approximately equal to the resistance of the input region.

Abstract: A digital-to-analog conversion circuit includes a first reference voltage generation circuit for generating a plurality of first reference voltages, a plurality of second reference voltage generation circuits for generating a plurality of second reference voltages created by dividing a difference in potential between adjacent two of the first reference voltages, a first selective control circuit for, upon receiving a first digital input signal group, selecting one of the first reference voltages and applying the selected one to a specified one of a plurality of signal lines during a first period, and selecting all of second reference voltages generated in one of the plurality of second reference voltage generation circuits and applying all the selected second reference voltages to signal lines other than the specified signal line, respectively, during a second period succeeding the first period, and a second selective control circuit for, upon receiving a second digital input signal group, applying a voltage

Abstract: An Ethernet-type local area network having multiport repeaters and nodes within a specified distance of the hub is able to communicate high speed digital data over multiple pairs of twisted-pair wires using long symbol group-type ternary coding. Bundle mode termination minimize impedance mismatches. Low-frequency collision detection circuitry permits detection of packet collisions on an a.c.-coupled network. Precise serialized digital to analog conversion is realized using chains of gates to form delay elements with precise delays.

Abstract: An n-bit analog processing circuit constructed with network swappers has n stages and an input port for inputting an analog signal to be processed. Each of the n stages includes first and second reference input ports, at least one swappable network having first and second terminals, and a switching element that is responsive to a digital input signal for varying a connectivity of the first and second terminals with respect to the first and second reference input ports. Each of the n networks has a primary electrical characteristic that is binarily weighted with respect to others of the networks. The primary electrical characteristic may be resistance, capacitance, capacitive reactance, inductance, inductive reactance, voltage potential, gain, transconductance, superconductance, time delay, permeability, electrical or optical conductor length, and/or winding turns.

Abstract: A digital-to-analog (D/A) converter used for a digital audio equipment, comprises a binary D/A converting circuit and a calculation processing circuit for receiving an analog signal derived from the binary D/A converting circuit. This D/A converter is capable of considerably reducing a load given to an LPF (low-pass filter) or, of omitting such an LPF. The binary D/A converting circuit outputs an analog signal value corresponding to each sampling point of a digital signal as a first analog output value, and also outputs an analog output signal value delayed by only 1 sampling period as a second analog output value. A difference calculating unit of the calculation processing circuit calculates a difference value between the first analog output value as a first analog input value, and the second analog output value as a second analog input value.

Abstract: A digital/analog converter including four D/A conversion.The D/A convertor comprises four D/A conversion parts (DA1) to (DA4). On a single semiconductor chip the D/A convertion parts (DA1) to (DA4) are arranged so that the D/A conversion parts (DA1) and (DA3) are symmetric with respect to a first center line (L1), the first and fourth D/A conversion parts (DA1) and (DA4) are arranged symmetric with respect to a second center line (L2) which crosses the first center line (L1) at right angles and the second and third D/A conversion parts are arranged symmetric with respect to the second center line. Although the locations of the resistances of each of the conversion parts produces errors, these cancel each other out due to their arrangement.

Abstract: A continuous ADC for generating a digital representation, corresponding to a given quantized voltage level, of an analog input signal and for updating the digital representation at times when the approximate amplitude of the analog signal changes from one quantized level to another. A preferred embodiment includes a set of serially connected output stages with each stage for generating a bit output signal included in the digital representation and an analog residual output signal having an amplitude equal to a linear combination of the amplitude of the input analog signal and the prior bit output signals.

Abstract: A bridge balancing circuit includes a bridge having a resistance change type sensor, a differential amplifier for extracting a voltage difference across two central nodes of the bridge, a comparator connected to the output terminal of the differential amplifier, a D/A converter an output terminal of which is connected to one of the two central nodes, and a controller for controlling the D/A converter. The differential amplifier and the comparator automatically detect a balanced point of the bridge, and the controller maintains a balanced state of the bridge.

Abstract: A peak-valley detector of an analog signal which provides a digital output of the analog signal. A digital counter is used having an output coupled to a digital-to-analog convertor. The output of the digital-to-analog convertor is compared to an input analog signal. The output of the comparator is used to control the input of a clock signal to the counter. A selective invertor controls whether the comparator's output allows counting for signals above or below the digital-to-analog convertor's output level.

Abstract: An operational amplifier is provided and includes at least two input terminals of one polarity and another input terminal of the opposite polarity. The amplifier includes an amplifying portion which comprises a differential section for receiving input signals applied to the input terminals. The differential section includes at least two differential amplifiers which form difference signals from the input signals. A summing section receives the difference signals and forms a sum result therefrom. A multiplying section provides an amplification gain to the sum result to form an output signal of desired gain. The amplifier is also provided with a feedback for applying an input signal to one of the input terminals, the output signal. The amplifier can be configured to provide amplification gains of 2, 1/2, -1 and 1.

Abstract: A digital-to-analog converter comprising: a distributing circuit (2, 3, 4, 5; 2, 13, 14-26) for distributing data pulses, which are bit-serially supplied at constant time intervals, into a plurality of routesand for providing them as pulses having a constant width; and a converting circuit (12) for adding together the pulses from the distributing circuit and thereby for converting them to an analog output. Such a circuit arrangement can provide pulses for conversion to analog form which all have an identical waveform and an identical area, and errors caused by the difference between the rise and fall times of the pulses can be eliminated and therefore D/A conversion characteristics can be improved.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal comprises a series arrangement of at least two integrating circuits (1,2) and a control unit (18) for supplying a first and a second control signal (S1, S2) to the first and the second integrating circuit. The integrating circuits are adapted to perform an integration step under the influence of the first and the second control signal. The control unit is adapted to generate, in this order, the first control signal M1 times, the second control signal M2 times, the first control signal M3 times and the second control signal M4 times. For converting arbitrary digital signals M2+M4 is equal to a constant (k). Due to this measure an offset voltage which is independent of the value of the n-bit digital signal to be converted is produced at the output (8) of the converter. For converting n-bit digital signal the constant k is preferably taken to be equal to 2.sup.p in which p.ltoreq.n.

Abstract: A digital-to-analog converter includes a sampled data sigma-delta modulator to resample and coarsely quantize the digital samples to be converted. The coarsely quantized samples are converted to sequences of pulses which are applied to a pulse sensitive analog integrator to develop analog representations of the digital signal.

Abstract: This circuit arrangement includes an interpolation filter (3) which converts the incoming signal values (A) into interpolated signal values (B) of increased repetition frequency. The interpolated signal values (B) are reduced in word length by means of a quantizer (4a) and by quantization error feedback through an error filter (25). A D/A converter (6) consists of two or more nonweighted switching stages connected in parallel. The activated switching stages deliver currents which are added together at the output end. The D/A converter (6) is controlled by a control circuit (5) which processes the output signals (D) of the quantizer (4a). The activated switching stages are continuously interchanged on a cyclic basis, so that relative resistance tolerances in the circuit average out.

Abstract: A D/A converter includes a first stage capacitor ladder, a second stage capacitor ladder, a coupling capacitor, (l+m) switches, and a short-circuiting switch. The first stage capacitor ladder includes l capacitors having one side electrodes commonly connected to a first point and capacitances binary-increased from 2.sup.0.C to 2.sup.l-1.C (l is a natural number and C is a unit capacitance). The second stage capacitor ladder includes m capacitors having one side electrodes commonly connected to a second point and capacitances binary-increased from 2.sup.0.C to 2.sup.m-1.C (m is a natural number). The coupling capacitor has a capacitance of 1.C and is connected between the first and second points. The (l+m) switches selectively connects another side electrodes of the (l+m) capacitors to a first or second reference voltage in response to an (l+m)-bit digital input signal. The short-circuiting switch is connected between the first reference voltage and the first point of the first stage capacitor ladder.

Abstract: An adaptive single-bit encoder and decoder has its adaptive function determined by dynamically dividing the message frequency band into delta-sigma and delta modulation regimes of operation. IN a practical embodiment this is accomplished by varying the corner frequency of a variable-frequency low-pass filter in a leaky integrator so that below the corner frequency the operation is that of delta-sigma modulation and above the corner frequency the operation is that of delta modulation. An adaptation control circuit removes the clock signal component from the encoded bit stream to provide an analog signal representative of bit stream information or loading for use in generating the control signal. The analog signal is peak rectified, smoothed, and (optionally) non-linearly processed to provide the control signal.