Abstract: Generation of segmented sawtooth waveforms. A desired waveform is divided into intervals. A slope is associated with each interval. A charge current representing the slope is applied to a timing capacitor during each interval. Responsive to a clock signal, a counter chain indexes a digital memory which provides values to a digital to analog converter. The output of the digital to analog converter drives an adjustable current source to charge the timing capacitor.

Abstract: A numerically controlled oscillator (NCO) is defined to include counter circuitry and integrator circuitry. The counter circuitry includes a first input for receiving a minimum count value, a second input for receiving a maximum count value, and a third input for receiving an increment value. The counter circuitry is defined to generate a counter digital waveform that oscillates between the minimum count value and the maximum count value with a linear slope corresponding to the increment value. The integrator circuitry is defined to compute a running integral of the counter digital waveform. The running integral of the counter digital waveform represents a sinusoidal digital waveform output of the NCO.

Abstract: A clock generator includes input circuitry for receiving an input signal and generating a memory address therefrom. A memory stores digital data indexed by the memory address which represents at least a portion of an analog clock. A digital to analog converter converts data retrieved from the memory to generate the analog clock which is then filtered by a filter and then converted into digital output clock.

Abstract: A low power analog output circuit is disclosed that utilizes a low pass filter driven by a bit stream to render a waveshaped output signal based upon a raw digital data signal. The analog output circuit includes sequential bit pattern selection logic that receives as an input, the raw digital data signal. The analog output circuit also includes a bit pattern storage that specifies bit stream sequences that are selected in accordance with control signals generated by the state machine based upon its current state and the current raw digital data signal. The analog output circuit includes an output stage driven by a digital input signal corresponding to values provided by a bit stream sequence selected from the bit pattern storage. The output stage comprises a low pass filter circuit having an effective time constant that is greater than a hold period associated with a single bit of the bit stream sequence that drives the digital input signal.

Abstract: A modulating mechanism is provided comprising a first storage and a corresponding first DAC, and a second storage and a corresponding second DAC. The first storage stores an adjusted digital representation of a first waveform, while the second storage stores an adjusted digital representation of a second waveform. The adjusted representation of the first waveform is adjusted to compensate for the deviation effects experienced by the first DAC (e.g. amplitude deviation, DC offset, non-linearity, etc.). The adjusted representation of the second waveform is adjusted to compensate for the deviation effects experienced by the second DAC. In effect, the adjusted representations of the first and second waveforms cause the DAC's to exhibit the proper behavior, despite the presence of the deviation effects. By storing and using adjusted digital representations of waveforms in this manner, many benefits can be realized, including for example, eliminating the need for any analog compensation circuits.

Abstract: The present invention provides a technique that prevents a shift of a driving waveform due to accumulation of errors in a process of generating the driving waveform to drive driving elements on a print head. The technique of the present invention successively sums up a plurality of gradient data at a preset calculation period to give a result of summation and carries out digital-to-analog (D-A) conversion with regard to only specific upper columns in the result of summation in synchronism with the preset calculation period, so as to generate a driving waveform. Each gradient data represents a local gradient of the driving waveform and is stored in a memory. In the process of generating the driving waveform, the technique of the present invention corrects the result of summation to a preset value under a predetermined condition. One preferable embodiment clears specific lower bits in the result of summation in synchronism with a floor signal.

Abstract: A signal synthesizer according to the present invention produces a high speed or high frequency carrier waveform without employing an ASIC or FPGA operating at a sampling rate of greater than twice the carrier frequency. The signal synthesizer basically simulates a high speed or high frequency direct digital synthesizer with a plurality of low speed or low frequency direct digital synthesizers. The low speed synthesizers are operated in parallel and each one produces an intermediate carrier waveform with a frequency less than the desired carrier frequency. The intermediate carrier waveforms are subsequently multiplexed together to form a high frequency digital carrier waveform that is subsequently converted to an analog signal with a high-speed digital-to-analog converter. In addition, the signal synthesizer may perform phase, frequency and/or amplitude modulation.

Abstract: A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence on the resistance ladder to generate the ramp voltage. By using control logic to decode the sequence, a looped shift register is used to close the switches.

Abstract: A digital-to-analog converter for generating output waveforms with less distortion without the need for high-speed components. The digital-to-analog converter comprises a D/A converter, four voltage holding sections, four step function waveform generators, a voltage summing section, two integrators and a timing controller. The voltages corresponding to four sequential digital data inputs are held in the voltage holding sections, respectively, and the step function generators generate step function waveforms at the voltage levels corresponding to the held voltages. The voltage summing section combines the step function waveforms generated in the step function waveform generators, and two integrators integrate this combined waveform two times, thus producing a continuous analog voltage composed of the input digital data.

Abstract: A phase-to-sinusoid-amplitude conversion system and method for use in, for example, direct digital frequency synthesizer applications. The system and method convert phase data to signal amplitude data using an approximation of the first quadrant of a sine function using a plurality of linear line segments of preferably equal length. Each segment is defined with a lower horizontal-axis bound; a lower vertical-axis bound; and a slope represented as a sum of a plurality of slope elements. Based on the approximation and for a given phase angle a set of values are evaluated, for each linear line segment, representing a product of (i) a horizontal displacement representing a difference between the prescribed phase angle and the lower horizontal-axis bound xi of a selected linear line segment where, for example, xi<X<xi+1 and (ii) each one of the slope elements of the selected linear line segment.

Abstract: A digital-analog converter for producing less distorted output waveforms without the need for an increase in the operating speed of components. A D/A converter 1 comprises a memory 10, an address counter 12, a B spline function generation circuit 14, four sampling function generation circuits 16, three delay circuits 18, four amplifiers 20, and three adding circuits 22, 24 and 26. Four items of digital data supplied one after another in the predetermined time interval T are stored in the memory 10. The gain of each of the four amplifiers 20 is set according to the corresponding digital data. The four sampling function generation circuits 16 generate signal waveforms of the sampling function, which appear individually in points a time T away from one another. The signal waveforms are amplified in the amplifier 20 and added to produce an analog signal associated with the interpolation value.

Abstract: A digital-to-analog converting method operating under two clock signals of different periods is disclosed. The method includes steps of monitoring a phase relationship between the two clock signals; starting transmission of a plurality of pre-stored series of waveform samples in response to each rising edge of the first clock signal, wherein a phase difference is present between every two adjacent series of waveform samples; outputting the waveform samples of each series in response to rising edges of the second clock signal; and selecting one of the plurality of pre-stored sets of waveform samples to be converted into an analog signal according to the phase relationship. The various pre-stored series of waveform samples having therebetween phase differences are optionally used for phase compensation so as to reduce the clock jitter between the two clock signals. A digital-to-analog converter for implementing the above-mentioned method is also disclosed.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises a multiplying section 1, four data holding sections 2-1 through 2-4, four data selectors 3-1 through 3-4, an adding section 4, a D/A converter 5, and two integrating circuits 6-1 and 6-2. Input data is multiplied by four multiplicators by the multiplying section 1, and the four multiplication results are held, as one set, in the data holding sections. The data selectors read out the data held in the four data holding sections in a predetermined order and generate step function data. The adding section adds the values of the step functions outputted from the four data selectors. Furthermore, a stepwise analog voltage corresponding to the sum is generated by the D/A converter 5 and integrated twice by means of the two integrating circuits 6-1 and 6-2.

Abstract: A digital-to-analog conversion circuit (105) includes a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

Abstract: The present invention refers to a digital to analog conversion circuit able to transform an input digital signal having n bit in a signal having a thermometric code and to convert it in an analog output signal.

Abstract: An apparatus for signal processing discrete-time values for signal-sampling systems, such as digital/analog converters, switched capacitor filters, direct digital synthesizers, sample-and-hold circuits and the like, having means for producing discrete-time values and means for processing discrete-time values into analog values, is distinguished in that at least one group of at least two signal-sampling systems, which, in particular, have the same input signals applied to them, is of parallel-connected design, means are provided for producing sampling frequencies with a shifted phase angle and for driving the respective sampling system with a shifted phase angle for the particular frequency produced, means are provided for summing the signals from the signal-sampling systems, and means are provided for further processing/converting the summed signals from the sampling systems into analog signals.

Abstract: An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform.

Abstract: Simplifying functions representing raised sine or cosine curves to functions representing simple sine or cosine curves makes it possible to implement an electrical equivalent circuit for a ramp generator. The core of the ramp generator with an output power level controller is second-order direct-form feedback structure (60), which forms a digital sinusoidal oscillator. The initial values of two state variables x2(n), x2(n+1) of the oscillator are chosen so that they both contain a predetermined first constant value. This first constant value will emerge as the amplitude value of the pure sine wave generated by the oscillator. Particularly the first constant value is equal to the desired nominal level A of the ramp minus the starting level. A second constant value (A+dc) is added to the oscillator output. The added result is scaled (66) so that the nominal power level is A. A multiplexer (67) keeps the power level between the ramps constant.

Abstract: The present invention discloses a device for converting a digital input into an analogue output, comprising means for generating a binary pulse signal in dependence on said digital input, a filter for filtering said binary pulse signal to obtain said analogue output where the level of the analogue output depends on the relation of high and low level pulses of the binary pulse signal during a period and the precision of the analogue output depends on the number of binary pulses during the period. The high and low level pulses in the binary pulse signal are spread through said period.

Abstract: A reference generator includes a memory that stores reference data which, when clocked out of the memory, produces an ATSC compliant VSB reference signal substantially free of sub-harmonics of the clock signal. A digital-to-analog converter converts the clocked out reference data to an analog signal. The analog signal may be at low IF. An up converter is arranged to upconvert the output of the digital-to-analog converter to an RF reference signal. The RF reference signal can be used, for example, to calibrate a VSB demodulator.

Abstract: A waveform generator 30 for generating a desired waveform includes a plurality of rectangular wave generators (40a to 40n) for generating a plurality of rectangular waves and a waveform synthesizing unit 42 for synthesizing the rectangular waves to generate a multi-level synthesized wave, and generate the desired wave based on the synthesized wave.

Abstract: A data conversion device for synthesizing digital data composed of two or more components (of which each consists of a series of one-bit digital data) so as to output a single analog signal has: a switch circuit for selecting one of the components of the digital data at a time by dividing a predetermined period into intervals having predetermined lengths of time in accordance with a select signal; a timing generator for generating the select signal; a current feeding circuit for feeding a current that flows in one or another direction in accordance with the output of the switch circuit; and a current-to-voltage conversion circuit for converting the current into a voltage so as to produce an analog signal.

Abstract: A time based digital to analog converter is presented in which known reference voltages are used to create variable period waveforms which, when combined according to a desired computation, can convert digital words into a sinusoidal signal of a precision variable. To illustrate the application of the present invention, a hemispherical resonator gyroscope (HRG) operating in force rebalance is presented wherein a time based digital to analog converter with a variable period output controls the HRG electronics in nulling the standing wave. A rate of the standing wave is calculated, and a software component calculates the fraction of the maximum rate needed to oppose and null the initial rate of the standing wave. The fraction of the maximum rate is converted to digital words corresponding to the number of periods of a clock connected to the circuit.

Abstract: A non-linear function of an input voltage is provided by cascading multiplying digital-to-analog converters (mDACs) to provide a polynomial power series to approximate the non-linear function. Weighting functions are provided by fixed gain amplifiers.

Abstract: Various modem designs are described, along with systems that use the modem designs for communicating data between a large number of remote locations and one or more central locations preferably over CATV. One aspect features a modem having a transmitter which uses a state machine and digital waveform signals stored in a memory to create a modulated signal. Another aspect features a modem having a receiver which uses a digital correlator including an SRAM for detecting a bipolar phase shift keyed signal. Still another aspect features a modem comprising an oscillator circuit having a feedback loop, wherein the feedback loop utilizes a downlink signal, and a protection circuit which prevents a malfunction in the modem from causing system-wide shutdown.

Abstract: A baseband simulation system is disclosed for testing an RF subsystem of a communication device, such as a cellular telephone, cordless telephone, etc. A preferred embodiment has a computer connected to an interface card which in turn is connected to a baseband simulation subsystem. The baseband simulation subsystem is connected to the RF subsystem under test. The baseband simulation subsystem includes three ports: a timing and control (TAC) port, an IQ port, and general purpose input output (GPIO) port. The TAC port receives a master clock signal from an external source and generates plural clocks therefrom. The IQ and GPIO ports receives at least one of these plural clocks. In a transmit mode, in response to one or more of the clocks generated by the TAC port, the IQ port retrieves from its memory prestored discrete I and Q samples and reconstructs therefrom arbitrary transmit analog i and q signals which are provided to the RF subsystem under test.

Abstract: A cycle-modulating DTMF generator for generating a DTMF signal; the generator comprises a programmable time-pulse generator, counters or up/down counters, a memory unit for storing data, a digital adder, and a digital-to-analog converter. The circuit of such generator is substantially a digital circuit so as to overcome the problem of signal distortion, which usually exists in an analog circuit.

Abstract: A cost effective waveform-generating apparatus that generates accurate and precise waveforms is disclosed. The present waveform-generating apparatus includes a memory for storing a sequence of sampled amplitudes of a waveform, said sampled amplitudes constituting at least two periods of said waveform; a counting circuit, electrically connected to the memory, responsive to a clock signal for generating counting signals; a controlling circuit, electrically connected to the memory and the counting circuit, responsive to the counting signals for controlling the memory to output the sampled amplitudes recurrently; and a digital to analog converter, electrically connected to the memory, for converting the recurrent sampled amplitudes into an analog output.

Abstract: A direct digital synthesizer (DDS) 3 comprises a phase accumulator for generating phase data in response to frequency data, periodic signal converters for generating a sine signal and a cosine signal in response to the upper bits of the phase data, phase error signal generating means for generating a phase error signal in response to the lower bits of the phase data, a multiplier for multiplying the cosine signal and the phase error signal to produce a spurious cancel signal, and a subtracter 35 for subtracting the spurious cancel signal from the sine signal, thereby obtaining a resultant sine signal free from spurious noise.

Abstract: A sinusoidal wave generation apparatus comprising a pulse generator for generating a pulse signal of a precise frequency in response to a clock signal from an oscillator, a frequency divider for dividing the precise frequency of the pulse signal from the pulse generator by a desired ratio to output a desired frequency of pulse signal, an up/down counter for alternately up-counting and down-counting the frequency-divided pulse signal from the frequency divider and outputting up/down-counted values corresponding to digital triangular wave data, a digital/analog converter for converting the digital triangular wave data of the up/down-counted values from the up/down counter into an analog triangular wave signal, a low pass filter for filtering a harmonic component of the analog triangular wave signal from the digital/analog converter to output a sinusoidal wave signal, a comparison circuit for comparing the up/down-counted values from the up/down counter with predetermined upper and lower reference values, respec

Abstract: A digital-to-analog converter includes a generator responsive to a digital input signal, a set of switches each being directly connected to the generator, and a first and a second terminals connecting therebetween a resistor device having a plurality of nodes directly connected to the switches in order that a node voltage can be obtained between one of the nodes and one of the terminals to serve as an analog signal. Such converter has a low distortion/noise and can be used in a broad source voltage scope.

Abstract: A digital to analog converter (10) and method is provided in which a plurality of digital to analog converter cells (16) generate an analog output signal based on a digital input signal, the cells being characterized by a switching threshold. An error signal circuit (22) generates a control voltage signal for controlling a first variable delay register (12). Signals latched by the first variable delay register (12) are characterized by rising and falling edges, and the first variable delay register (12) is controlled by the control voltage signal such that the rising and falling edges cross the switching threshold at substantially the same time.

Abstract: A system provides I and Q baseband analog modulation signals for use in GMSK modulation responsive to serial bits of digital data. The I baseband modulation signal is represented by I(t)=cos [2.pi.f.sub.m .intg.g(t)dt] and the Q baseband modulation signal is represented by Q(t)=sin [2.pi.f.sub.m .intg.g(t)dt], wherein f.sub.m is the modulating frequency and g(t) is a filtered version of the serial bits of digital data. The system includes an input for receiving the serial bits of digital data, a memory including addressable memory locations for storing data representing the waveform amplitudes of the I and Q modulation baseband analog signals, and an address generator for addressing selected ones of the memory locations responsive to the serial bits of digital data. The system further includes digital to analog converters coupled to the memory for receiving the data stored at the memory locations addressed by the address generator and for converting the data to the I and Q modulation baseband analog signals.

Abstract: A digital to analog converter, wherein a time/voltage array is programmable, to determine which of the possible reference voltages will be enabled by which of the control inputs. Anther set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determined which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates, so that the polarity of a bipolar output can be reversed.

Abstract: A digital-to-analog converter (DAC) is disclosed which uses an oversampled modulation technique followed by an analog lowpass filter to generate an output waveform with four precisely controlled amplitude levels for 2B1Q data transmission applications. The DAC accepts a 2-bit input word at the baud rate and generates one of four possible analog output amplitudes having relative ratios of +3, +1, -1, and -3.

Abstract: In an AC signal generating apparatus a digital sine wave signal of a set frequency, generated by a digital sine wave signal generating part, is converted by a D/A converter to an analog sine wave signal and is then output. The output sine wave signal is converted by an output detector to a voltage mean value, and the difference between it and a reference value is obtained by a comparator. The difference is negatively fed back, as a reference voltage, to the D/A converter to control its conversion gain so that the difference may approach zero. Thus, a highly accurate sine wave signal is obtained.

Abstract: A circuit for interfacing switches to a component which allows the positions of the switches to be determined by the component. The component includes an input port and an output port. A switch network which is a parallel combination of two or more series combinations of a resistor and a switch is connected between the input and output port. A capacitor is connected between the input port and ground. The component determines switch positions by outputting a voltage on the output port and determining the time for the capacitor to charge to a predetermined value. Since each series combination has a unique resistance, the position of the switches therein can be determined in accordance with the capacitor charging time.

Abstract: A data generator generates digital data at a sampling time interval .sub..DELTA. T (sampling frequency f.sub.s =1/.DELTA.T), and the three latest items of digital data V.sub.-1, V.sub.0, V.sub.+1 are repeatedly latched successively in three latch circuits every 3.multidot..sub..DELTA. T. A pulse response signal generator outputs unit pulse response signals of period 3.multidot..sub..DELTA. T at the time interval .multidot..sub..DELTA. T, and three multiplying-type DA converters multiply these three unit pulse response signals .phi..sub.0 (t+.sub..DELTA. T), .phi..sub.0 (t), .phi..sub.0 (t-.sub..DELTA. T) by the digital data V.sub.-1, V.sub.0, V.sub.+1, respectively, at a speed of a.multidot.f.sub.s (a times in time .sub..DELTA. T). The outputs of these multiplying-type DA converters are combined into an analog signal S.sub.A, which is delivered as an output.

Abstract: A converter for producing the function V.sub.out =V.sub.bias =V.sub.swing (1-2D), in which a DAC is combined with an operational amplifier and (typically) three or four resistors. A function of the voltage V.sub.swing, or a current corresponding thereto, is applied to the reference voltage input terminal of the DAC. The variable D is the DAC's digital input code, expressed as a decimal or fraction in the range between 0 and 1. The DAC output provides a suitably scaled and signed signal which is added to or subtracted from the offset signal V.sub.bias to produce V.sub.out.

Abstract: A circuit for generating an analog sine voltage from a digital phase input (11) employing a memory (13) storing sine and cosine values and a correction value for each phase and first and second digital-to-analog converters (DACs) (19,21). For each digital phase input (N), selected sine and cosine values are combined and the result is read out to the first DAC (19), which generates an analog sine approximation voltage. A corresponding correction value is simultaneouosly read out to the second DAC (21), whose output is scaled by an attenuator (23) to provide a correction voltage for correcting the deviation in the output voltage of the first DAC (19) from the ideal sine voltage value.

Abstract: A low cost, high quality converter for generating an amplitude modulated signal in response to a sequence of digital words representing a modulation signal, such as a video image. The converter receives the sequence of digital words at an input rate. The input sequence of digital words is combined with a sequence of factors at a sample rate to generate a second sequence of digital words at the sample rate representing the amplitude modulated signal. The second sequence of digital words is then converted to the amplitude modulated signal. The sequence of factors is a sequence of cosines of the carrier frequency at the carrier phase angle of 45, 135, 225 and 315 degrees. The value of these cosines are +0.707, -0.707, -0.707, +0.707 respectively. These values are normalized to 1 so that they become a sequence of +1, -1, -1, and +1. Multiplication by the sequence of factors is thus carried out by alternately inverting the input sequence of digital words at one-half the sample rate.

Abstract: A continuous analog signal is produced by successively generating digital data V.sub.K (K=. . . , -4, -3, -2, -1, 0, 1, 2, 3, . . . ) every predetermined sampling period T, repeatedly generating, successively at a period 3T, signals .phi.(t+T), .phi.(t), .phi.(t-T), where a unit pulse response signal .psi.(t) is expressed by.psi.(t)=.SIGMA.A.sub.K .multidot..phi.(t-K.multidot.T) (K=-.infin..about.+.infin.)using a signal .phi.(t) (0.ltoreq.t.ltoreq.3.multidot.T) expressed by three piecewise polynomials, computing C in accordance with the equationC=.SIGMA.A.sub.-K .multidot.V.sub.K (K=-M.about.m)every sampling period T, where V.sub.0 represents digital data prevailing at the present time, cyclically storing the results of computation as C.sub.-1, C.sub.0, C.sub.1 in successive fashion, and converting the digital data into an analog quantity in accordance with the equationC.sub.-1 .multidot..phi.(t+T)+C.sub.2 .multidot..phi.(t)+C.sub.3 .multidot..phi.

Abstract: A method and apparatus for converting a digital signal into a band-limited analog signal with variable bandwidths, a high level of performance, high spurious frequency rejection, and simple implementation, employing polyphase interpolating digital filters, a fixed-sampling rate digital to analog converter, and a fixed-frequency analog low-pass filter.