Abstract: An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.

Abstract: A level shifter, a digital-to-analog converter (DAC), and a buffer amplifier, and a source driver and an electronic device including the same are provided. The source driver includes a level shifter configured to receive digital bits and provide a level-shifted output signal; a DAC including a resistor string configured to provide a plurality of gradation voltages formed by an upper limit voltage and a lower limit voltage being received through one end and the other end, and an N-type metal oxide semiconductor (NMOS) switch and a P-type MOS (PMOS) switch configured to be controlled by the level-shifted output signal and output a gradation voltage corresponding to the level-shifted output signal; and an amplifier configured to amplify a signal provided by the digital-to-analog converter, and the lower limit voltage is provided to a body electrode of the NMOS switch.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including a first sample and hold circuit for sampling an input signal, a first ADC configured to generate a digital representation of the sampled input signal from the first sample and hold circuit, and a first digital-to-analog converter (DAC) responsive to the output of the first ADC and configured to generate an analog representation of the digital representation of the sampled input signal. A control processor is provided and configured to generate a digital control signal. A current control circuit is responsive to the digital control signal for generating an analog current control signal for selectively altering a characteristic of at least one of the first ADC and the first DAC.

Abstract: An input circuit for processing an analog input signal in the form of an analog measurement signal with a modulated additional signal and for converting the input signal into a serial bit stream having a frequency distribution of high levels which is proportional to the input signal, and a method for operating such an input circuit, the input circuit including a device for comparing an instantaneous voltage value of the input signal with a variable comparison value and a device for adapting the comparison value to an instantaneous value of the generated bit stream, is provided.

Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.

Abstract: An apparatus of a Digital-to-Analog Converter (DAC) is provided. The apparatus includes a logic circuit for performing a logical operation based on a combination of bit values b0 through bN-1 of a digital code, and a plurality of switches for controlling an output state of a plurality of current cells based on an output of the logical operation, wherein the plurality of the current cells respectively output currents under a control of respective ones of the plurality of switches.

Abstract: Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.

Abstract: A gamma voltage generator includes an RGB common gamma voltage generation section configured to generate RGB common gamma voltages using corresponding gamma reference voltages among a plurality of gamma reference voltages; and at least two of an RG gamma voltage generation section configured to generate RG gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, an R gamma voltage generation section configured to generate R gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, a G gamma voltage generation section configured to generate G gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages, and a B gamma voltage generation section configured to generate B gamma voltages using corresponding gamma reference voltages among the plurality of gamma reference voltages.

Abstract: A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.

Abstract: An impulse waveform generating apparatus comprises an oscillator for generating a reference signal having a center frequency in a frequency band of an impulse to generate, a timing matching circuit for shifting a phase of the reference signal by 90 degrees, a frequency demultiplier for dividing a frequency of the phase shift signal and obtaining a timing signal having a frequency component having a frequency width of an impulse to generate, a memory storing a waveform shape table, a waveform forming section for forming a waveform in synchronism with the timing signal, according to information of a shape table having a predetermined waveform, a low-pass filter for obtaining an envelope signal from an output signal of the waveform forming section, and a waveform generating section for changing an amplitude of the reference signal according to a value of the envelope signal.

Abstract: A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: A converter of 6-bit input includes a reference voltage generating circuit generating 17 reference voltages, a first switch circuit having 19 switch pairs each including MOS transistors for selecting two adjacent reference voltages in accordance with the four most significant bits, a second switch circuit including a series circuit of MOS transistors for dividing the selected two reference voltages into four to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower of the selected two reference voltages or one of the three intermediate voltages. In a second mode in which a gray level having a smaller ON-resistance of a MOS transistor than that in the first mode is selected, the number of MOS transistors used in the first and second switch circuits for voltage division is increased.

Abstract: A DA converter circuit configured to output a gray scale voltage to a liquid crystal display panel is disclosed, wherein the gray scale voltage is generated from reference voltages fewer than gray scales of the liquid crystal display panel and it is still to be able to prevent deterioration in display quality of the liquid crystal display panel. A DA converter circuit of at least one embodiment includes: a reference voltage generator circuit for generating reference voltages; a selector circuit for selecting one or two reference voltages from the reference voltages in according to the inputted gray scale value; and a voltage follower circuit for outputting the gray scale voltage that is the one reference voltage thus selected or a mean value of the two reference voltages thus selected. Reference voltages are generated, in at least one embodiment, as a variety of gray scale voltages.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A scrambling system for a digital-to-analog converter (DAC) includes a DAC that receives a digital input word and a scrambling module that randomly selects at least one of a plurality of current sources based on the digital input word. The DAC outputs an analog signal based on the at least one of the plurality of current sources.

Abstract: A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit.

Abstract: A source driver and a digital-to-analog converter (DAC) thereof are provided. The DAC converts an input data into an analog voltage. The DAC includes a reference voltage generation unit, a switch unit, and a selection unit. The reference voltage generation unit provides a plurality of voltage levels. The switch unit is coupled to the reference voltage generation unit and determines whether to output the voltage levels, wherein the switch unit is turned off during a data conversion period of the input data. The selection unit is coupled to the reference voltage generation unit via the switch unit, and the selection unit selects one of the voltage levels output by the switch unit according to the input data, wherein the selected voltage level is served as the analog voltage output by the DAC.

Abstract: A D/A converter includes a plurality of current sources configured to be on or off according to input digital data; a constant voltage source configured to apply a constant voltage to the current sources; current supply wirings provided between the constant voltage source and the respective current source, the current supply wirings respectively having equal length from the constant voltage source to the respective current source; ground-side wirings summing up output currents from the plurality of current sources; and output terminals connected to the ground-side wirings, the output terminals outputting analogue data corresponding to the input digital data.

Abstract: A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

Abstract: An embodiment of the present invention is a technique to design a DAC. A double-summed-to-zero (DSTZ) graph is created having a plurality of nodes linked by a plurality of directed branches. The DSTZ graph represents a finite state machine (FSM) that generates a sequence for a switching block used in a mismatch-shaping digital-to-analog converter (DAC). Each of the plurality of nodes represents a state in the FSM. The DSTZ graph has a total work function and a total potential energy summing to zero for a cycle traversal. A switching sequence is generated starting from a reference node in the plurality of nodes in response to an input sequence. The reference node has a zero potential energy.

Abstract: For example, in order to convert a 6-bit digital signal into an analog signal, a reference voltage generating circuit for generating 17 reference voltages, a first switch circuit having 19 switch pairs each including a MOS transistor for two reference voltages adjacent to each other in accordance with upper four bits, a second switch circuit including a series circuit of 12 MOS transistors and for dividing the difference between the two selected reference voltages using combined ON-resistances into four so as to obtain three intermediate voltages, and a third switch circuit for selectively outputting the lower voltage of the two selected reference voltages or one of the three intermediate voltages in accordance with lower two bits, are provided.

Abstract: An analog-to-digital converter has a resistor string that generates a series of voltages. An upper selector selects voltages at the upper end of the series. A lower selector selects voltages at the lower end of the series. A pair of midrange selectors select a pair of adjacent voltages in the middle range of the series. A midrange voltage generator generates further voltages spaced between the two selected midrange voltages. An output selector selects one of the further voltages. The selectors are controlled by various bits of a digital input signal. The voltage selected by the upper selector, lower selector, or output selector becomes an analog output signal. This analog-to-digital converter has comparatively few resistors and transistors and can generate accurate voltages for driving a gray-scale display.

Abstract: A decoder circuit that selects a grayscale voltage responsive to digital input includes a first transistor circuit that selects grayscale voltages greater than a certain voltage and a second transistor circuit that selects grayscale voltages less than the certain voltage. The two transistor circuits are formed in separate substrates, one substrate being a well formed in the other substrate, or both substrates being wells formed in a third substrate. The substrate of the first transistor circuit is biased at a higher potential than the substrate of the second transistor circuit. This biasing scheme enables all selected grayscale voltages to propagate quickly through the decoder circuit.

Abstract: A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

Abstract: In each of sub-decoding circuits at a first stage provided for a plurality of output candidates arranged adjacently, for selecting corresponding output candidates in accordance with a bit of multibit data for transmission to subsequent stage sub-decoding circuits, unit decoders are arranged in parallel in a direction perpendicular to an arranging direction of the output candidates. A size in a vertical direction along which reference voltages of the output candidates of a decoding circuit are arranged can be reduced without increasing a size in a horizontal direction.

Abstract: A microcontroller is provided, which includes a control unit (UC), at least one digital to analog converter (DAC) as a peripheral of the said control unit, and a buffer register located between the said control unit and the said converter, receiving data and a first command to transfer the said data from the said control unit. The microcontroller includes means of synchronisation of the said converter including a register inserted between the said buffer register and the said converter, the said register receiving a second transfer command independent of the said control unit.

Abstract: There is provided an arbitrary waveform generator that generates an arbitrary waveform. The arbitrary waveform generator includes a waveform pattern generating section that generates pattern data showing a pattern of the arbitrary waveform, a digital-analog converting section that outputs the arbitrary waveform based on the pattern data, and a correction processing section that corrects the pattern data and inputs the corrected data into the digital-analog converting section based on a value made by differentiating the pattern data and a time constant of a path through which the arbitrary waveform output from the digital-analog converting section passes.

Abstract: A system, apparatus, method and article to emulate a filter are described. The apparatus may include a digital-to-analog converter having an impulse response emulator, the impulse response emulator to receive multiple digital signals each having a predetermined waveform, and convert a sequence of bits from each digital signal to a predetermined analog waveform corresponding to the sequence of bits. Other embodiments are described and claimed.

Abstract: Devices and methods to test high speed analog-to-digital and digital-to-analog signal converters are provided. According to one embodiment, a testing device can comprise an output, a mixer, and an input. The output can provide a signal, and the mixer can receive the signal and provide a test signal to a data converter having a sampling frequency. The test signal can be spectrally impure. The input can sample the data converter output at a frequency less the sampling frequency so that the data converter output is under sampled. According to another embodiment, a first set of data converters are tested to obtain a mapping function that relates dynamic specifications to device signatures. Then a second set of data converters can be tested and based on their device signatures mapped with the mapping function, dynamic specifications for the second set of data converters can be obtained. Other embodiments are also claimed and described.

Abstract: In one embodiment, a micro electromechanical system (MEMS) driver circuit receives a pulse-width modulated (PWM) signal and uses it to control a voltage at a MEMS cell. The driver circuit further includes a current source, a capacitor, and a reset circuit that can discharge the capacitor. The voltage at the MEMS cell can be controlled in proportion to the pulse width of the PWM signal. In another embodiment disclosed, a MEMS driver circuit receives a first PWM signal and a second PWM signal. Each PWM signal is coupled to a current source. One current source can provide a course current control and the other current source can provide fine current control. The driver circuit can further include a capacitor and a reset circuit for discharging the capacitor. The voltage at the MEMS cell can be controlled in proportion to a summation of the first and second current sources. According to another aspect of the embodiments, a method of controlling a voltage at a MEMS cell is disclosed.

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time ?tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: An apparatus for producing a natural electromagnetic alternating field close to a user's body. The natural electromagnetic alternating field is similar to an area of pleasant weather (Sferics), to compensate for electrical stress acting on a user. The field can also be used for positive stimulation of the well-being of the user. The apparatus has a means for producing the alternating field and a means for transmitting the alternating field.

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: A tree-structured dynamic encoder generates an N-bit encoder output word in response to each encoder input word of a sequence of encoder input words, such that the number of encoder output word bits of value 1 equals a value of the encoder input word and such that positions bits of value 1 within the N-bit encoder output word for each give value of encoder word varies with time. Some or all of the switching blocks produce more than two block output words in response to each block input word. The dynamic encoder includes a tree of switching blocks, each dynamically encoding a block input word into more than one block output words, each having fewer bits than the block input word. A sum of values of the output words of each switching block always equals a value of that block's input word.

Abstract: An inkjet head driving circuit driving piezoelectric actuators 21 for ink ejection provided on an inkjet head H includes one D/A converter 62 that converts a digital signal into an analog voltage and outputs the analog voltage, and a waveform generating portion 64 into which an output voltage of the D/A converter 62 is input, and which generates a voltage rising waveform when the output voltage of the D/A converter 62 is larger than a predetermined potential that is midway between a maximum value and a minimum value of that output voltage, and generates a voltage rising waveform when the output voltage of the D/A converter 62 is smaller than the predetermined potential.

Abstract: A multi-level pulse width modulation (multi-level PWM) technique uses multiple voltage levels and/or multiple output channels to obtain improved resolution (also referred to as dynamic range) over ordinary PWM-based digital systems, in particular digital audio systems. A digital audio signal is converted to either (1) an N-level PWM signal which is output to a single channel including a filter and loudspeaker, (2) N components of an N-level PWM signal output to N corresponding channels, (3) some number of multi-level signals output to multiple channels or (4) some number of PWM signals output to multiple channels. The digital audio signal can also be divided into different frequency bands to be processed separately and output to different sets of loudspeakers, wherein fewer low frequency loudspeakers can be used than high frequency loudspeakers to produce equal effective resolution for the output of all frequency bands.

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: A controlled drive circuit for an analog controlled power semiconductor includes a digitally operating logic module, which has a control input receiving control signals from an A/D converter and a control output supplying processed control signals to a D/A module that converts the processed digital control signals signal to an analog or quasi-analog control variable that controls the power semiconductor.

Abstract: An inkjet head driving circuit driving piezoelectric actuators 21 for ink ejection provided on an inkjet head H is provided with an analog switch 71 (72) whose input can be switched between the output voltage of a D/A converter 62 (63) and ground potential, and outputs either that output voltage or ground potential to a waveform generating portion 64. The analog switch 71 (72) is configured such that when a digital signal for generating a voltage rising waveform (voltage falling waveform) with the waveform generating portion 64 is input into the D/A converter 62 (63), the input into the analog switch 71 (72) is switched from ground potential to the output voltage of the D/A converter 62 (63).

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time &Dgr;tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: A controlled drive circuit for an analog controlled power semiconductor includes a digitally operating logic module, which has a control input receiving control signals from an A/D converter and a control output supplying processed control signals to a D/A module that converts the processed digital control signals signal to an analog or quasi-analog control variable that controls the power semiconductor.

Abstract: A decoder for reducing a test time for detecting defective switches in a digital-to-analog converter includes a switch controlling portion for receiving a plurality of digital input signals having information about analog output signals and at least one test order signal for ordering a normal mode or a test mode, outputting the plurality of digital input signals and inverted signals of the plurality of digital input signals when the test order signal orders the normal mode, and outputting as control signals the plurality of digital input signals and second signals having the same phase as the plurality of digital input signals when the test order signal orders the test mode; a plurality of groups of switches each connected in series to a direct current voltage source; and a switch portion for switching the plurality of direct current voltage sources as a function of the plurality of control signals of the switch controlling portion.

Abstract: A waveform generator 30 for generating a desired waveform includes a plurality of rectangular wave generators (40a to 40n) for generating a plurality of rectangular waves and a waveform synthesizing unit 42 for synthesizing the rectangular waves to generate a multi-level synthesized wave, and generate the desired wave based on the synthesized wave.

Abstract: A D/A converter of low distortion factor includes a plurality of voltage dividing resistances formed on a P-type semiconductor substrate and connected in series with each other between power source voltage and ground. One of plural N-channel MOS transistors used as switching elements is selected in correspondence with a decoding result of a decoder, and the selected transistor is connected between an output node and a corresponding tap provided on a current path made up of plural voltage dividing resistances. Since the N-channel MOS transistors are formed directly on the P-type substrate, the voltage dividing resistances are not arranged near an N-type well region. The voltage dividing resistances therefore have uniform resistive value, so that D/A conversion with low distortion factor is realized.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.

Abstract: A D/A converter of a low distortion factor includes a plurality of voltage dividing resistances 53 which are formed on a P-type semiconductor substrate and are connected in series with each other between a power source voltage VDD and the ground GND. An N-channel type MOS transistor 54 as a switching element, which is selected in correspondence with the decoding result of a decoder 51, is connected between a node N1 and each of a plurality of taps provided on a current path made up of plural voltage dividing resistances 53. Since the N-channel type MOS transistor 54 is formed directly on the P-type semiconductor substrate, there is no need for the voltage dividing resistance 53 to be arranged near an N-type well region formed on the P-type substrate. This makes it possible to manufacture the voltage dividing resistance having a uniform resistive value, thus there being realized the D/A conversion of a low distortion factor.

Abstract: The present disclosure discloses an apparatus for generating a shaped waveform derived from a binary input signal. The apparatus receives a binary input signal and a sample clock signal. The sample clock signal changes the state of an up/down counter. The binary input signal controls the counting direction of the counter. The counter addresses a lookup table containing stored values. Also disclosed is the apparatus in which the lookup table output is converted to an analog signal by a digital-to-analog converter. The lookup table can be programmed such that the circuit output is equivalent to a filtered version of the binary input signal. The apparatus may optionally be enabled or disabled, such that the apparatus output assumes a predetermined state when disabled.

Abstract: A skewless differential switching circuit uses skewless switching elements to convert complementary signals with skew into complementary output signals with minimal time skew between the output signals and with equalized rise and fall times of the output signals for minimum harmonic distortion.