Abstract: A first current cell group of an digital-to-analog converter has a first set of current cells which individually turn on and off in response to respectively input digital signals. A second current cell group of the analog-to-digital converter has a second set of current cells which respectively correspond to the first set of current cells and which individually turn on and off in response to respectively input digital signals such that an on/off state of each of the first set of current cells is opposite an on/off state of each corresponding one of the second set of current cells. The first set of currents cells are connected in parallel between a first power supply voltage and a first node, and the second set of currents cells are connected in parallel between the first node and a second power supply voltage.

Abstract: A circuit for implementing a first order noise shaping apparatus for use in data converters employing thermometer-code based elements is disclosed. Raw thermometer code is rotated by up to four columns of shifters such that the code is rotated up to 15 positions. In this manner, the elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements. Such a process may be used in digital to analog converters and analog to digital converters such that a suitable data weighted algorithm can be used.

Abstract: High-speed and high accuracy digital-to-analog (D/A) converters find many applications in signal processing. For wideband telecommunication systems, there is a strong demand on high-performance D/A converters. With the design of the present invention it is enabled to prevent distortions and intermodulations for high-speed and high-accuracy digital-to-analog (D/A) converters for telecommunication applications, where the requirements on distortion and intermodulation can be very stringent. By combining segmentation for MSBs and binary weighting for LSBs a high-performance digital-to-analog conversion architecture can be achieved, where a delay for the binary weighted LSBs is used to equalize a delay introduced by segmentation and where all bit switches (14) are clocked with a tree-like-clock distribution network (11). New floor plans for CMOS, BiCMOS and bipolar implementation are thus invented and circuits for CMOS bit switches and current sources are also disclosed.

Abstract: A D/A converter arranged to improve the resolution by changing the number of resistors to be interposed between a resistance ladder, from which a divided voltage between positive and negative voltage sources is taken out, and the positive and negative voltage sources while maintaining the total resistance value at a constant value, in which the resistance value of the resistor to be interposed between the resistance ladder and the positive and negative voltage sources is selected to uniformly lower the divided voltage which is taken by the resistance ladder by a level corresponding to 1/2 LSB to perform 1/2 LSB correction.

Abstract: In a digital/analog (D/A) converter, a plurality of resistors are connected in series between first and second power supply voltage terminals, and a plurality of switches are arranged in a tree configuration between first nodes of the resistors and an output terminal. The switches are turned ON and OFF in response to input bits. At least one reset switch is connected to a second node of at least one of the switches on a side of said output terminal, thus resetting the second node to a predetermined voltage.

Abstract: A general digital-to-analog (DAC) topology spectrally shapes the DAC conversion noise caused by analog circuit mismatches. In particular, highly practical first-order and second-order noise-shaping DACs are special cases of a general topology. The topology extends the practicality of using noise-shaping DACs in .DELTA..SIGMA. data converters. The first-order DAC is at least as hardware efficient as previously known DACs, but offers the advantage that it is amenable to a simple dithering technique capable of eliminating spurious tones. The second-order DAC is more hardware efficient than previously known DACs, and generally has a large spurious-free dynamic range without any dithering. Moreover, the present invention allows DACs with other types of noise-shaping characteristics (e.g., bandpass noise-shaping characteristics) to be designed based on general DAC topology.

Abstract: A resistance ladder which divides a potential difference between two power sources into 2.sup.m levels by a resistance group in the center portion, then adjusting the number of resistors which are disposed at the both end portions of the resistance ladder and interposed between the resistors of the center portion and the two power sources so that the division voltages of 2.sup.m levels are changed in (n-m) levels, with the result that the potential difference is divided into 2.sup.n levels. A D-A converter uses the resistance ladder. An A-D converter with the D-A converter which generates a reference voltage to be compared with an input voltage.

Abstract: Signal sources are arranged in a matrix form and provide preset analog values. Switching means are connected between signal sources and an analog output terminal having connection paths to the respective signal sources. Latch circuits are respectively provided for switch control circuits for controlling the switching means. Each of the latch circuits latches a control signal from a corresponding one of the switch control circuits and outputs the control signal in response to a preset synchronizing signal to a corresponding one of the switching means. The switching means are simultaneously controlled by output signals of decoders so that a desired analog output is permitted to be derived from the output terminal. The period of the clock signal can be shorten and a switching operation causing variation exceeding a desired variation occurring when the digital signal is changed can be prevented.

Abstract: Digital-to-analog converter having a reference voltage divider and a selection circuit by which the voltage at one of the nodal points of the reference voltage divider can be switched-through to the output of the converter. The selection circuit is controlled by selection signals coming from a decoder circuit by which the digital input signal is decoded. In addition, the converter includes a bias voltage divider which can apply different bias voltages to a level shifting circuit by which the signal level of the selection signals can be shifted.

Abstract: A plurality of resistors are connected between a source terminal to which a reference voltage is applied and a grounded terminal. A plurality of switches, which constitute a first switch group and derives voltages divided by the resistors, are respectively connected to the odd-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. A plurality of switches, which constitute a second switch group and derives voltages divided by the resistors, are respectively connected to the even-numbered connection nodes among the connection nodes between the grounded terminal and a resistor and between each adjacent resistors. Each of the switches of the first and second switch groups is connected to a logical circuit serving as a decoder for selecting one of the switches in accordance with the content of bits other than the least significant bit of an input digital signal.

Abstract: A digital-to-analog converter which comprisesan input terminal (1) for receiving a digital input signal,an output terminal (2) for supplying the analog output signal,a current source circuit (3) having N current sources (I.sub.1 to I.sub.N) for generating N currents of substantially equal current intensity at N outputs (3.1 to 3N), anda combination circuit (4) having N inputs (4.1 to 4N) coupled to the N outputs of the current source circuit and an input (6) for receiving the digital input signal and an output (7).In order to convert a digital signal D which is presented to the input terminal (1) during a time interval (Ta), the time interval is sub-divided into at least two sub-intervals (T.sub.d1, T.sub.d2).

Abstract: In a digital-to-analog conversion circuit, a level detector is used to determine when the digital signal is lower than a predetermined value. When a predetermined time has expired, after the level detection, an inversion detector detects an inversion in polarity of the digital signal. As a result, a control signal is produced to shift the digital signal input to the digital-to-analog (D/A) converter and to attenuate the output analog signal.

Abstract: The invention provides a monolithic Y-bit resistive-ladder type digital-to-analog converter (DAC) having a unity gain inverting operational amplifier as an input buffer to the resistive ladder segment of the DAC. The reference voltage is applied to the input buffer amplifier. Optional bipolar operation is provided by applying a non-inverted reference voltage to the output of the resistive ladder segment of the DAC through a scaled resistance. Analog ground current cancellation is provided by a secondary X-bit R-2R ladder (where X Y) with the non-inverted reference voltage applied to it. The secondary bit ladder is switched in parallel with the top X bits of the main ladder, thereby supplying or sinking roughly the same amount of current as the X most significant bits of the main resistive ladder, but with opposite sense.

Abstract: A digital-to-analog converter includes a decoding network and a plurality of output members such as capacitors. The decoding network receives a plurality of binary signals individually having logic levels respectively coding for binary "1" and binary "0" and individually coding for a binary value of an individually weighted significance and cumulatively coding for an analog value. The network decodes the logic levels of the binary signals and activates output members in accordance with such decoding. As the analog value coded by the logic levels of the binary signals increases, the output members previously activated in the plurality remain activated and other output members in the plurality become activated. The decoding network and the output members are disposed on an integrated circuit chip. Dependent upon their positioning on the chip, the output members have different characteristics which cause errors to be produced in the analog signal, particularly at low analog values.

Abstract: A current source arrangement in which the equality of a number of current sources (1-8) constituted by transistors is improved in that each of these current sources (1-8) is constituted by a number of transistors which are arranged regularly in a matrix on the surface area of an integrated circuit.

Abstract: Sub-sets of switches are provided each having a number of switches directly related to an individual bit in a binary coded input word. Signals representing the individual bits are introduced to the switches in the different sub-sets to obtain switch conductivities in accordance with such binary bits. The switches are connected in a repetitive array to provide paths through the conductive ones of the switches. The switches are connected to output members and a line to introduce the current through the output members to the line in accordance with the pattern of switch conductivities. This provides for progressive increases in the number of the output members connected to the line, ad for a continued connection to the line of output members previously connected to the line, with progressive increases in the binary value. The cumulative current through the line is indicative of the analog value.

Abstract: A converter converts to an analog value a plurality of digital signals each having characteristics representing an individual digital value. A plurality of switches are disposed in sets with the switches in each set being responsive to an individual one of the digital signals. The number of switches in each set is related to the digital significance of the set, preferably on an inverse basis. The switches are connected in a repetitive array to output members and a line to provide for the connection for progressive ones of the members to the output line in accordance with the pattern of the switches in the conductive and non-conductive states in representation of progressive increases in the digital value. The repetitive also provides, with such progressive increases in the digital values, output members previously connected to the line. The repetitive array may be responsive to the digital signals in a single delay time.

Abstract: An apparatus and method for generating or shaping the waveform of electronic signals thereby controlling the high frequency energy content of transitions thereof and in particular for imparting a sine squared shape to synchronizing pulses utilized in television systems is shown.