Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive an oscillator signal from phase-locked loop circuitry. The phase-locked loop circuitry may include a digital or analog phase-locked loop having a first frequency divider, a ring oscillator, and an auxiliary phase noise cancellation loop coupled to the ring oscillator. The auxiliary phase noise cancellation loop may include at least a time-to-digital converter, a second frequency divider, an amplifier, and a bandpass filter configured to reject thermal and quantization noise associated with the time-to-digital converter. The first frequency divider may have a first division ratio, whereas the second frequency divider may have a second division ratio that is less than the first division ratio to provide faster phase noise correction.

Abstract: A method includes providing, by a signal source circuit of a sensing circuit, a signal to a sensor via a conductor. When the sensor is exposed to a condition and is receiving the signal, an electrical characteristic of the sensor affects the signal. The signal includes at least one of: a direct current (DC) component and an oscillating component. When the sensing circuit is in a noisy environment, transient noise couples with the signal to produce a noisy signal. The method further includes comparing, by a transient circuit of the sensing circuit, the noisy signal with a representation of the noisy signal. When the noisy signal compares unfavorably with the representation of the noisy signal, supplying, by the transient circuit, a compensation signal to the conductor. A level of the compensation signal corresponds to a level at which the noisy signal compares unfavorably with the representation of the noisy signal.

Abstract: A successive approximation analog-to-digital with an input for receiving an input analog voltage, and an amplifier with a first set of electrical attributes in a sample phase and a second set of electrical attributes, differing from the first set of electrical attributes, in a conversion phase.

Abstract: Systems and methods related to successive approximation register (SAR) analog-to-digital converters (ADCs) are provided. A method for performing successive approximation registers (SAR) analog-to-digital conversion includes comparing, using a comparator, a first digital-to-analog (DAC) output voltage to a sampled analog input voltage to generate a comparison result including a first positive output and a first negative output; and gating, using gating logic circuitry, at least one of the first positive output or the first negative output of the comparator to next logic circuitry, the gating based at least in part on a digital feedback comprising information associated with at least one of an opposite polarity of the first positive output or an opposite polarity of the first negative output.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

Abstract: A successive approximation analog-to-digital converter includes a digital-to-analog converter DAC configured to receive a digital signal. First conversion units of the DAC are configured to sample an analog signal via a first switch and provide a first level voltage. Each first conversion unit includes a first capacitor array and a first switch array controlled from the digital signal. A single second conversion unit of the DAC is configured to provide a second level voltage. The second conversion unit includes a second capacitor array and a second switch array. A comparator operates to compare each of the first level voltages to the second level voltage and to provide a comparison signal based on each comparison and actuation of a set of third switches. A control circuit closes the first switches simultaneously and closes the third switches successively for the conversion of each sampled analog signal.

Abstract: Disclosed successive approximation register analog-to-digital converters (SAR ADCs) and conversion methods detect a statistical effect of meta-stability induced errors and limit the level of such errors. One illustrative integrated circuit chip includes: a SAR ADC that employs asynchronous bit cycles to convert a sequence of analog signal samples into a sequence of digital signal samples; and a detector that accelerates the asynchronous bit cycles when a meta-stability error bias exceeds a predetermined threshold. An illustrative analog-to-digital conversion method includes: converting a sequence of analog signal samples to a sequence of digital signal samples using a successive approximation register analog to digital converter (SAR ADC) with asynchronous bit cycles; deriving a meta-stability error bias from the sequence of digital signal samples; and accelerating the asynchronous bit cycles when the meta-stability error bias exceeds a predetermined threshold.

Abstract: A method of operating a pipelined analog-to-digital converter (ADC) having a plurality of output stages includes: performing a first calibration process for the pipelined ADC to update a parameter vector of the pipelined ADC, where components of the parameter vector are used for correcting nonlinearity of the pipelined ADC, where performing the first calibration process includes: providing an input signal to the pipelined ADC; converting, by the pipelined ADC, the input signal into a first digital output; providing a scaled version of the input signal to the pipelined ADC, where the scaled version of the input signal is generated by scaling the input signal by a scale factor; converting, by the pipelined ADC, the scaled version of the input signal into a second digital output; and calibrating the pipelined ADC using the first digital output and the second digital output.

Abstract: A charge-steering amplifier circuit and a control method thereof are provided. The charge-steering amplifier circuit is used for amplifying a differential input signal and includes a sample-and-hold circuit, a charge-steering amplifier, a reference voltage generation circuit, and a switch circuit. The sample-and-hold circuit is configured to sample the differential input signal to generate first and second sampled signals. The charge-steering amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first and second input terminals receive the first and second sampled signals, respectively. The reference voltage generation circuit is configured to generate a reference voltage according to the differential input signal. The switch circuit is configured to couple the reference voltage to the first output terminal and the second output terminal.

Abstract: A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

Abstract: An analog-to-digital converter (ADC) and an operation method thereof are provided. The ADC includes: a comparator which compares a signal input through a first input terminal and a signal input through a second input terminal, and outputs an output value according to the comparison result. A successive approximation register receives the output value of the comparator, sets digital signal values from a most significant bit to a least significant bit, and outputs the digital signal values. A digital-to-analog converter receives the digital signal values, and converts it into an analog signal based on a reference voltage Vref, and outputs it to the second input terminal. A noise component is added to the input signal and to the analog signal Vdac?.

Abstract: A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

Abstract: An analog-to-digital converter according to one or more embodiments is disclosed that converts an analog input to a digital converted value by repeating a conversion data generation operation by a conversion data generator, a potential generation operation by a capacitance DAC, and a comparison operation by a comparator for a resolution bit, the analog-to-digital converter. a comparator operation signal generation circuit predicts the time when a potential generated by the capacitance DAC becomes settled based on a charging or discharging time to a capacitance element whose characteristics are equal to those of the capacitance used in the capacitance DAC, and generates a comparator operation signal to allow the comparator to start the comparison operation.

Abstract: The exemplified disclosure presents a successive approximation register analog-to-digital converter circuit that comprises a two-step (e.g., two-stage) analog-to-digital converter (ADC) that operates a 1st-stage successive approximation register (SAR) in the continuous time (CT) domain (also referred to as a “1-st stage CTSAR”) that then feeds a sampling operation location in the second stage. Without a front-end sampling circuit in the 1st-stage, the exemplary successive approximation analog-to-digital converter circuit can avoid high sampling noise associated with such sampling operation and thus can be configured with a substantially smaller input capacitor size (e.g., at least 20 times smaller) as compared to conventional Nyquist ADC with a front-end sample-and-hold circuit.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

Abstract: The present disclosure belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed SAR_ADC digital logic circuit, in particular to a high-speed digital logic circuit for SAR_ADC and a sampling adjustment method. The digital logic circuit includes a comparator, a logic control unit parallel to the comparator, and a capacitor array DAC. The comparator and the logic control unit are simultaneously triggered by a clock signal. The comparator outputs a valid comparison result Dp/Dn, the logic control unit outputs a corresponding rising edge signal, the rising edge signal is slightly later than Dp/Dn output by the comparator through setting a delay match, Dp/Dn is captured by the corresponding rising edge signal, thereby settling a capacitor array. The present disclosure eliminates the disadvantage of the improper settling of the capacitor array of the traditional parallel digital logic.

Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a se

Abstract: A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

Abstract: An analog-to-digital converter (ADC) system includes a main ADC, a reference ADC, a sampling control circuit, and a calibration circuit. The main ADC obtains a first sampled input voltage by sampling an analog input according to a first sampling clock, and performs analog-to-digital conversion upon the first sampled voltage to generate a first sample value. The reference ADC obtains a second sampled voltage by sampling the analog input according to a second sampling clock, and performs analog-to-digital conversion upon the second sampled voltage to generate a second sample value. The sampling control circuit controls the second sampling clock to ensure that the second sampling clock and the first sampling clock have a same frequency but different phases, and adjusts the second sample value to generate a reference sample value. The calibration circuit applies calibration to the main ADC according to the first sample value and the reference sample value.

Abstract: An analog-to-digital converter (1) includes an S/H circuit (10) configured to sample and hold an analog input signal (IN) in synchronization with a sampling clock signal (CLK), a delay circuit (20) configured to delay the sampling clock signal (CLK), an ADC circuit (30) configured to sample an output signal (S/H_out) of the S/H circuit (10) in synchronization with the sampling clock signal (CLK_delay) that is delayed, and output a digital signal (OUT) corresponding to an amplitude of the output signal that is sampled, and a delay adjustment circuit (40) configured to adjust a delay time of the sampling clock signal (CLK) in the delay circuit (20) in accordance with a change in frequency of the sampling clock signal (CLK).

Abstract: A pipelined analog-to-digital converter and an output calibration method for the same. The pipelined analog-to-digital converter introduces an error calibration mechanism on the basis of traditional pipelined analog-to-digital converters through a control module, an equivalent gain error extraction module, an error storage module and a coding reconstruction module to compensate for gain errors and setup errors caused by operational amplifiers in a pipelined conversion module, so that the analog-to-digital conversion accuracy is improved, and requirements for the gain and bandwidth of the operational amplifier are relaxed, which can effectively reduce the power consumption of the analog-to-digital converter and the complexity of the corresponding analog circuit; a curve fitting method is adopted to obtain an ideal output sequence and then calculate errors; meanwhile, extraction and calibration of equivalent gain errors are all done in digital ways, and therefore accuracy thereof is high.

Abstract: The present disclosure discloses a sample and hold amplifier circuit that includes a positive and a negative terminal capacitor arrays, a positive and a negative terminal switch arrays and a differential output circuit. A second terminal of each of bit capacitors in the positive and the negative terminal capacitor arrays are respectively coupled to a positive and a negative output terminal. In a sampling time period, according to a first connection relation, each of the connected bit capacitors is controlled to receive a polarity input voltage to perform a gain modification. In a holding time period, according to a second connection relation, each of the connected bit capacitors is controlled to receive an offset modification voltage to perform an offset modification. A positive and a negative output voltages are generated at the positive and the negative output terminal to be outputted as a pair of differential output signals by the differential output circuit.

Abstract: An apparatus is disclosed for analog-to-digital conversion. In an example aspect, the apparatus includes an analog-to-digital converter (ADC). The ADC includes a reference-crossing detector having an input and an output. The ADC also includes a ramp generator coupled between the output of the reference-crossing detector and the input of the reference-crossing detector. The ADC further includes a voltage shifter coupled between the output of the reference-crossing detector and the input of the reference-crossing detector.

Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.

Abstract: An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

Abstract: Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

Abstract: A control circuit of a pipeline analog-to-digital converter (ADC) is provided. The pipeline ADC includes a multiplying digital-to-analog converter (MDAC) which includes a capacitor. The control circuit includes six switches and two buffer circuits. The first and second switches are respectively coupled between one end of the capacitor and the first and second reference voltages. The output terminals of the first and second buffer circuits are respectively coupled to the first and second switches. The input terminal of the first buffer circuit is coupled to the third reference voltage through the third switch, or receives a control signal through the fifth switch. The input terminal of the second buffer circuit is coupled to the fourth reference voltage through the fourth switch, or receives the control signal through the sixth switch. The first and second reference voltages are different, and the first and second switches are not turned on simultaneously.

Abstract: A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

Abstract: A data converter circuit comprises timing circuitry configured to time stages of a conversion performed by the data converter circuit; a level shifter circuit configured to receive a control signal associated with the conversion and provide a level shifted version of the control signal to one or more switch circuits of the data converter circuit; and a time delay circuit element including a replica circuit of the level shifter circuit that adds a circuit delay to a transition of the control signal at the timing circuitry.

Abstract: A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

Abstract: An analog-to-digital converter (ADC) is described. This ADC includes a conversion circuit with multiple bit-conversion circuits. During operation, the ADC may receive an input signal. Then, the conversion circuit may asynchronously perform successive-approximation-register (SAR) analog-to-digital conversion of the input signal using the bit-conversion circuits, where the bit-conversion circuits to provide a quantized representation of the input signal. For example, the bit-conversion circuits may asynchronously and sequentially perform the SAR analog-to-digital conversion to determine different bits in the quantized representation of the input signal. Moreover, the ADC may selectively perform self-calibration of a global delay of the bit-conversions circuits. Note that the timing self-calibration may be iterative and subject to a constraint that a maximum conversion time is less than a target conversion time.

Abstract: A control circuit for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The switched-capacitor DAC includes a target capacitor. A first terminal of the target capacitor is coupled to an input terminal of the comparator. A second terminal of the target capacitor is coupled to a first reference voltage through a first switch and coupled to a second reference voltage through a second switch. The control circuit includes a third switch and a buffer circuit. The third switch is coupled between the first reference voltage and the second terminal of the target capacitor. The buffer circuit is coupled to the first switch and the third switch for controlling the first switch and the third switch based on a control signal.

Abstract: VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

Abstract: A data bus includes process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages including a buffer element configured to buffer a data bit sequence and to forward the buffered data bit sequence from a first of the buffer elements to a last of the buffer elements. The linear main pipeline includes N pipeline stage elements arranged in series. Each pipeline stage element is connected to the last buffer element of a respective linear pipeline and configured to read-out one or more of the buffered data bit sequences and to forward the read-out data bit sequences from one of N pipeline stag elements to a next of the N pipeline stage elements.

Abstract: The present invention provides a comparator circuit applicable to a high-speed pipeline ADC. The comparator circuit includes a switch capacitor circuit, a pre-amplification circuit, and a latch circuit. The pre-amplification circuit includes a pre-amplifier, a resistance-adjustable device, two switches. The latch circuit includes a differential static latch, a first capacitor, a second capacitor, and a third switch. The transmission rates of a sampling phase and a setup phase can be increased.

Abstract: A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.

Abstract: A multi-stage switched capacitor circuit and an operation method thereof are provided. The multi-stage switched capacitor circuit includes a first operational stage, a second operational stage and a third operational stage that are serially connected in order. Each operational stage operates in a sample phase or a hold phase and generates a detection signal indicating an end of the hold phase. The operation method of the multi-stage switched capacitor circuit includes: controlling the second operational stage to operate in the hold phase when the detection signal of the first operational stage indicates the end of the hold phase of the first operational stage, and the detection signal of the third operational stage indicates the end of the hold phase of the third operational stage.

Abstract: A sense amplifier and a method for accessing a memory device are disclosed. In an embodiment a sense amplifier for a memory device includes a first input node selectively coupled to a first memory cell through a first local bitline and a first main bitline, a second input node selectively coupled through a second local bitline and a second main bitline to a second memory cell or to a reference generator configured to generate a reference current, a first current generator controllable so as to inject a first variable current into the first input node, a second current generator controllable so as to inject a second variable current into the second input node, a first branch coupled to the first input node and comprising a first switch circuit, a first sense transistor and a first forcing transistor and a second branch coupled to the second input node and including a second switch circuit, a second sense transistor and a second forcing transistor.

Abstract: An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits.

Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.

Abstract: A sensor arrangement includes a sensor having a first terminal and a second terminal, and an amplifier having an amplifier input for applying an input signal and an amplifier output for providing an amplified input signal, the amplifier input being coupled to the second terminal. A quantizer having a quantizer input and a quantizer output is configured to provide a multi-level output signal on the basis of the amplified input signal and a feedback circuit having a feedback circuit input coupled to the quantizer output and a feedback circuit output coupled to the first terminal. The feedback circuit includes a digital-to-analog converter configured to generate an analog signal on the basis of the multi-level output signal, the analog signal being the basis of a feedback signal provided at the feedback circuit output, a feedback capacitor coupled between the feedback circuit output and an output of the digital-to-analog converter, and a voltage source coupled to the feedback circuit output.

Abstract: A sensing circuit includes a signal source circuit and a transient circuit. The signal source circuit provides a signal to the sensor via a conductor. When the sensor is exposed to a condition and is receiving the signal, an electrical characteristic of the sensor affects the signal, which is interpreted by the signal source circuit. When the sensing circuit is in a noisy environment, transient noise couples with the signal to produce a noisy signal. The transient circuit compares the noisy signal with a representation of the noisy signal. When the noisy signal compares unfavorably with the representation of the noisy signal, the transient circuit supplies a compensation signal to the conductor. The level of the compensation signal corresponds to a level at which the noisy signal compares unfavorably with the representation of the noisy signal.

Abstract: A clock-less delay comparator coupled to a first input signal and a second input signal, the clock-less delay comparator comprising: a first transistor having a control terminal coupled to the second input signal, a first current terminal coupled to a first voltage supply, and a second current terminal; a second transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a third transistor having a control terminal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fourth transistor having a control terminal coupled to the first input signal, a first current terminal coupled to the first voltage supply, and a second current terminal; a fifth transistor having a control terminal coupled to the second input signal, a first current terminal, and a second current terminal coupled to the control terminal of the third transistor; a sixth transistor having a control terminal coupled to the first input

Abstract: An analog-to-digital converter (ADC) circuit includes a signal input terminal, a sample-and-hold circuit, and a successive approximation register (SAR) ADC. The sample-and-hold circuit includes an input terminal coupled to the signal input terminal. The SAR ADC includes a comparator, a first capacitive digital-to-analog converter (CDAC), and a second CDAC. The first CDAC includes a first input terminal coupled to the signal input terminal, a second input terminal coupled to an output terminal of the sample-and-hold circuit, and an output terminal coupled to a first input terminal of the comparator. The second CDAC includes a first input terminal coupled to the signal input terminal, an output terminal coupled to a second input terminal of the comparator.

Abstract: Techniques are disclosed to compensate for changes in the impedance of stage(s) preceding a trans-impedance amplifier (TIA) that is used within an RF chain. The techniques identify the changes in the source impedance value of the input stage (e.g., the mixers and LNAs) as a result of a gain state change, which alters the signal-to-transfer function (STF) of the TIA during operation and negatively impacts radio performance. The STF is maintained for changes in the source impedance value throughout different gain states without using switchable shunt components by using tunable elements to compensate for the source impedance changes, thus keeping the STF constant.

Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator coupled to the CDAC, and a successive approximation register (SAR) control circuit coupled to the CDAC and the comparator. The SAR control circuit is configured to successively select bits of a digital output value. The SAR control circuit is also configured to, after selection of the bits of the digital output value: maintain a state of first switches of the CDAC applied to select a most significant bit of the digital output value, and revert second switches of the CDAC applied to select bits of the digital output value having significance lower than the most significant bit to a state of the second switches prior to selection of the most significant bit.

Abstract: Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e.

Abstract: A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises two sampling switches which are coupled to a 2-column successive approximation register (SAR) analog-to-digital converter (ADC). The 2-column SAR ADC comprises a differential comparator, a local SAR control, and two digital-to-analog converters (DACs). The two sampling switches are coupled between two readout columns and two inputs of the differential comparator, respectively. An image readout method reads two pixels with three conversions through the RC. The RC is operated by the local SAR control to set the two DACs based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.