Analog Input Compared With Static Reference Patents (Class 341/158)
  • Patent number: 10353451
    Abstract: In a system using a device not adapted to a single wire bus, a semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Ishikawa, Yoshiaki Daimon, Norihiko Ishizaki, Yuichi Iwaya
  • Patent number: 10348992
    Abstract: The present disclosure relates to a comparator, an AD converter, a solid-state imaging device, an electronic apparatus, and a comparator control method that can reduce power consumption while increasing the determination speed of the comparator. The comparator includes a comparison unit, a positive feedback circuit, and a current limiting unit. The comparison unit compares the voltage of an input signal and the voltage of a reference signal, and outputs a comparison result signal. The positive feedback circuit increases the transition speed at the time when the comparison result signal is inverted. The current limiting unit limits the current flowing in the comparison unit after the inversion of the comparison result signal. The present disclosure can be applied to comparators, for example.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 9, 2019
    Assignee: Sony Corporation
    Inventors: Masaki Sakakibara, Kenichi Aoyagi, Seiji Yamada
  • Patent number: 10327659
    Abstract: An analog front end (AFE) system for substantially eliminating quantization error or noise can combine an input of an integrator circuit in the AFE system with an input of the digital-to-analog converter (DAC) circuit in the feedback loop of the AFE system. By combining the input of the integrator with the input of the DAC circuit in the feedback loop, the in-band quantization noise of the filter can be substantially eliminated, thereby improving measurement accuracy.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 25, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Arthur J. Kalb, Yogesh Jayaraman Sharma, Marvin Liu Shu
  • Patent number: 10277236
    Abstract: An ultrasound device including an asynchronous successive approximation analog-to-digital converter and method are provided. The device includes at least one ultrasonic transducer, a plurality of asynchronous successive-approximation-register (SAR) analog-to-digital converters (ADC) coupled to the at least one ultrasonic transducer, at least one asynchronous SAR in the plurality having a sample and hold stage, a digital-to-analog converter (DAC), a comparator, and control circuitry, wherein a DAC update event following at least one bit conversion is synchronized to a corresponding DAC update event of at least one other ADC in the plurality of ADCs.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: April 30, 2019
    Assignee: Butterfly Network, Inc.
    Inventors: Kailiang Chen, Tyler S. Ralston
  • Patent number: 10090848
    Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.
    Type: Grant
    Filed: January 14, 2018
    Date of Patent: October 2, 2018
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Hassan Elwan, Mohamed Aboudina, Janakan Sivasubramaniam
  • Patent number: 10003454
    Abstract: Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 19, 2018
    Assignee: KANDOU LABS, S.A.
    Inventor: Armin Tajalli
  • Patent number: 9977073
    Abstract: An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: May 22, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOY, INC.
    Inventor: Pak-Kim Lau
  • Patent number: 9960632
    Abstract: Disclosed are a method and apparatus for controlling a booster circuit such that maximum power is extracted from a power supply while power consumption for monitoring power generated by the power supply is reduced, and an apparatus for extracting maximum power by using the method and apparatus for controlling a booster circuit.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 1, 2018
    Assignees: Samsung Electronics Co., Ltd, Korea Advanced Institute of Science and Technology
    Inventors: Je-in Yu, Gyu-hyeong Cho, Kyu-sub Kwak, Hui-dong Gwon, June-hyeon Ahn, Young-sub Yuk
  • Patent number: 9664752
    Abstract: A magnetic field sensor includes first, second, and third magnetic field sensing elements having respective first, second and third maximum response axes, the first second and third maximum response axes pointing along respective first, second, and third different coordinate axes. In response to a magnetic field, the first, second, and third magnetic field sensing elements are operable to generate first second, and third magnetic field signals. Signals representative of the first, second, and third magnetic field signals are compared with thresholds to determine if the magnetic field is greater than the thresholds. A corresponding method is also provided.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: May 30, 2017
    Assignee: Allegro Microsystems, LLC
    Inventors: Gerardo A. Monreal, Bruno Luis Uberti
  • Patent number: 9577662
    Abstract: A CT-SDADC of the present disclosure converts the analog input signal from a representation in an analog signal domain to a representation in a digital signal domain to provide the digital output signal. The CT-SDADC achieves the analog-to-digital conversion and ELDC by switching between two phases in the SAR sub-ADC: a sampling phase and a conversion phase. During the sampling phase, the SAR sub-ADC captures the analog input signal across multiple arrays of switchable capacitors. The conversion phase comprises a number of steps, and one or more bits of the digital output signal are resolved at each step of the conversion phase. A portion of the SC-DAC is driven by the delayed CT-SDADC output during the conversion phase to effectively compensate for excess loop delay caused by the CT-SDADC feedback loop.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 21, 2017
    Assignee: Broadcom Corporation
    Inventors: Guowen Wei, Xinyu Yu, Michael Inerfield, Tom Kwan
  • Patent number: 9461664
    Abstract: Imagers may include analog-to-digital converter circuitry that produces a digital output code from an analog input voltage. The analog-to-digital converter circuitry may include a series of capacitors including a first set of binary-mapped capacitors. The analog-to-digital converter circuitry may include a second set of one or more capacitors that have capacitances that are less than binary-mapped capacitance values. The digital output code may include bits having respective bit positions within the digital output code. During successive-approximation operations performed by the analog-to-digital converter circuitry, each bit of the digital output code may be produced using a corresponding capacitor. Digital processing circuitry such as an image processor may produce a digital value from the digital output code by multiplying the bits of the digital output code with respective weights determined based on the capacitance of the corresponding capacitors.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 4, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Parthasarathy Sampath
  • Patent number: 9395780
    Abstract: A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA includes a USB accessory port. The ACA bridge circuit includes detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: July 19, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Peter Brendan Considine, Sylvain Berthout, Arnaud Deconinck
  • Patent number: 9313436
    Abstract: An analog-digital converter includes: a first comparator configured to make a comparison between a pixel voltage and a first reference voltage, the pixel voltage being a signal voltage outputted from a pixel including an photoelectric conversion element, the pixel voltage corresponding to electric charge generated by the photoelectric conversion element; a second comparator configured to make a comparison between the pixel voltage and a second reference voltage; and a voltage follower configured to connect an input terminal for the first reference voltage of the first comparator and an input terminal for the second reference voltage of the second comparator through a switch.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: April 12, 2016
    Assignee: SONY CORPORATION
    Inventor: Keiji Ookuma
  • Patent number: 9214950
    Abstract: A flash analog to digital converter (ADC) provides a temperature compensated trim current by applying a first temperature compensated reference current across a replica resistor ladder. The reference current is mirrored to a trim digital to analog converter, which outputs a fractional portion of the temperature compensated reference current. The proportional trim current is then fed back to the reference current to provide a trimmed temperature compensated reference current. The trimmed reference current is mirrored across the output resistor ladder providing a trimmed current in which the trim varies along with temperature changes due to the trim current being a proportion of the temperature compensated reference current. A proportional trim current which varies with temperature changes is applied to the gain current trim and mismatch current trim in a DAC of a quantizing stage of a sub-ranging ADC.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: December 15, 2015
    Assignee: Lockheed Martin Corporation
    Inventors: Brandon R. Davis, Toshi Omori, Lloyd F. Linder, Victoria T. Pereira
  • Patent number: 9166609
    Abstract: It is intended to provide an AD converter capable of increasing its conversion accuracy. An AD converter is equipped with a clock generator which generates a first clock using a second clock and a comparator which includes a comparison circuit for comparing an input signal with a prescribed value in a first period of the first clock and a precharging circuit for precharging, in a second period of the first clock, an internal voltage to a prescribed value for the next comparison operation. The clock generator includes a replica circuit of the precharging circuit of the comparator. In the replica circuit of the precharging circuit, a precharging period from the start to the end of precharging is set as the second period of the first clock.
    Type: Grant
    Filed: September 2, 2013
    Date of Patent: October 20, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Masao Takayama, Junichi Naka, Naoya Yosoku
  • Patent number: 9165166
    Abstract: An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: October 20, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takayuki Hamada, Sanroku Tsukamoto
  • Patent number: 9124288
    Abstract: To determine the accuracy of an AD converter more simply than in the related art, a semiconductor device includes a successive approximation AD converter. The AD converter includes one or a plurality of testing capacitors used in a test mode, separately from a C-DAC used for AD conversion in a normal mode. In the test mode, the accuracy of a capacitor under test among a plurality of capacitors configuring the C-DAC is determined by comparing a potential occurring in the capacitor under test and a potential occurring in the testing capacitors.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 1, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takahiro Umezaki, Yasutaka Horikoshi, Takehiro Mikami
  • Patent number: 9124292
    Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: September 1, 2015
    Assignee: Analog Devices Global
    Inventors: Zhao Li, Shipra Bhal, Kevin Glenn Gard, David Nelson Alldred, Christopher Mayer, Trevor Clifford Caldwell, David J. McLaurin, Victor Kozlov
  • Patent number: 9106248
    Abstract: The present invention relates to an analog to digital converter. The analog to digital converter includes comparing modules at multi levels, where a comparing module at each level includes a comparator and a metastable state determining unit. The comparator is configured to, when a previous-level comparing module is not in a metastable state, receive a first clock, a first input signal, and a second input signal, and compare the first input signal with the second input signal. The metastable state determining unit is configured to, when the previous-level comparing module is not in a metastable state, receive the first clock, generate a reference clock according to the first clock, and if a second clock that is output by the comparator is later than the reference clock, determine that the current-level comparing module is in a metastable state.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: August 11, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingjun Fan, Liming Fang, Yuan Liu
  • Patent number: 9094030
    Abstract: An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: July 28, 2015
    Assignee: SAMSUNG ELECTRONICS CORPORATION
    Inventors: Jung-Ho Lee, Sung-Sang Lim, Yong-Woo Kim, Michael Choi
  • Patent number: 9035814
    Abstract: A feedforward delta-sigma modulator includes a successive approximation analog-to-digital converter, a digital-to-analog converter, N integrators, a first adder, a second adder, and an optimization zero generation unit, where N is a positive integer. An output terminal of each integrator of the N integrators is coupled to the successive approximation analog-to-digital converter. The digital-to-analog converter is coupled between the first adder and the successive approximation analog-to-digital converter. The first adder is coupled to an input terminal of a first integrator of the N integrator. The second adder is coupled to an input terminal of a Kth integrator of the N integrators, where K is a positive integer. The optimization zero generation unit is coupled between an output terminal of a (K+1)th integrator of the N integrators and the second adder.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 19, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Che-Wei Chang
  • Patent number: 9035810
    Abstract: A system and method are provided for measuring current sources, such as might be useful in the calibration of a digital-to-analog converter (DAC). The method provides a first plurality of current sources. Each current source is engageable to supply a current representing a corresponding nominal value. The method selectively enables current source combinations of current. In response to measuring the current source combinations, current difference values are found, and the current source nominal values are adjusted using the current difference values. In one aspect, a reference current source is provided having a reference first value, and the current source nominal values are adjusted with respect to the reference first value. The current sources may have corresponding nominal digital values adjusted using measured digital difference values.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: May 19, 2015
    Assignee: IQ—Analog Corporation
    Inventors: Mikko Waltari, Costantino Pala
  • Patent number: 9024797
    Abstract: In an integrating A/D converter, first and second reference voltage inputs (18, 20) alternatingly connect through a reference voltage switch (16, 16?) via a first reference resistor (Rref) to an inverting input (122) of an integrator (12). A comparator (22) connected downstream of the integrator (12) compares a test voltage applied to its test voltage input (221) with a comparator reference voltage applied to its reference voltage input (222). This input (221) is connected to- the output (126) of the integrator (12). A control device (40) actuates the first reference voltage switch (16, 16?) in a pulsed manner and measures the time intervals between the individual switching processes. An inverter (24) inverting a measuring voltage (UM) and a first heating resistor (RMH) coupled thermally with a measuring resistor (RM), are connected in series between the measuring voltage input (14) and the output of the first reference voltage switch (16, 16?).
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: May 5, 2015
    Assignee: Sartorius Lab Instruments GmbH & Co. KG
    Inventors: Heinrich Feldotte, Heyko Holst
  • Publication number: 20150120026
    Abstract: A system includes an analog-to-digital converter receiving a plurality of input signals. One particular input signal has a particular analog value and the analog-to-digital converter uses a fixed reference to convert the particular analog value to a particular digital value. The analog-to-digital converter uses the particular analog value as a reference for converting the analog values of the remaining input signals.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: Texas Instruments Incorporated
    Inventor: Zhenyong Zhang
  • Publication number: 20150109160
    Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.
    Type: Application
    Filed: April 29, 2014
    Publication date: April 23, 2015
    Applicant: NOVATEK Microelectronics Corp.
    Inventor: Jer-Hao Hsu
  • Patent number: 9007252
    Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 14, 2015
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Jer-Hao Hsu
  • Patent number: 8994570
    Abstract: An analog-to-digital converter employs one or more reference ladders for generating reference voltages with which to compare the analog signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 31, 2015
    Assignee: Cambridge Silicon Radio Limited
    Inventor: Hashem Zare-Hoseini
  • Patent number: 8988267
    Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Hideyuki Funaki, Go Kawata, Tetsuro Itakura, Masanori Furuta
  • Patent number: 8988260
    Abstract: A continuous-time delta-sigma digital-to-analog converter (DAC) includes a first delta-sigma modulator configured to quantize a most significant bit or bits of a digital input signal and produce a first quantization error signal, and a second multi-stage delta-sigma modulator configured to quantize less significant bits of the digital input signal. A first DAC is coupled to an output of the first delta-sigma modulator, and a second DAC is coupled to an output of the second noise-shaping filter. The second DAC has a greater resolution than the first DAC. A low pass output filter is coupled to a sum of an output of the first DAC and an output of the second DAC.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 8981986
    Abstract: Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Broadcom Corporation
    Inventors: Pauli Mikael Seppinen, Markus Nentwig, Sami Seppo Antero Kallioinen, Kim Kaltiokallio
  • Patent number: 8976051
    Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ljudmil Anastasov, Jens Barrenscheen
  • Patent number: 8970419
    Abstract: An analog-to-digital converter (“ADC”). The ADC includes a bank of comparators and a window controller. The window controller is coupled to the bank of comparators to selectively activate first comparators of the bank of comparators associated with a window size and to selectively inactivate second comparators of the bank of comparators.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 3, 2015
    Assignee: Xilinx, Inc.
    Inventors: Brendan Farley, James Hudner, Ivan Bogue, Declan Carey, Darragh Walsh, Marc Erett
  • Patent number: 8970412
    Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: March 3, 2015
    Assignee: Invensense, Inc.
    Inventors: Derek K. Shaeffer, Xiang Fang
  • Publication number: 20150048958
    Abstract: In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Inventors: Heimo Hartlieb, Clemens Kain, Michael Hausmann
  • Patent number: 8952836
    Abstract: A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: February 10, 2015
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Hongwei Zhu, Yuwei Zhao
  • Patent number: 8928511
    Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: January 6, 2015
    Assignee: Mediatek Inc.
    Inventors: Yu-Hsin Lin, Hung-Chieh Tsai, Sheng-Jui Huang
  • Publication number: 20150002327
    Abstract: In an integrating A/D converter, first and second reference voltage inputs (18, 20) alternatingly connect through a reference voltage switch (16, 16?) via a first reference resistor (Rref) to an inverting input (122) of an integrator (12). A comparator (22) connected downstream of the integrator (12) compares a test voltage applied to its test voltage input (221) with a comparator reference voltage applied to its reference voltage input (222). This input (221) is connected to the output (126) of the integrator (12). A control device (40) actuates the first reference voltage switch (16, 16?) in a pulsed manner and measures the time intervals between the individual switching processes. An inverter (24) inverting a measuring voltage (UM) and a first heating resistor (RMH) coupled thermally with a measuring resistor (RM), are connected in series between the measuring voltage input (14) and the output of the first reference voltage switch (16, 16?).
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Inventors: Heinrich Feldotte, Heyko Holst
  • Patent number: 8922408
    Abstract: A semiconductor device using analog-to digital (AD) conversion realizes reliable control so that, at the time of AD converting reference voltage, a low-voltage transistor in a reference voltage generating circuit is not destroyed by voltage held in a sample and hold circuit. In a semiconductor device, when an instruction of detecting a reference voltage value is received, a switch control unit controlling switching of an input signal of an internal AD converter temporarily automatically couples an input node of a sample and hold circuit and a ground node and, after that, couples the input node of the sample and hold circuit and an output node of a reference voltage generating circuit.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Takaya Masuda
  • Patent number: 8902094
    Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Broadcom Corporation
    Inventors: Heng Zhang, Delong Cui, Jun Cao
  • Publication number: 20140347198
    Abstract: The present invention relates to an analog-to-digital converting circuit with temperature sensing and the electronic device thereof. The present invention uses a first impedance device to receive a reference voltage and produces an input current according to a temperature. An analog-to-digital converting unit is coupled to the first impedance device and produces a digital output signal according to the input current. Thereby, according to the present invention, by integrating the first impedance device into the analog-to-digital converting circuit, the circuit area and the power consumption can be lowered, which further reduces the cost and improves the accuracy of temperature sensing.
    Type: Application
    Filed: June 17, 2013
    Publication date: November 27, 2014
    Inventors: CHAN-HSIANG WENG, CHUN-KUAN WU, TSUNG-HSIEN LIN
  • Patent number: 8896757
    Abstract: There is provided a delta-sigma A/D converter including a first integrator, a second integrator located on an output side of the first integrator, a quantizer located on an output side of the second integrator, and a first current D/A converter receiving an output of the quantizer and providing a negative feedback signal to an input side of the quantizer.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventor: Tomohiro Matsumoto
  • Patent number: 8890729
    Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.
    Type: Grant
    Filed: January 26, 2013
    Date of Patent: November 18, 2014
    Assignee: Crest Semiconductors, Inc.
    Inventors: Donald E. Lewis, Ryan James Kier, Rex K. Hales, Yusuf A. Haque
  • Patent number: 8890740
    Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: November 18, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Masanori Hoshino, Takumi Danjo
  • Patent number: 8884802
    Abstract: A calibration system for an analog-to-digital converter (ADC) an internal ADC that receives an analog input and converts the analog input to digital multi-bit data. The calibration system also includes a reference shuffling circuit that shuffles reference values of comparators of the internal ADC. Further, the calibration system includes a calibration circuit that calibrates the comparators of the internal ADC. The calibration system includes a digital block that measures an amplitude based on the digital multi-bit data. Additionally, the calibration system includes calibration logic that controls the calibration circuit based on an output of the digital block.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: November 11, 2014
    Assignee: Analog Devices Technology
    Inventors: Zhao Li, Shipra Bhal, Kevin Glenn Gard, David Alldred, Christopher Mayer, Trevor Clifford Caldwell, David J. McLaurin, Victor Kozlov
  • Publication number: 20140327562
    Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Inventor: Dusan STEPANOVIC
  • Patent number: 8878713
    Abstract: A system includes an array of comparators configured to convert an analog input to a digital output, a switch configured to adjust output bits of the digital output, and a control logic; the control logic is configured to initialize the switch and a direct-current source coupled to the analog input; the control logic is configured to increase the direct-current source in incremental steps of a minimal voltage value corresponding to the least significant bit of the digital output; and the control input is also configured to cause the switch to adjust one or more output bits of the digital output based at least in part on a value of the output bit corresponding to the current incremental step.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 4, 2014
    Assignee: Fujitsu Limited
    Inventors: Pradip Thachile, Magnus O. Wiklund, William Warren Walker
  • Patent number: 8872691
    Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Keysight Technologies, Inc.
    Inventor: Dusan Stepanovic
  • Patent number: 8860599
    Abstract: A method utilized in an analog-to-digital conversion apparatus, for converting an analog input signal into a digital output signal including a first portion and a second portion, includes: using a comparator circuit to compare the analog input signal with at least one first reference level to generate a preliminary comparison result, the at least one first reference level being used for determining the first portion; estimating the first portion according to the preliminary comparison result; based on the preliminary comparison result, performing the successive approximation procedure to obtain a posterior comparison result according to a plurality of second reference levels, the second reference levels being used for determining the second portion; and, estimating the second portion according to the posterior comparison result. The preliminary and posterior comparison results are generated by the comparator circuit.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Mediatek Inc.
    Inventor: Yuan-Ching Lien
  • Publication number: 20140300499
    Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 9, 2014
    Applicant: MaxLinear, Inc.
    Inventors: Raja Pullela, Curtis Ling
  • Publication number: 20140266847
    Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.
    Type: Application
    Filed: September 17, 2013
    Publication date: September 18, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Junhua SHEN, Ronald A. KAPUSTA, Edward C. GUTHRIE