Serial Conversions With Change In Signal Patents (Class 341/162)
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Patent number: 11955986Abstract: A comparator circuit, including an input circuit, first and second inverting amplification circuits, first and second coupling circuits, and a feedback circuit, wherein the input circuit generates an amplified input signal based on positive and negative input voltages, the first inverting amplification circuit generates an intermediate amplified signal based on the amplified input signal during a sampling period, the second inverting amplification circuit generates a comparison result signal based on the intermediate amplified signal during the sampling period, the first coupling circuit is connected between the input circuit and the first inverting amplification circuit, the second coupling circuit is connected between the first inverting amplification circuit and the second inverting amplification circuit, and the feedback circuit amplifies the input node of the first inverting amplification circuit with a rail-to-rail voltage corresponding to a power supply voltage or a ground voltage based on the comparisType: GrantFiled: January 13, 2023Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyochang Kim
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Patent number: 11646746Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.Type: GrantFiled: May 31, 2022Date of Patent: May 9, 2023Assignee: SIGMASENSE, LLC.Inventor: Phuong Huynh
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Patent number: 11646745Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100 s of kHz (e.g., 200-300 kHz), or even higher.Type: GrantFiled: March 30, 2022Date of Patent: May 9, 2023Assignee: SIGMASENSE, LLC.Inventor: Phuong Huynh
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Patent number: 11635314Abstract: In accordance with an embodiment, a method for monitoring a data converter configured to convert data using a calibration determined by a calibration data record includes calibrating the data converter in order to determine a corresponding multiplicity of time associated calibration data records at a multiplicity of different times; and determining a state of the data converter based on comparing at least one of the multiplicity of time associated calibration data records with a comparison data record.Type: GrantFiled: May 29, 2019Date of Patent: April 25, 2023Assignee: Infineon Technologies AGInventors: Peter Bogner, Andrea Cristofoli, Michael Kropfitsch, Jochen O. Schrattenecker
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Patent number: 11606101Abstract: An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.Type: GrantFiled: August 19, 2021Date of Patent: March 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyoungjun Moon, Dongryeol Oh, Younghyo Park, Youngjae Cho, Michael Choi
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Patent number: 11588494Abstract: A sample-and-hold amplification circuit can include a sampling circuit configured to sample first and second input signals in response to first and second control signals to generate first and second sampled signals, an amplification circuit configured to amplify a voltage difference between the first and second sampled signals to generate first and second output signals, and an offset compensation circuit configured to form a first path between input and output terminals of the amplification circuit in response to the first control signal to store an offset of the input terminal and form a second path between the input and output terminals in response to the second control signal to reflect the offset to the output terminal.Type: GrantFiled: June 22, 2021Date of Patent: February 21, 2023Assignee: SK hynix Inc.Inventors: Joo Won Oh, Keun Jin Chang
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Patent number: 11387842Abstract: A system including a circuit, including a first preamplifier, a sampling switch, a regenerative latch, and a second preamplifier aligned in a pipelined sequence with the first preamplifier, wherein the first and second preamplifier are associated with dynamic comparator and configured to gain signal utilizing multiple cascaded gains and sample-and-hold stages including a plurality of phases.Type: GrantFiled: March 10, 2021Date of Patent: July 12, 2022Inventors: Sangwoo Lee, Sayyed Mahdi Kashmiri, Kenneth Wojciechowski
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Patent number: 11374585Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.Type: GrantFiled: April 27, 2021Date of Patent: June 28, 2022Assignee: SigmaSense, LLC.Inventor: Phuong Huynh
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Patent number: 10853239Abstract: A memory card controller coupled to a host device includes a processing circuit which is used for reading card specific data from a flash memory of a memory card to store the card specific data in a register wherein a multiply parameter and a basic capacity are marked in the card specific data and used for sending the card specific data to the host device to make the host device calculate a maximum capacity of the memory card according to the multiply parameter and the basic capacity marked in the card specific data.Type: GrantFiled: December 23, 2018Date of Patent: December 1, 2020Assignee: SILICON MOTION INC.Inventor: Chao-Kuei Hsieh
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Patent number: 10608658Abstract: A pipelined ADC includes a first sub ADC and a second sub ADC. The second sub ADC is configured to receive, as an input, an analog residue generated by the first sub ADC. The first sub ADC is configured to operate in a first conversion phase, generating a digital output of the first sub ADC, and a second conversion phase, generating the analog residue. The first sub ADC includes a reference-voltage generator circuit configured to generate a reference voltage of the first sub ADC and having a first mode of operation and a second mode of operation, in which the noise power of the reference voltage is less than in the first mode of operation. The reference-voltage generator circuit is configured to operate in its first mode of operation in the first conversion phase and in its second mode of operation in the second conversion phase.Type: GrantFiled: July 4, 2016Date of Patent: March 31, 2020Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Mattias Palm, Daniele Mastantuono, Roland Strandberg
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Patent number: 10396813Abstract: The analog-to-digital converter includes a first stage in which a voltage to be converted is applied to the input of a first comparator. The first comparator delivers, on a first digital output, a first digital result representative of the comparison between the voltage to be converted and the comparison voltage. The first digital output is connected to a calculator of a first intermediate voltage. A second comparator compares the first intermediate voltage with the comparison voltage and delivers a second digital result on a second digital output terminal. The second digital output terminal is connected to a second calculator of residual voltage that is a function of the voltage to be converted, of first and second voltages and of the first and second digital results. The first calculator is formed by the second calculator.Type: GrantFiled: November 10, 2016Date of Patent: August 27, 2019Assignee: SOCIETE FRANCAISE DE DETECTEURS INFRAROUGES—SOFRADIRInventor: Gilbert Decaens
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Patent number: 10340938Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.Type: GrantFiled: April 24, 2018Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Roee Eitan, Ram Livne, Ahmad Khairi, Yoel Krupnik, Ariel Cohen
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Patent number: 10277175Abstract: In order to realize a circuit in a subsequent stage with a smaller circuit scale with respect to a single-ended input of a large signal, a double-sampling switched-capacitor input circuit includes a first switched-capacitor input circuit, which includes first capacitors for double sampling, and a second switched-capacitor input circuit, which includes second capacitors for double sampling, and which is configured to operate in opposite phase to the first switched-capacitor input circuit, the double-sampling switched-capacitor input circuit having a configuration in which the first capacitors and the second capacitors have different values, and in which the value of the second capacitors is adjusted so that a signal is attenuated.Type: GrantFiled: February 24, 2017Date of Patent: April 30, 2019Assignee: ABLIC INC.Inventor: Eiki Imaizumi
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Patent number: 9973079Abstract: An integrated circuit includes (a) an analog-to-digital converter operated according to a first clock signal; and (b) a charge pump circuit providing a negative power supply voltage to the integrated circuit, the charge pump circuit being operated according to a second clock signal having a frequency that is different from a frequency of the first clock signal, such that a noise level introduced by the charge pump into the analog-to-digital converter is less than the average noise level over a predetermined range of frequencies for the second clock signal. The integrated circuit may further include a clock divider circuit (e.g., a programmable clock divider) that generates both the first clock signal and the second clock signal.Type: GrantFiled: January 30, 2014Date of Patent: May 15, 2018Assignee: Linear Technology CorporationInventors: Michael Keith Mayes, Todd Stuart Kaplan, David Edward Bliss
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Patent number: 9912341Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.Type: GrantFiled: March 1, 2013Date of Patent: March 6, 2018Assignee: Infineon Technologies AGInventor: Dieter Draxelmayr
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Patent number: 9236878Abstract: A method is disclosed. An analog signal is sampled to form a sample value using a sample and hold circuit. The sample value is converted to form a first digital result. The sample value is converted to form a second digital result.Type: GrantFiled: February 14, 2014Date of Patent: January 12, 2016Assignee: Infineon Technologies AGInventors: Peter Bogner, Herwig Wappis, Jens Barrenscheen
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Patent number: 9184761Abstract: A method, comprising: selecting three Two-Tuples before and three after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time difference between the asynchronous samples surrounding the selected sample, and the five linear slopes of the line segments between the three points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.Type: GrantFiled: February 28, 2014Date of Patent: November 10, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Abhijit A. Patki, Ganesan Thiagarajan, Udayan Dasgupta
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Patent number: 9154091Abstract: This document describes a new op-amp sharing technique for pipeline ADC without memory effect. The key features of this technique are: the usage of negative impedance converter and scaled replica of the op-amp input device to achieve zero error voltage, which in turns achieve low power dissipation due to the removal of the tradeoff between op-amp sharing and memory effect. With this technique much lower operation of pipeline ADC can be achieved for applications of data communications and image signal processing.Type: GrantFiled: September 12, 2013Date of Patent: October 6, 2015Assignee: Microchip Technologies, Inc.Inventors: Louis Hau-Yiu Tsui, Isaac Terasuth Ko
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Patent number: 9136868Abstract: An improved analog to digital converter comprises at least one delta sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages. The pipelined analog to digital converter stages may have a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage. The sampling rate of the at least one delta sigma analog to digital converter stage may be an oversampling rate. The sampling rate of the at least one delta-sigma analog to digital converter stages and the pipeline stages may be adjusted by adjusting their sampling frequency and the number of effective pipeline stages may be adjusted—for example, by adjusting a sampling frequency input at each stage. The effective number of pipeline stages may be adjusted, for example, based on the precision needed to process the current signal.Type: GrantFiled: August 22, 2014Date of Patent: September 15, 2015Assignee: Nokia Technologies OyInventor: Hans Danneels
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Patent number: 9071778Abstract: An apparatus for acquiring an i-bit digital code by a first stage AD conversion and a j-bit digital code by a second stage AD conversion includes a comparing unit which compares a reference signal and an analog signal in the first stage AD conversion; and an amplifying unit for outputting an amplified residual signal acquired by amplifying a difference between the analog signal and an analog signal corresponding to the i-bit digital code. The comparing unit compares the amplified residual signal and the reference signal in the second stage AD conversion.Type: GrantFiled: November 18, 2013Date of Patent: June 30, 2015Assignee: CANON KABUSHIKI KAISHAInventor: Daisuke Yoshida
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Patent number: 9070796Abstract: A solid-state imaging device generates signals by photoelectric conversion elements included in a first substrate in which circuit elements of a plurality of pixels are arranged. The solid-state imaging device outputs, from the plurality of pixels via output circuits, the signals that are generated by the photoelectric conversion elements and are via connection parts that electrically connect the first substrate with a second substrate, the output circuits being included in the second substrate.Type: GrantFiled: December 4, 2012Date of Patent: June 30, 2015Assignee: OLYMPUS CORPORATIONInventor: Naofumi Sakaguchi
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Patent number: 9019137Abstract: A charge canceling multiplying digital-to-analog converter (MDAC) is provided with a reference block having inputs to accept reference voltages each sample clock cycle. The MDAC includes a sampling block having inputs to accept differential analog input voltage signals each sample clock cycle. A differential amplifier has a negative input and positive input connected to the reference block and sampling block to receive differential amplifier input signals, and a positive output and a negative output to supply differential output voltage signals each amplify clock cycle. The sampling section includes a first pair of feedback capacitors connected between the differential amplifier negative input and positive output, and a second pair of feedback capacitors connected between the differential amplifier positive input and negative output each amplify clock cycle. A capacitor from the first pair of parallel feedback capacitors is swapped with a capacitor from the second pair prior to each sample clock cycle.Type: GrantFiled: January 17, 2014Date of Patent: April 28, 2015Assignee: IQ-Analog CorporationInventors: Mikko Waltari, Michael Kappes
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Patent number: 8994572Abstract: The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing.Type: GrantFiled: September 6, 2012Date of Patent: March 31, 2015Assignee: Japan Science and Technology AgencyInventors: Hao San, Tsubasa Maruyama, Masao Hotta
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Patent number: 8970409Abstract: A dynamic dithering method is provided for improving linearity in analog-to-digital converters.Type: GrantFiled: March 13, 2013Date of Patent: March 3, 2015Assignee: Hittite Microwave CorporationInventors: Oystein Moldsvor, Bjornar Hernes
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Patent number: 8970227Abstract: A circuit for capacitive touch applications has a charge integrator, a low pass-filter, and a correlated double sampler having an input capacitor. The circuit also includes a sampler and holder, and an analog to digital converter. The low pass-filter has a cut-off frequency lower than the Nyquist frequency of the sampler and holder, and the low pass filter includes input capacitor and a serial resistor.Type: GrantFiled: September 14, 2010Date of Patent: March 3, 2015Assignee: Advanced Silicon SAInventors: Olivier Nys, Hussein Ballan, Norman Chappatte, François Vuadens
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Patent number: 8957361Abstract: A switching circuit, a charge sense amplifier, and a photon counting device are provided. The switching circuit configured to close and open a connection between a first terminal and a second terminal of a predetermined circuit element, includes: a first transistor comprising a source connected to the first terminal, a drain connected to the second terminal, and a gate; a second transistor comprising a drain, a source, and a gate connected to the drain of the second transistor; a current source configured to supply a current flowing through the drain and the source of the second transistor, to generate a gate voltage of the gate of the second transistor; and a multiplexer configured to receive the gate voltage, a reference voltage, and a control signal, and selectively apply the gate voltage or the reference voltage to the gate of the first transistor based on the control signal.Type: GrantFiled: August 15, 2012Date of Patent: February 17, 2015Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Sang-wook Han, Hyun-sik Kim, Young-hun Sung, Jun-hyeok Yang, Gyu-hyeong Cho
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Patent number: 8947287Abstract: An A-type converter circuit compares an input voltage with multiple threshold voltages, judges which segment it belongs to, and generates first and second voltages with the input voltage segment between them. The A-type converter circuit generates third and fourth voltages by amplifying the differences between the first and the input voltages and between the second and the input voltages. A B-type converter circuit divides the range between the third and fourth voltages into multiple segments, and judges which segment includes the common voltage. Subsequently, the B-type converter circuit generates fifth and sixth voltages with the common voltage segment between them. The B-type converter circuit generates a seventh (the next stage's third voltage) and an eighth voltage by amplifying the differences between the fifth and the common voltages and between the sixth and the common voltages.Type: GrantFiled: August 24, 2012Date of Patent: February 3, 2015Assignee: Tokyo Institute of TechnologyInventors: Akira Matsuzawa, Masaya Miyahara
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Patent number: 8928517Abstract: An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage.Type: GrantFiled: January 9, 2013Date of Patent: January 6, 2015Assignee: Analog Devices, Inc.Inventors: Scott Bardsley, Franklin Murden, Peter Derounian, Eric Siragusa
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Patent number: 8922415Abstract: An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.Type: GrantFiled: August 10, 2013Date of Patent: December 30, 2014Assignee: MaxLinear, Inc.Inventors: Eric Fogleman, Sheng Ye, Xuefeng Chen, Kok Lim Chan
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Patent number: 8907828Abstract: A method for testing the material of a test object (8) in a nondestructive manner, said test object being moved relative to a probe (1) at a variable relative speed, comprises the following steps: detecting a probe signal (US) by means of the probe (1), subjecting the probe signal (US) to analog-to-digital conversion in order to generate a digitized probe signal (USD) in the form of a sequence of digital words with a predefined, in particular constant, word repetition rate, n-stage decimation of the word repetition rate of the digitized probe signal (USD) or of a digital demodulation signal (UM) derived from the digitized probe signal by means of n cascaded decimation stages (5_1 to 5_n), where n?2, selecting an output signal (UA_1 to UA_n) of one of the n decimation stages (5_1 to 5_n) depending on the instantaneous relative speed and filtering the selected output signal by means of a digital filter (7), which is clocked with the word repetition rate of the selected output signal.Type: GrantFiled: July 18, 2012Date of Patent: December 9, 2014Assignee: Institut Dr. Foerster GmbH & Co. KGInventors: Bernhard Holzmayer, Michael Halter
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Patent number: 8872685Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: QUALCOMM IncorporatedInventors: Tongyu Song, Sang Min Lee, Derui Kong, Dongwon Seo
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Patent number: 8854550Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.Type: GrantFiled: November 4, 2013Date of Patent: October 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Tae-Pyeong Kim, Han-Kyul Lim, Cheon-Oh Lee
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Patent number: 8836549Abstract: A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.Type: GrantFiled: December 20, 2011Date of Patent: September 16, 2014Assignee: Analog Devices, Inc.Inventors: Robert Schell, Michael R. Elliott
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Patent number: 8836565Abstract: An analog to digital converter can operate in a sampling mode or in a comparing mode. The analog to digital converter comprises: a comparator; a first capacitor, comprising a first terminal coupled to a first input terminal of the comparator; a second capacitor; a first switch module; a control unit, for controlling the conductive states of the first switch module corresponding to the sampling mode or the comparing mode. The first capacitor samples a value of a first input signal and the second capacitor samples a value of a first reference signal via the first switch module in the sampling mode. The first capacitor and the second capacitor are not coupled to each other in the sampling mode. The first capacitor and the second capacitor are coupled in series via the first switch module in the comparing mode.Type: GrantFiled: September 27, 2013Date of Patent: September 16, 2014Assignee: Mediatek Inc.Inventor: Wen-Hua Chang
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Patent number: 8830109Abstract: A pipeline analog-to-digital converter is disclosed. An example of a pipeline analog-to-digital converter comprises a plurality of stages. Each of the plurality of stages comprises an analog-to-digital conversion circuit comprising a comparator configured to produce an n-bit digital domain output; and a switchable conductance digital-to-analog conversion circuit operatively coupled to the comparator and configured to switch between at least two conductance values in response to a value of the n-bit digital domain output.Type: GrantFiled: March 12, 2013Date of Patent: September 9, 2014Assignee: Semtech CorporationInventors: Ark-Chew Wong, Masashi Yamagata
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Patent number: 8823574Abstract: A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N?n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.Type: GrantFiled: August 31, 2011Date of Patent: September 2, 2014Assignee: Sony CorporationInventor: Masaki Sakakibara
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Patent number: 8803721Abstract: A multiplying analog-to-digital converter (“MDAC”) that reduces the power consumption of the MDAC by at least 2.3 times by improving the feedback factor. The amplifier may include a feed forward approach in which the input capacitor (also referred to as “sampling capacitor”) is buffered by a common gate amplifier to improve bandwidth by removing input and parasitic capacitance terms from the global feedback loss. THe amplifier may also use an alternate form of local compensation, for example, cascode compensation. The amplifier may also further include an alternate way to reduce parasitic capacitance with a buffer.Type: GrantFiled: March 13, 2013Date of Patent: August 12, 2014Assignee: Analog Devices, Inc.Inventors: William T. Boles, Michael R. Elliott
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Patent number: 8791845Abstract: A pipeline ADC (analog-to-digital converter) (14) includes a residue amplifier (7) for applying a first residue signal (Vres1) to a first input of a residue amplifier (11A) and to an input of a sub-ADC (8) for resolving a predetermined number (m) of bits and producing a redundancy bit in response to the first residue signal. A level-shifting MDAC (9A) converts the predetermined number of bits and the redundancy bit to an analog signal (10) on the a second input of the residue amplifier, which amplifies the difference between the first residue signal and the analog signal to generate a second residue signal (Vres2). The MDAC causes the residue amplifier to shift the second residue signal back within a predetermined voltage range (±Vref/2) by the end of the amplifying if the second residue signal is outside of the predetermined voltage range.Type: GrantFiled: August 31, 2012Date of Patent: July 29, 2014Assignee: Texas Instruments IncorporatedInventors: Gautam S. Nandi, Rishubh Khurana
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Patent number: 8791844Abstract: A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.Type: GrantFiled: June 6, 2012Date of Patent: July 29, 2014Assignee: Microchip Technology IncorporatedInventors: Daniel Meacham, Andrea Panigada, Jorge Grilo
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Patent number: 8773294Abstract: A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.Type: GrantFiled: June 7, 2012Date of Patent: July 8, 2014Assignee: Analog Devices, Inc.Inventors: Stephen R. Kosic, Jeffrey P. Bray
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Patent number: 8750430Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.Type: GrantFiled: April 5, 2011Date of Patent: June 10, 2014Assignee: Fujitsu LimitedInventor: Yoichi Koyanagi
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Patent number: 8723707Abstract: A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.Type: GrantFiled: July 27, 2012Date of Patent: May 13, 2014Assignee: Analog Devices, Inc.Inventor: Ahmed Mohamed Abdelatty Ali
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Patent number: 8717219Abstract: According to one embodiment, a semiconductor integrated circuit is configured to convert a difference between a first analog voltage and a second analog voltage into a digital signal. The semiconductor integrated circuit includes m (m is an integer greater than or equal to 2) first capacitors and second capacitors. Each of the m capacitors has a first electrode and a second electrode, and the first electrodes are connected to each other. Each of the m second capacitors has a third electrode and a fourth electrode, and the third electrodes are connected to each other. The semiconductor integrated circuits further includes: a comparator configured to compare a voltage of the first electrode and a voltage of the third electrode; and a logic circuit configured to generate the digital signal based on a comparison result of the comparator.Type: GrantFiled: February 28, 2013Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Jun Deguchi
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Patent number: 8618973Abstract: The present invention is related to a pipelined analog-to-digital converter, ADC, for converting an analog input signal into a digital signal comprising—a plurality of comparing means having tuneable thresholds for comparing an input signal with; at least two of said given thresholds being different and—a plurality of amplifying circuits,—wherein said plurality of comparing means is configured to form a hierarchical tree structure, said hierarchical tree structure having a plurality of hierarchical levels, wherein at least one of said hierarchical levels is associated with at least one amplifying circuit of said plurality of amplifying circuits, said at least one amplifying circuit generating the input of at least one comparing means at the next hierarchical level and—wherein said plurality of hierarchical levels comprises means for setting said tuneable thresholds in accordance to the output of previous hierarchical level so that non-linear distortion of the preceding hierarchical level is removed.Type: GrantFiled: July 8, 2010Date of Patent: December 31, 2013Assignees: IMEC, Vrije Universiteit BrusselInventor: Bob Verbruggen
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Patent number: 8614638Abstract: A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.Type: GrantFiled: June 19, 2012Date of Patent: December 24, 2013Assignee: QUALCOMM IncorporatedInventors: Sotirios Limotyrakis, Michael Peter Mack, Hyunsik Park, Sang-Min Lee, Brian James Kaczynski, MeeLan Lee
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Patent number: 8604962Abstract: A first stage circuit for a pipeline ADC first stage combines the functions of an input sample-and-hold-plus-amplifier (SHA) stage, and the functions of the first analog-to-digital conversion stage of an ADC, including a multiplying DAC (MDAC), stage-flash ADC (SFADC) comparators, and residue opamp (RAMP). The ADC first stage is duplicated, inputs and outputs are connected, and an autozero circuit using a switched-capacitor filter feedback loop controls the RAMP bias circuitry to reduce 1/f noise and DC offsets. The sampling capacitors may be connected to the ADC input for one full sample clock time period and are disconnected from the analog input period before connecting the sampling capacitors to an amplifier voltage output or voltage reference, thereby sampling the input and allowing sufficient time for the SFADC comparators to resolve and control the MDAC capacitor settings with a low metastability error rate.Type: GrantFiled: November 28, 2012Date of Patent: December 10, 2013Assignee: Lewyn Consulting IncInventor: Lanny L Lewyn
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Patent number: 8552900Abstract: A successive approximation register switched capacitor analog to digital converter utilizes a high frequency clock for controlling comparator reset switches and a clock distribution block to operate at lower sample rates. The successive approximation cycles are clocked with the high frequency clock so that the reset switches stay within the leakage limit irrespective of the sample rate but the end of conversion signal is delayed to mimic the slower sample rate.Type: GrantFiled: April 20, 2012Date of Patent: October 8, 2013Assignee: Texas Instruments IncorporatedInventors: Haydar Bilhan, Maher Mahmoud Sarraj
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Patent number: 8548767Abstract: The invention relates to a measuring device having at least one first assembly and at least one second assembly. The first assembly and the second assembly each comprise an intermediate frequency interface or a complex baseband interface. The intermediate frequency interfaces or baseband interfaces are designed as serial digital interfaces.Type: GrantFiled: February 7, 2008Date of Patent: October 1, 2013Assignee: Rohde & Schwarz GmbH & Co. KGInventors: Gottfried Holzmann, Werner Mittermaier
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Patent number: RE45282Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A system includes a CMOS active pixel image sensor having an array for photoreceptors to convert an image into an analog signal. The CMOS image sensor converts the analog signal into a digital signal using a pipelined analog to digital converter.Type: GrantFiled: January 24, 2012Date of Patent: December 9, 2014Assignee: Round Rock Research, LLCInventors: Eric R. Fossum, Sandor L. Barna
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Patent number: RE45493Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A CMOS image sensor converts successive analog signals, representing at least a portion of an image, into successive digital signals using an analog to digital circuit block. Multiple clock cycles may be used by the circuit block to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal by the circuit block may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal by the circuit block.Type: GrantFiled: June 25, 2012Date of Patent: April 28, 2015Assignee: Round Rock Research, LLCInventors: Eric R. Fossum, Sandor L. Barna