Abstract: A data converter (10) includes an analog input element (12), an operational amplifier (14), a first reference input element (18), a second reference input element (22), and a control element (34). The analog input element (12) operably couples the analog signal to a first input (13) of the operational amplifier (14). The first and second reference input elements (18 & 22) respectively couple a first signal (16) and a second signal (22) to a first input of the operational amplifier (14). The control element (34) generates the control signal based on an output of the operational amplifier (14) to force the first input node (13) to be equivalent to the second input node (15) of the operational amplifier (14). The data converter (10) also includes an analog-to-digital converter (26) that allows the circuit to perform a sigma-delta conversion.

Abstract: In an analog/digital converting circuit, when an analog input voltage exceeds a reference voltage, the analog input voltage is modified into analog voltages not exceeding the reference voltage, and comparison voltages generated by dividing the reference voltage are compared with the modified analog voltages.

Abstract: A method and apparatus is disclosed for an analog-to-digital converter (ADC) to minimize power consumption. The ADC of the present invention minimizes the number of clock cycles required to determine the correct digital code for a particular sample point on an electrogram signal, thus making it possible to turn off some or all of the ADC logic during idle periods. The ADC includes prediction logic that provides a starting point for subsequent digital code representations of the electrogram signal. The prediction logic receives recent code conversions values to predict a current digital code value. This predicted digital code is converted to an analog value and compared with the actual electrogram signal. Next, the ADC adds (or subtracts) a constant value (C) to (or from) the predicted code and compares the result to the electrogram signal.

Abstract: A receive signal strength indication analog-to-digital converter includes a digital portion and an analog portion. The digital portion includes structure for approximating radio frequency receive signal strength in digital form and a state machine implementing a successive approximation algorithm. The analog portion includes a digital-to-analog converter, an analog comparator, and structure for transmitting the output of the digital-to-analog converter to the analog comparator. The receive signal strength indication analog-to-digital converter also includes structure for transmitting the approximate radio frequency receive signal strength in digital form to the digital-to-analog converter and structure for transmitting the output of the comparator to the state machine.

Abstract: A multistage pipelined algorithmic A/D converter digitally calibrated to avoid errors due to charge injection, offset and capacitor mismatch. To perform this calibration, measurements are made at the converter to determine the degree of capacitor mismatch for each stage to be calibrated. In the embodiment disclosed, only one stage is calibrated. The remaining stages of the converter are employed to develop the digital calibration data for the stage being measured. This calibration data is stored in a memory forming part of the converter. The stored data is thereafter used during each conversion to cancel the errors due to capacitor mismatch.

Abstract: A sequential conversion-type A/D converter having a fixing bit register for identifying which bits of a sequential conversion register are to be fixed, a fixed value register for holding the binary values of the bits of the sequential conversion register to be fixed, and a conversion start position setting circuit for identifying a leading bit of the sequential conversion register as a bit of a lower order than the bits of said sequential conversion register to be fixed. The control circuit starts sequential conversion from the bit set by the conversion start position setting circuit. The invention achieves a sequential conversion type A/D converter which can convert, in a shorter period of time than the prior art, analog input signals showing small changes, without deteriorating conversion accuracy.

Abstract: A subranging analog-to-digital converter wherein, during a first phase, a differential analog input voltage is held by a track and hold circuit and is fed to a low resolution flash ADC to provide the most significant bits (MSBs). During a second or recirculating phase, flash ADC output segments corresponding to the MSBs are fed to respective current switches of a current DAC to produce complementary analog conversion currents that are coupled to the track and hold circuit. In response to the complementary DAC currents, the output stage of the track and hold circuit is used to subtract a voltage corresponding to the MSBs from the input voltage without the use of a separate subtractor. Further, the DAC current switches provide equal currents during the first or MSB phase to deactivate the subtraction function during the first phase.

Abstract: A current integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to receive a ground voltage and an inverting input coupled to an input conductor, with an input current flowing through the input conductor, an integrating capacitor having a first terminal coupled by an isolation switch to the input conductor. A reset circuit is coupled to the integrating capacitor and is operative to reset the integrating capacitor before each integrating cycle. A digital-to-analog converter, which may be a CDAC, has an output coupled to a second terminal of the integrating capacitor, which may constitute the capacitors of the CDAC. An input of a tracking circuit is coupled to an output of the comparator to produce digital signals on digital inputs of the digital-to-analog converter to maintain the input of the comparator close to a virtual ground voltage, a digital signal on the inputs of the digital-to-analog converter representing the integral of the input current.

Abstract: In an A/D converter for electrical signals, the difference, between the instantaneous analog input signal Y(t) and a previous analog signal value Y(t-T), is converted in a fast analog-to-digital converter (3) to a digital sum value. This sum value is added to the preceding digital value, stored in a buffer memory (7, 7'), and the result is fed to a slow but precise D/A converter (2) for generation of the next Y(t-T) value. This has the advantage that good results can be obtained with A/D converters less expensive than those heretofore required to obtain such results.

Abstract: An image signal correcting circuit device includes an A/D conversion unit for converting an analog image signal output from an image reading unit into a digital signal, a storage unit for storing correction data, and a correction unit for performing correction on a signal based on the correction data stored in the storage unit. The correction data stored in the storage unit is difference data between at least two pixel signals in the digital signal which is generated by a correction data generating unit. Alternatively, the correction data stored in the storage unit is obtained by amplifying an analog reference signal by an amplification factor of m (m>1) and by converting the amplified analog signal into a digital correction signal by the A/D conversion unit.

Abstract: An analog-to-digital converter includes a sample and hold circuit for sampling and holding an analog input signal, a comparator circuit for comparing the analog input signal held by the sample and hold circuit with an input signal and generating an output signal, a control circuit for generating a digital signal based on the output signal of the comparator circuit, a digital-to-analog converter for converting the digital signal generated from the control circuit into an analog signal and for supplying the analog signal to the comparator circuit as the input signal, and an initial setting circuit for initializing the analog input signal held by the sample and hold circuit and the input signal which is output from the digital-to-analog converter to a reference voltage.

Abstract: A high resolution analog to digital converter is provided which operates at a relatively high speed. The converter will operate in either a bipolar or unipolar mode and the bipolar mode includes a signal/sign transposer. A sample/holding circuit temporarily holds the analog input at its sample level. The device also includes analog to digital converter, a reference selector, a reference source, a digital/analog converter, a subtracter for conversion voltages, a plurality of latches, a buffer and timing/control circuitry.

Abstract: A cyclic analog-to-digital converter includes two arithmetic circuits and a single comparator. The output of each arithmetic circuit is connected to the input of the other arithmetic circuit. Each arithmetic circuit can modify the analog signal being converted in accordance with output signals from the comparator. Embodiments are disclosed in which the arithmetic circuits include switched capacitors and separate or shared operational amplifiers.

Abstract: A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.

Abstract: In an analog-to-digital converter, a circuit for sampling an analog input signal that has a signal range above and below a ground reference voltage includes a divider circuit scaling the analog input signal down to a lower magnitude such that all values of the scaled analog input signal are above the ground reference voltage. The scaled down analog input signal is applied to a source electrode of a sampling MOSFET. A body-to-source voltage of the sampling MOSFET is maintained at approximately zero volts by applying the scaled down signal to a non-inverting input of a first operational amplifier and applying an output voltage produced by the first operational amplifier to its inverting input and a body electrode of the sampling MOSFET. A gate-to-source voltage of the sampling MOSFET is maintained at approximately 1.

Abstract: An A/D converter comprises a first stage integrator for receiving an input signal, a last stage integrator, a multibit A/D converter connected to the output terminal of the last stage integrator, an outer feedback loop connected between the output terminal of the multi-bit A/D converter and the input terminal of said first stage integrator and having a 1-bit D/A converter, an inner feedback loop connected between the output terminal of the multibit A/D converter and the input terminal of the last stage integrator and having a multibit D/A converter, and a digital signal processing circuit, connected to the output terminal of the A/D converter, for performing digital signal processing of an output from the A/D converter to eliminate quantization noise caused by the outer feedback loop.

Abstract: A neural network quantizer for quantizing input analog signals includes a plurality of multi-level neurons. The input analog signals are sampled and supplied to respective ones of the multi-level neurons. Output values of the multi-level neurons are converted into analog values, weighted by weighting coefficients determined in accordance with a frequency band of at least one frequency component of the input analog signals and fed back to the respective one of the multi-level neurons and to the other multi-level neurons. The weighted analog values fed back are compared with the respective ones of the sampled input analog signals. The output values of the multi-level neurons are corrected in response to the compared results, and when the compared results are converged within a predetermined range, the output values of the multi-level neurons are produced to quantize the input analog signals.

Abstract: An analog-digital converter having an analog integrator which integrates the difference between the analog input signal and a signal from, for example, a digital-analog converter controlled by a microprocessor, whereby a high resolution and a very high operating speed are rendered possible with a relatively low degree of complexity and minimal noise.

Abstract: An analog-to-digital converter comprises plural amplifiers, a first group of transistors for input, a second group of transistor for biasing, a third group of transistors for feedback and plural inverters. The first group of transistors are PMOS transistors, and the second and third groups of transistors are NMOS transistors. The connecting weight of each transistor may be set with the conductance values thereof in accordance with a geometrical aspect ratio W/L of MOS transistors. The amplifiers comprise two CMOS inverters connected in series.

Abstract: An algorithmic analog/digital converting circuit in accordance with the present invention comprising a control signal generator for inputting a least significant bit signal from a shift register, a start signal and a clock signal to output a first to a tenth switching signals for controlling ON/OFFs of a first to tenth switches and a latch signal for controlling latch of said shift register, in order to perform an operation of steps of sampling an input signal and a reference voltage signal, comparing the sampled input signal with the sampled reference voltage signal, subtracting or holding in accordance with an output signal from a comparator reproducing the subtracted or held signal and amplifying the reproduced signal.

Abstract: A current-integrating analog-to-digital converter includes a comparator having a non-inverting input coupled to a ground voltage and an inverting input coupled to an input conductor carrying an analog input current. An integrating capacitor having one terminal coupled to the input conductor and another terminal coupled to an output of a digital-to-analog converter. A tracking circuit is coupled to an output of the comparator to apply digital signals to inputs of the digital-to-analog converter to maintain the inverting input close to a virtual ground voltage. A digital filter filters the digital signals to produce a digital output signal that precisely represents the input current.

Abstract: A successive comparison type analog-to-digital (AD) converter having a successive comparing circuit which is implemented by two successive comparators, and having a parallel two sequence AD conversion capability while adapting itself to another conversion system at the same time as needed. The successive comparators are not expensive and are, therefore, sucessful in constituting an inexpensive successive comparison type AD converter.

Abstract: A successive approximation analog-to-digital converter whose susceptibility to errors is reduced by the use of overlapping measurement ranges in the successive conversion steps.

Abstract: A high-speed algorithmic successive approximation analog to digital converter includes a system input terminal, and a tri-state comparator having an input terminal connected to the signal sampler. The comparator produces a first indication of a signal on its input terminal exceeds an upper reference voltage and the comparator produces a second indication if a signal on its input terminal exceeds the lower reference voltage, and does not exceed the upper reference voltage. A subtractor is connected to the system input terminal and to the comparator for subtracting from a received signal a first value corresponding to the upper reference voltage if the comparator produces the first indication, or a second value corresponding to the lower reference voltage if the comparator produces the second indication.

Abstract: A multiplexing parallel analog digital converter including two multiplexers, comparators, a demultiplexer, and a control unit. One multiplexer is provided the reference voltages resulting from a voltage division of inner resistors by a most significant bit reference ladder and a least significant bit reference ladder for the reference voltage of the next comparison. The other multiplexer is provided the reference voltages by accepting an analog input signal and the difference signal between an analog input signal and the output of a 4-bit digital analog converter. By using two multiplexers, only one analog digital converter is needed in this present device, so, the number of comparators is reduced. The multiplexer sends the digital signals compared with the most significant bit signal and the least significant bit signal, respectively, to a most significant output latch and a least significant output latch, respectively, so the 8-bit digital signal is obtained.

Abstract: A successive approximation analog to digital converter including at least one superconducting loop (FIG. 3-30; FIG. 8-68). Superconducting loops (61-64) may be used to store flux quanta used as reference levels in a digital to analog converter of the analog to digital converter. Alternatively, non-superconducting reference inductors (FIG. 3-38) can provide flux quanta reference levels. Switchable screens (34; 66) are interposed between the flux quanta stores and lobes (31; 74) in an addition/subtraction superconducting loop (30; 68). An analog signal is sampled and the corresponding magnetic flux coupled to a sensing lobe (32; 71) and concentrated at a flux concentrating lobe (33; 72). The reference fluxes are selectively coupled into the addition/substraction superconducting loop until a magnetometer (40;73) indicates zero net flux through the concentrating lobe, this corresponding to completion of the conversion.

Abstract: An A/D converter comprises a D/A conversion circuit, a sample-holding circuit which samples and holds the output signal of the D/A conversion circuit, a substraction circuit which performs subtraction for the output signal of the D/A conversion circuit and the output signal of the sample-holding circuit, a subtracting-amplifying circuit which performs subtraction for the output signal of the substraction circuit and the input analog signal and amplifies the result of subtraction, a switch circuit which blocks the input analog signal to the subtracting-amplifying circuit, and an A/D conversion circuit which performs A/D conversion selectively for the input analog signal or the output signal of the subtracting-amplifying circuit.

Abstract: A high resolution analog to digital (A/D) converter amplifies and filters a magnitude difference between a pulse width modulated offset voltage and an input voltage to produce an amplified filtered difference voltage, the duty cycle of offset voltage modulation being adjusted such that the magnitude of the difference voltage is within a narrow input voltage range of a recirculating remainder A/D converter. The amplified, filtered difference voltage is converted to representative digital data by the recirculating remainder A/D converter. A microprocessor, which controls the offset voltage, combines the result with the magnitude of the offset voltage to produce a comparatively high resolution digital representation of the input voltage.

Abstract: An unknown analog signal is compared in amplitude with the signal from a digital-to-analog (D-A) converter. The converter, preferably monotonic, may be at least partially formed from a plurality of switches connected in a recursive array to define sub-sets having a recurrent relationship. An adjustable-gain amplifier produces a difference signal having an amplitude indicating the amplitude comparison. A flash converter converts the difference signal to binary signals. These binary signals are modified and fed back to the D-A converter to obtain from this converter an output signal having an amplitude approximating the amplitude of the unknown analog signal. A plurality of successive approximations of the analog signal may be provided in this manner. In at least one (1) of these approximations, the gain of the amplifier may be increased to increase the sensitivity of the approximation by increasing the gain of the difference signal.

Abstract: Besides an input switched capacitor (14) for sampling an input analog signal into output electric charges, an oversampling analog-to-digital converter comprises an additional switched capacitor (47) for sampling, into additional electric charges in synchronism with the input switched capacitor, controlled electric charges produced by a capacitor array (24) which is coupled to a reference voltage source (23) and is controlled by a predetermined number of control signals produced by a control logic (22) in response to an output digital signal. A summing circuit delivers the output and the additional electric charges to an integrator (15) connected to a quantizer (21) which produces a quantized signal substantially identical with the digital signal. Preferably, the summing circuit comprises a connecting switch (49) for supplying the output and the additional electric charges to the integrator in synchronism with the input and the additional switched capacitors.

Abstract: An automatic level control circuit for a multi-level quadrature amplitude-modulated (QAM) demodulator having a QAM detector, which produces baseband in-phase (P) and quadrature (Q) signals in response to an input QAM camer wave, and two analog-digital (A/D) convertors which convert the Q and P signals into two parallel digital signals. Automatic level control of the input level of the baseband signal to the A/D convertor is maintained constant by the combination of a reference signal generator in a feed back loop with each A/D convertor. The A/D convertor produces a decoded digital signal and the reference voltage generator, in response to those signals, provides reference voltage to the A/D convertor that are optimized in response to variations in input signal level.

Abstract: In a digital communication system, a residual signal is generated, encoded, and combined with an encoded information signal in a manner that does not appreciably degrade the encoded information signal. The information contained within the residual signal may be used by the receivers to improve the quality of the recovered signal. The residual signal is modulated such that it may only be recovered when the signal-to-noise ratio is sufficiently high. In this way, the quality of the recovered signal improves with increased signal-to-noise ratio.

Abstract: An A/D converter utilizing a charge redistribution scheme includes a single ended comparator and associated therewith a capacitor array of binary weighted capacitors. The input signal is sampled with the input of the comparator disposed at a point midway between ground and a unipolar reference voltage. The bottom plates of the capacitors in the hold mode are then disposed at the midpoint of the reference signal. In the redistribution mode, the value of the bits is determined by switching the bottom plates of the capacitors between the midpoint of the reference voltage and either ground or the full value of the reference voltage. The input signal during sampling is attenuated by sampling it onto only one-half of the array.

Abstract: In a successive approximation analogs-to-digital converter, a successive approximation register (SAR) includes an N bit, edge triggered shift register, each bit including a master-slave flip-flop. The output of each shift register bit is applied to a latch input of a D-type latch and to one input of a two-input gate that performs a logical ANDing function. Another input of the gate is connected to an output of the latch. The D input of each of the N latches is connected to an output of a corresponding comparator, which compares an analog input signal to a signal produced by an N bit digital-to-analog converter (DAC) in response to successive approximation numbers produced by the SAR. The gate outputs are connected to digital inputs of the DAC. A "0" propagates through the shift register at the DAC conversion rate.