Abstract: The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Abstract: A system includes a signal generator and a correlator. The signal generator outputs a first signal to a first end of a capacitance to be measured. The correlator is connected to an output of the signal generator that outputs the first signal and to a second end of the capacitance. The correlator receives the first signal from the output of the signal generator and receives a second signal from the second end of the capacitance. The correlator correlates the first signal and the second signal and generates an output signal based on a correlation between the first signal and the second signal. The output signal is proportional to a capacitance value of the capacitance.

Abstract: An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N?2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.

Abstract: An imaging apparatus and a method of driving the same that can generate a digital data of a high resolution pixel signal are provided. The imaging apparatus includes: a pixel (10-1) for generating a signal by photoelectric conversion; a comparing circuit (30-1) for comparing a signal based on the pixel with a time-dependent reference signal; a counter circuit (40-1) performing a counting operating until an inversion of a magnitude relation between the signal based on the pixel and the time-dependent reference signal; and a selecting circuit (30-2) for setting a time-dependent change rate of the reference signal, according to a signal level of the signal based on the pixel.

Abstract: An information processing apparatus includes: status information input means for inputting status information indicating an operating state and power consumption of each of a plurality of electronic appliances targeted for connection from the plurality of electronic appliances; list screen generating means for generating a list screen that associates the status information inputted from each of the plurality of electronic appliances with the plurality of electronic appliances; and a display control means for controlling display means for displaying the list screen thereon.

Abstract: An analog to digital converter with increased sub-range resolution. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a full-range ADC having a first quantization accuracy configured to sample the analog communication signal across the full-range and a central sub-range ADC having a second quantization accuracy greater than the first quantization accuracy and configured to sample the analog communication signal across a central sub-range of the full-range. The ADC also includes signal combining circuitry configured to process outputs of the full-range ADC and the central sub-range ADC to create the digital communication signal.

Abstract: An AD converting device includes a resistance-voltage conversion circuit which changes a first integrated voltage in proportion to a product of a varied resistance of a variable resistance and an electrical current applied to the variable resistance and changes a second integrated voltage and a reference voltage in proportion to a product of a total resistance of the variable resistance and the electrical current.

Abstract: An analog to digital converter with increased sub-range resolution and method for using the analog to digital converter is described herein. The device includes an analog front end that produces an analog communication signal, a digital front end that receives a digital communication signal, and an Analog to Digital Converter (ADC) that samples the analog communication signal across a full-range. The ADC includes a plurality of sub-range ADCs, each sub-range ADC measuring the analog communication signal across at least one respective sub-range of the full-range, the plurality of sub-ranges extending across the full-range, a central sub-range ADC having greater quantization accuracy than at least one other sub-range ADC. The ADC also includes signal combining circuitry operable to process outputs of the plurality of sub-range ADCs to create the digital communication signal.

Abstract: An analog-to-digital converter converting an analog input signal into a digital signal includes a comparator comparing a reference signal with an input signal and, if the reference signal matches the input signal, inverting an output; and a counter counting a comparison time. The counter includes flip flops that perform serial input/output. An input and an output of the counter are interconnected. The counter operates in a counter mode and a shift register mode. In the counter mode, a data output of each flip flop is supplied to a clock input of the next flip flop, and, if the output of the comparator is at a predetermined level, the counter functions as a counter synchronized with a counter clock signal. In the shift register mode, the flip flops are cascade-connected, and the counter functions as a shift register synchronized with a shift register clock signal.

Abstract: A rearview assembly includes a mounting structure for attaching to a vehicle. The mounting structure includes a housing that has a rearview element disposed inside for providing a driver of the vehicle with a view to the rear of the vehicle. The rearview assembly also includes a continuously variable slope delta encoder module in or on the mounting structure configured to generate a feedback signal. The rearview assembly also includes a pre-processing module on or within the mounting structure. The pre-processing module is configured to process a source signal and the feedback signal from the continuously variable slope delta encoder module, and to provide a pre-processed signal to the continuously variable slope delta encoder module based on the value of the source signal and the feedback signal.

Abstract: The invention relates to normalisation of a TDC system (20). The TDC system (20) comprises a TDC core (21), a gain normalization circuit (22) and an adjuster (23). The TDC core (21) comprises a set of nominally identical delay elements and converts the time difference between the edges of a reference clock signal (FREF) and a controllable clock signal (CLK) into a raw TDC output code as a digital word. The adjuster (23) is configured to carry out the gain normalisation by adjusting the output code. The gain normalization circuit (22) comprises at least a processor for analyzing the occurrence probability of the output code values, and for determining the adjustment to be made by the adjuster (23) according to said occurrence probability.

Abstract: A method and apparatus are provided for sigma-delta (??) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

Abstract: A solid-state image pickup device includes a pixel array including pixels arranged in a matrix, a pixel signal readout unit, and a timing control unit for controlling processing of the pixel signal readout unit by using a timing signal. The pixel signal readout unit includes: a plurality of comparators for comparing a readout signal potential with a reference voltage to generate a determination signal and outputting the determination signal, and a plurality of counters. Each counter counts a comparison time of each corresponding one of the comparators. The timing control unit (a) divides a predetermined processing period into at least a first-time readout period, a first comparison period, a second-time readout period, and a second-time comparison period, (b) classifies the periods into two periods, and (c) generates a timing signal of processing of each divided period by counting for each divided period in the counter.

Abstract: Measurement amplification methods and devices for detecting the detuning of a measurement bridge (10) to which a bipolar, rectangular supply voltage (Us) is supplied. The methods and devices use integrating A/D conversion and are characterized in that a reference voltage (Uref) used for the A/D conversion undergoes polarity changes synchronized with the polarity changes of the supply voltage (Us). Offset and drift are eliminated by totaling an even number of individual measurements.

Abstract: An AD converter includes an analog data storing unit, a first DA converter for converting an input digital data into a first analog reference voltage which varies within a first voltage range in a range of every possible signal voltage of the input analog data, a second DA converter for converting the input digital data into a second analog reference voltage which varies within a second voltage range in the range of every possible signal voltage of the input analog data, a first comparator for comparing the input analog data with the first reference voltage, a second comparator for comparing the input analog data with the second reference voltage and a digital data storing unit for storing a digital data corresponding to a point of time when a change of state occurs in the comparison results of each of the first and second comparators.

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

Abstract: A system for measuring signals in a non-linear network is provided which reduces the reliance on hardware and processing support when correcting for A/D offset by performing a pair of dual slope measurement cycles with an integrating analog to digital converter (ADC) circuit. Each of the measurement cycles has at least four phases including a first integrating phase and a first de-integrating phase followed by a second integrating phase and a second de-integrating phase. The system further includes an ADC controller operatively communicative with the integrating ADC circuit for detecting when the first count value is reached during the second de-integrating phase and then resetting the second count value in response to this detection so that the second count value is offset corrected at the end of the second de-integration phase. As a result, a difference calculation is automatically performed during the measurement cycle.

Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: The signal processing device comprises determining means to supply an output signal having a value representative of a time constant of a part of an input signal having an appreciably exponential form. The determining means comprise first integrating means to supply a first integration signal representative of integration of the input signal in two opposite directions for appreciably equal times. Extraction means connected to the first integrating means supply a value representative of a time constant as a function of the first integration signal. The process comprises integration and extraction steps to supply the value representative of a time constant.

Abstract: A multislope, continuously integrating analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: A multislope, continuously integrating analog-to-digital converter includes a first switch coupled to a first reference voltage, a second switch coupled to a second reference voltage, a third switch coupled to an input voltage, and an integrator operably coupled to the first, second, and third switches. The analog-to-digital converter utilizes a primary discharge current of opposite polarity to a secondary discharge current. The analog-to-digital converter has a high resolution due to a small reference voltage, and a high dynamic range due to a large reference voltage. The analog-to-digital converter can operate in either a conversion mode or a calibration mode. During the calibration mode, a calibration factor is calculated for use during the conversion mode. When applied to the conversion mode, the calibration factor corrects for errors in the conversion process.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: A low-cost circuit processes, with high precision, the output signals of a pointing stick used for controlling a cursor on a computer display screen. A two-stage method of high precision moderate range analog-to-digital (A/D) conversion is combined with a known method of A/D conversion by sweeping a reference voltage across the range of the voltage to be measured at a known rate and noting the time of coincidence. Operational amplifiers of moderate quality are used in an open-loop mode, so that the operational amplifier inputs are high impedance. In order to get sufficient isolation from power supply noise and variations, the analog circuitry is isolated from the supply voltage while measurements are being made.

Abstract: According to the present invention, standard analog to digital converter circuitry may be utilized to measure an unknown analog value and to produce a digital value after conversion that automatically contains an offset value with respect to a given measurement range. The digital value produced according to the present invention is not representative of a raw measurement value but rather is representative of a value with respect to a given measurement range; thus, a digital value of 0 may indicate the minimum value of a given measurement range rather than a value of 0 Ohms, 0 volts, or 0 Amps. This may be expressed in equation form where the desired conversion value is represented by:k(X.sub.unknown -X.sub.offset)where k is a constant, X.sub.unknown is the unknown analog value being measured, and X.sub.offset is the offset value. X.sub.offset the offset value may or may not be equal to a reference value.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value.

Abstract: An analog-to-digital converter operates according to the multiple ramp procedure with continuous integration of the input signal in a charge storage or charge summation circuit, whereby downward integration is performed at periodically recurrent time intervals with the aid of a comparator circuit at the output of the charge storage or charge summation circuit, a logic circuit, a clock oscillator, a switching circuit, a first reference signal and a second reference signal. Hereby the duration of the switched-on state of one of the reference signals is a measure for the input signal. The transfer function of the quantization noise H.sub.q (z) with an n-th order (n=1,2,3, . . . ) high pass filter characteristic can be derived from a transfer function H(z) describing the specified configuration.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps.

Abstract: Method and apparatus for converting an analog input voltage signal (preferably in the form of a low-frequency rectangular voltage) to a digital output signal proportional to the input voltage. The input voltage is integrated to the integrator voltage over a certain integration time. After the expiration of the integration time, the integrator voltage is de-integrated to zero over a de-integration time by a reference voltage and the input voltage is found from the ratio of de-integration time to integration time, multiplied by the reference voltage. During the integration time, modulation pulses, preferably derived from the reference voltage, are superimposed on the input voltage and thus the integrator voltage is influenced, so that a given integrator voltage is obtained regardless of the input voltage.

Abstract: An integrating analog-to-digital converter comprising an integrator, a memory capacitor for memorizing the potential of an integrated output from the integrator, a comparator for comparing the potential memorized in the memory capacitor and the potential of the integrated output divided by a set of potential dividing resistances, a clock pulse generating circuit, a counter for counting the period until the integrated output of the reference voltages passes through a reference level using clock pulses, and a reversible counter for counting the period from when the integrated output passes through the reference level to when the integration is completed, by the clock pulses, and for adding its value to the counted value from the counter as low order digits; wherein the number of digits of AD conversion is increased, and high conversion accuracy and high resolution are realized by enlarging the time period from the reference level crossing point to a clock pulse immediately after the crossing in the reference vo

Abstract: A multislope A/D converter is presented which employs a multislope integration technique enabling the use of a single comparator to detect polarity changes in the integrator output voltage. The run-up interval of the integrating A/D converter is controlled by a four-step pattern that is repeated as many times as is required in order to keep the integrator output voltage within the confines of a preselected voltage range. During the first step of the four-step pattern, a positive reference charge is applied to the integrator. In the second step, a decision is made as to whether to either maintain the application of the positive reference charge to the integrator or to change over to the negative reference charge. The decision is determined such that the reference charge causes the integrator output voltage to move toward or through a preselected target voltage range.

Abstract: A multislope continuously integrating analog-to-digital converter for converting an analog input signal into a digital output signal where the converter employs an integrator for continuously integrating the input signal in relation to a series of reference voltages of increasing magnitude and a zero crossing detector to determine when the reference voltage has completely discharged the integrator. A counter or the like is employed for timing the duration of the discharge which corresponds to the digital equivalent of the analog input signal.

Abstract: An integrating analog-to-digital converter (ADC) which calculates the coarse portion of its output by integrating an input analog signal over a predetermined number of time intervals during runup using a known technique to define the analog signal in terms of a slope count. The invention is particularly characterized in that an ADC is used in lieu of rundown of the integrator voltage to calculate the fine portion of the ADC output also in terms of slope count. This is accomplished by converting the residual analog signal remaining at the end of runup into a fractional slope count which can be added to the slope count determined during runup so that the resulting total slope count is directly proportional to the input voltage. To maintain linearity, calibration of the circuit is necessary and is accomplished by calculating a calibration constant which relates the ADC reading to slope count.

Abstract: Integrating analog to digital converter operating according to a multiple ramp procedure and having a charge storage or charge summation circuit which continuously up-integrates an input signal and which by means of a following comparator, a logic circuit and reference currents or reference voltages, down-integrates during periodically recurrent time intervals, the instants being defined by an oscillator, a timebase counter and a bistable stage. The time between two successive such instants being called a submeasurement. At the imput of the charge storage or charge summation circuit used for the input signal or at one its other inputs, convergence accelerating signals are superimposed after every nth (n=1,2,3, . . . ) submeasurement to provide for strongly enhanced convergence range and for shorter convergence period, and these convergence accelerating signals having Taylor series expansions according to time in the time interval of a submeasurement which are first or higher order polynomials.

Abstract: A multiple ramp analogue-to-digital converter comprises an integrator connected to receive and integrate an analogue input signal to be converted, and an opposing coarse reference signal. Instead of these signals being applied to the integrator sequentially, as is conventional, they are applied simultaneously. A flash converter is used to provide a rough initial estimate of the magnitude and polarity of the analogue input signal, so that the duration of application of the coarse reference signal can be estimated in advance. A fine reference signal is then applied to the integrator to restore its output to zero and improve the resolution of the conversion.

Abstract: The present invention provides a switched capacitor analog-to-digital converter for the sampling of an analog input signal and conversion to an equivalent digital format utilizing a multi-slope conversion technique. The elements comprising the converter are, preferably, integrated onto a single chip using CMOS technology. The converter includes a processor for coordinating switching in the converter and generating the digital output signal. A sampling circuit having a switched capacitor controlled by the processor is included in the converter for sampling the voltage of the analog input signal and transferring charge representative of the analog input signal between an integrator and the sampling circuit. Further included in the converter is a discharge circuit for either transferring charge to the integrator or receiving charge from the integrator.

Abstract: In a continuously variable slope delta modulation encoder or decoder, the slope of a reconstructed signal is varied by selecting the charging voltage across an integrating capacitor. For an NTSC video signal, the charging voltage may be selected by a shift register connected to a voltage divider supplying the integrating capacitor.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.

Abstract: There is provided according to the invention a method and apparatus for eliminating or minimizing the error due to amplifier offset or drift error in an integrating dual slope analog-to-digital converter. The converter is provided with a switching and control arrangement whereby the integrating capacitor is charged for one-half of the predetermined charging time as a function of the sum of the levels of the unknown signal and the error signal. The integrating capacitor is charged for the remaining half of the predetermined time period as a function of the difference of the levels of the unknown signal and the error signal so that the capacitor reaches a level of charge which is a function of the level of the unknown signal substantially unaffected by the level of the error signal.

Abstract: An analogue to digital multi-slope converter has an integrator 10 to which an analogue input signal 30 is continuously applied. A reference voltage 36, 37 is superimposed onto the integrator input 30 in pulse form, being switched on and off according to a predetermined program controlled by a clock and modified by a comparator 11 such that reference voltage pulses occur in pairs of opposite polarity. The sequence of pulses is applied in such a manner that the final pulse of a sequence causes the integrator output to move towards a comparator 11 reference level, the reference voltage then being maintained until the reference level is reached after which a new cycle is started.

Abstract: Apparatus including an analogue-to-digital converter 26 having a given number of digits, includes a variable gain amplifier (23) for the input (VA) to the converter (26). If any one instantaneous value (21A) of the input (VA) is less than is necessary to saturate the converter (26), i.e. to use all the digits of the converter (26), the gain of the amplifier (23) is automatically set to amplify the instantaneous input (21A) to the extent necessary to saturate the converter (26). By such selective amplication of different outputs (VA), each instantaneous value (21A) is digitized by the full number of digits of the converter (26) and the resolution of the apparatus is the same for all inputs (VA) regardless of their magnitude. On the other hand the converter is not over-saturated such as could be the case if the different inputs (VA) were amplified by a common gain.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.