Intermediate Conversion To Time Interval Patents (Class 341/166)
  • Patent number: 11187792
    Abstract: The device executes a method for determining the delay time of a first wavelet in a transmission path (I1). For this purpose, the first wavelet is transmitted into the transmission path (I1) at a time after a reference time. After passing through the transmission path (I1), the delayed and typically deformed transmission wavelet is scalar-multiplied with a second (analysis) wavelet. The result is compared to a reference value. The scalar product value adopts the reference value at a time (ts). The delay of the first and/or second wavelet in relation to the reference time is adjusted according to said time (ts) in relation to the reference time. An amplitude adjustment is not carried out.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 30, 2021
    Assignee: ELMOS SEMICONDUCTOR SE
    Inventors: Marco Liem, André Srowig
  • Patent number: 11042126
    Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 22, 2021
    Assignee: Huawei International Pte. Ltd.
    Inventors: Chao Yuan, Rui Yu, Xuesong Chen, Supeng Liu, Theng Tee Yeo
  • Patent number: 11029197
    Abstract: An optical sensor arrangement has an integrator, a photodiode for providing a current corresponding to a first polarity, a comparator coupled to the integrator for comparing a voltage with a threshold voltage to provide a comparison output, a reference charge circuit and a control unit. The reference charge circuit is coupled to the integrator for selectively providing first charge packages of a first size or second charge packages of a second size. The control unit is configured to control operation in a calibration phase, in an integration phase and in a residual measurement phase. During the calibration phase, the reference charge circuit provides one of the first charge packages and one or more of the second charge packages to the integrator until the comparison output changes. A reference number is determined corresponding to a number of the second charge packages provided.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 8, 2021
    Assignee: ams AG
    Inventors: Bernhard Greimel-Längauer, Peter Bliem
  • Patent number: 10979679
    Abstract: The vehicle accident recording system is configured for use with a vehicle. The vehicle further comprises a vehicle electric power source. The vehicle accident recording system comprises an acceleration sensor, a plurality of cameras, a control circuit, and a commercially provided and publically available cellular wireless network. The acceleration sensor detects the deceleration event. The plurality of cameras continuously captures video images of the area around the vehicle. The control circuit controls the operation of the vehicle accident recording system. The commercially provided and publically available cellular wireless network provides a communication link between the vehicle accident recording system and the appropriate authority. The vehicle accident recording system is isolated from the vehicle electric power source such that the vehicle accident recording system continues to operate in the event that the vehicle electric power source fails during the unfortunate incident.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 13, 2021
    Inventor: Jarvis Williams
  • Patent number: 10972118
    Abstract: A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 6, 2021
    Assignee: Silicon Laboratories Inc.
    Inventor: Obaida Mohammed Khaled Abu Hilal
  • Patent number: 10924129
    Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: February 16, 2021
    Assignee: MEDIATEK INC.
    Inventors: Su-Hao Wu, Chan-Hsiang Weng
  • Patent number: 10886847
    Abstract: Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for adjusting the output voltage.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: January 5, 2021
    Assignee: Arm Limited
    Inventors: Benoit Labbe, Graham Peter Knight, Philex Ming-Yan Fan
  • Patent number: 10788794
    Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Ofir Degani, Elan Banin, Eran Ben Ami
  • Patent number: 10715754
    Abstract: In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: July 14, 2020
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: John Kevin Moore, Neale Dutton
  • Patent number: 10671025
    Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 2, 2020
    Assignee: ams AG
    Inventors: Christian Mautner, Friedrich Bahnmueller, Friedrich Laengauer, Robert Kappel
  • Patent number: 10651868
    Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: May 12, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: Sri Ram Gupta
  • Patent number: 10388223
    Abstract: An electronic device includes display circuitry with a source amplifier and a data line that drives signals provided by the source amplifier. Additionally, the display circuitry includes pixels, where each pixel includes a diode, and a scan thin-film-transistor (TFT) that selectively couples the pixels with the data line, based upon a scan control signal. Sensing circuitry of the electronic device includes a capacitor that is electrically coupled to the data line, wherein the capacitor is pre-charged by the source amplifier when the scan TFT is OFF and a sensing amplifier electrically coupled to the data line, providing a sensing output of both a diode voltage of the one or more pixels and a driving current of the one or more pixels, depending on the current operation of the sensing circuitry. Further, conversion circuitry converts the sensing output from an analog domain to a digital domain.
    Type: Grant
    Filed: September 24, 2016
    Date of Patent: August 20, 2019
    Assignee: Apple Inc.
    Inventors: Kingsuk Brahma, Mohammad B. Vahid Far
  • Patent number: 10269417
    Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Gururaj K. Shamanna, Stefan Rusu, Eric A. Karl, Zheng Guo
  • Patent number: 10097200
    Abstract: A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by temporarily changing the sample rate to a temporary sample rate and then changing the sample rate back to the original sample rate. Synchronization in a reduced amount of time is achieved by determining the interval between the synchronization pulse and one of the output samples and determining a processing time of the device for generating the output samples at a new rate. The system calculates a temporary sample rate based on these calculations that tends to reduce an amount of time to achieve synchronization.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 9, 2018
    Assignee: Analog Devices Global
    Inventors: Miguel Usach Merino, Michael Hennessy, Anthony Evan O'Shaughnessy, Claire Croke
  • Patent number: 10097187
    Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 9, 2018
    Assignee: NXP USA, Inc.
    Inventors: Olivier Vincent Doare, Didier Salle, Birama Goumballa, Cristian Pavao Moreira
  • Patent number: 10084983
    Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: September 25, 2018
    Assignee: Fermi Research Alliance, LLC
    Inventors: Farah Fahim, Grzegorz Deptuch, Tom Zimmerman
  • Patent number: 10044264
    Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: August 7, 2018
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Bryan Kris, James Bartling
  • Patent number: 10032555
    Abstract: A current regulator for regulating alternating current (AC) flow to a load device is provided. The current regulator can include an AC coupling device that can be electrically connected to the load device via an output electrical path, a current control device electrically connected in series with the AC coupling device, and an AC feedback circuit electrically connected to the output electrical path and the current control device. The current control device can modify a current flow through at least one component of the AC coupling device in response to receiving an error correction current. An output AC current provided to the load device can be controlled based on the current flow through the component of the AC coupling device. The AC feedback circuit can include voltage error compensation device that provides the error correction current in response to receiving a feedback voltage corresponding to the output AC current.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: July 24, 2018
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Isaac Ng, Abdul Qadir Shabbir
  • Patent number: 9971312
    Abstract: Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: May 15, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Eskinder Hailu, Bupesh Pandita
  • Patent number: 9893632
    Abstract: An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes a voltage reduction circuit cell that includes a first capacitor, a second capacitor, a switching circuit, and a hold capacitor. The switching circuit includes a plurality of switching devices that are coupled to the first and the second capacitors for delivering power from an input terminal to an output terminal. The plurality of switching devices includes at least two switching devices that are coupled to ground. The voltage reduction circuit cell also includes a controller for operating the switching circuit in a plurality of operational modes to deliver an output power signal at a desired voltage level.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: February 13, 2018
    Assignee: Advanced Charging Technologies, LLC
    Inventors: Michael H. Freeman, W. J. “Jim” Weaver, Jr., Mitchael C. Freeman, Robert Dieter, Andrea Baschirotto, Piero Malcovati, Marco Grassi, Glenn Noufer, Randall L. Sandusky, Neaz E. Farooqi, Jim Devoy, Silvia Jaeckel, Madison Hayes Yarbro Freeman
  • Patent number: 9825754
    Abstract: A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: November 21, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Roshan Samuel
  • Patent number: 9791638
    Abstract: A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: October 17, 2017
    Inventor: David Schie
  • Patent number: 9780674
    Abstract: An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes a voltage reduction circuit cell that includes a first capacitor, a second capacitor, a switching circuit, and a hold capacitor. The switching circuit includes a plurality of switching devices that are coupled to the first and the second capacitors for delivering power from an input terminal to an output terminal. The plurality of switching devices includes at least two switching devices that are coupled to ground. The voltage reduction circuit cell also includes a controller for operating the switching circuit in a plurality of operational modes to deliver an output power signal at a desired voltage level.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 3, 2017
    Assignee: Advanced Charging Technologies, LLC
    Inventors: Michael H. Freeman, W. J. “Jim” Weaver, Jr., Mitchael C. Freeman, Robert Dieter, Andrea Baschirotto, Piero Malcovati, Marco Grassi, Glenn Noufer, Randall L. Sandusky, Neaz Farooqi, Jim Devoy, Silvia Jaeckel, Madison Hayes Yarbro Freeman
  • Patent number: 9405024
    Abstract: A radiation detector module for use in a time-of-flight positron emission tomography (TOF-PET) scanner generates a trigger signal indicative of a detected radiation event. A timing circuit including a first time-to-digital converter (TDC) and a second TDC is configured to output a corrected timestamp for the detected radiation event based on a first timestamp determined by the first TDC and a second timestamp determined by the second TDC. The first TDC is synchronized to a first reference clock signal and the second TDC is synchronized to a second reference clock signal, the first and second reference clock signals being asynchronous.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: August 2, 2016
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Thomas Frach, Gordian Prescher
  • Patent number: 9294114
    Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 22, 2016
    Assignee: OLYMPUS CORPORATION
    Inventor: Yoshio Hagihara
  • Patent number: 9287837
    Abstract: A sensor device is provided with a voltage detection type sensor unit for converting a physical quantity into a voltage value and outputting a voltage signal indicating the voltage value; a chopper amplifier unit for generating a modulation signal by chopping the voltage signal output from the sensor unit with a predetermined chopping frequency, amplifying the modulation signal into an amplification signal, then demodulating the amplification signal and outputting it as an output signal; an integration unit including an operational amplifier, an input resistor connected to the inverting input terminal of the operational amplifier and a capacitor connected between the inverting input terminal and an output terminal of the operational amplifier; and a digital conversion unit for converting the output signal integrated by the integration unit into a digital signal.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: March 15, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Choon How Lau, Minoru Kumahara
  • Patent number: 9170564
    Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 27, 2015
    Assignee: MegaChips Corporation
    Inventor: Hideyuki Sato
  • Patent number: 9171189
    Abstract: Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: October 27, 2015
    Assignee: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: Yannis Tsividis, Ning Guo
  • Patent number: 9141088
    Abstract: A time-to-digital converter adopted to transform an enabled time of a time signal into an output data and an operation method thereof are provided. The operation method includes the following steps: providing a counter clock signal by a digital phase locked loop according to a reference clock signal; providing a counter result by a counter unit according to the counter clock signal and the time signal; comparing the enabled time of the time signal with a minimum time to provide a comparison result by a comparator unit; and outputting the counter result as the output data according to the comparison result when the enabled time of the time signal is longer than the minimum time.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: September 22, 2015
    Assignee: Winbond Electronics Corp.
    Inventor: Chen-Yi Lee
  • Patent number: 9124280
    Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: September 1, 2015
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Yeomyung Kim, Tae Wook Kim
  • Patent number: 9106245
    Abstract: A method for interference suppression of a sampling process includes sampling an analog signal with a sampling frequency f, and determining whether an interference amplitude is present. The method provides that if an interference amplitude is present, the sampling frequency f is increased or decreased, and the method begins again with the sampling of the analog signal with the increased or decreased sampling frequency. In addition, a device is described for carrying out the method.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: August 11, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Thomas Wuchert, Matthias Kalisch
  • Patent number: 9100041
    Abstract: A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: August 4, 2015
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Justin Richardson, Mairead Kelly, Andrew Myles
  • Publication number: 20150145572
    Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: Hideyuki Sato
  • Patent number: 9035815
    Abstract: An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: May 19, 2015
    Assignee: XILINX, INC.
    Inventors: Donnacha Lowney, Aidan Keady, Christophe Erdmann
  • Patent number: 9019136
    Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 28, 2015
    Assignee: MediaTek Inc.
    Inventors: Chen-Yen Ho, Hung-Chieh Tsai, Yu-Hsin Lin
  • Patent number: 9019141
    Abstract: An imaging apparatus and a method of driving the same that can generate a digital data of a high resolution pixel signal are provided. The imaging apparatus includes: a pixel (10-1) for generating a signal by photoelectric conversion; a comparing circuit (30-1) for comparing a signal based on the pixel with a time-dependent reference signal; a counter circuit (40-1) performing a counting operating until an inversion of a magnitude relation between the signal based on the pixel and the time-dependent reference signal; and a selecting circuit (30-2) for setting a time-dependent change rate of the reference signal, according to a signal level of the signal based on the pixel.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 28, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hashimoto, Yasushi Matsuno
  • Patent number: 8994573
    Abstract: A digital-to-time converter (DTC) comprises a gate controller configured to generate a gate enable signal based on first and second digital values so that the gate enable signal has a first enable period and a second enable period for each pair of a first digital value and a second digital value. A gate conditionally passes a main clock signal to a gate output in response to the gate enable signal, the gate thus providing a gated signal at a gate output. A frequency divider generates a frequency divided signal as the output signal of the digital-to-time converter based on the gated signal. The DTC may be calibrated by a time-to-digital converter connected between an input for the main clock signal and an output of a delay element of the DTC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 31, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Stephan Henzler, Markus Schimper
  • Patent number: 8988269
    Abstract: A time difference adjustment circuit includes two flip-flop circuits, a delay circuit, and a reset circuit. The delay circuit includes first and second transistors of a first polarity and third and fourth transistors of a second polarity, wherein drains of the first and third transistors are coupled to each other, drains of the second and fourth transistors are coupled to each other, the drains of the first and third transistors and a gate of the fourth transistor are coupled to each other, an input signal is coupled to a gate of the first transistor, an output signal is supplied from the drains of the second and fourth transistors, and first and second reset signals are respectively coupled to gates of the second and third transistors.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: March 24, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Shiro Dosho
  • Patent number: 8988262
    Abstract: A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Miyashita
  • Patent number: 8981987
    Abstract: An imaging device includes a comparator that compares a noise signal with each of a first reference signal and a second reference signal having potentials with different changing quantities per unit time, and that compares a photoelectric conversion signal with each of the first reference signal and the second reference signal. Also, the imaging device AD-converts signals obtained by amplifying the noise signal by a first gain and a second gain having different gains, and AD-converts a signal obtained by amplifying the photoelectric conversion signal by one of a first gain and a second gain.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 17, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiji Hashimoto, Takashi Muto, Daisuke Yoshida, Hirofumi Totsuka, Yasushi Matsuno
  • Patent number: 8976052
    Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhance operation speed and reduced power consumption.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Min Kim, Kyoung-Min Koh, Yoon-Seok Han
  • Patent number: 8976054
    Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: March 10, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
  • Patent number: 8970421
    Abstract: Disclosed is a time-to-digital (TDC) converter comprising an analog voltage source. An analog-to-digital converter quantizes two voltage samples in response to receiving a first input signal at a first time t1 and a second input signal at a second time t2. The first and second digital signals are combined to produce a digital signal that represents the difference (t2?t1).
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: March 3, 2015
    Assignee: Marvell International Ltd.
    Inventors: Xiang Gao, Chih-Wei Yao, Chi-Hung Lin, Li Lin
  • Patent number: 8970420
    Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventors: Stephan Henzler, Markus Schimper, Stefan Tertinek
  • Patent number: 8969771
    Abstract: An imaging system includes an A/D converter including a holding unit holding a pixel signal as a voltage level, a comparator comparing the voltage level held with a reference level, a circuit capable of changing the voltage level so as to approach the reference level at first and second rates, wherein the voltage level is changed at the first rate to determine higher bits in accordance with inversion of a relationship between the reference level and the voltage level, after that, the voltage level is changed at the second rate to determine lower bits in accordance with inversion of the relationship between the reference level and the voltage level, and an adjusting unit which adjusts the voltage level during a period until the voltage level is changed at the second rate after determination of the higher bits so that the lower bits and the voltage level hold a linear relationship.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: March 3, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuji Ikeda, Hiroki Hiyama, Kazuo Yamazaki
  • Publication number: 20150054566
    Abstract: An electrical signal is processed by digitizing the electrical signal to produce a stream of digitized data in the time domain, wherein the stream has an original frequency spectrum, transmitting the stream to N signal paths (N>1), and down-converting and filtering the stream in each of the N signal paths to produce N streams of digitized data in the time domain, wherein the N streams have N frequency spectra, respectively, and the N frequency spectra cover N different portions of the original frequency spectrum, respectively.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 26, 2015
    Inventor: Robin A. Bordow
  • Publication number: 20150041625
    Abstract: A time to digital converter includes a sample module operable to sample an input signal at multiple different instances of time. A transition detection module, formed of comparison elements, processes the sampled input signal at successive time instances so as to detect transitions in the input signal in terms of time. An output module generates detected transitions in the input signal on multiple parallel outputs.
    Type: Application
    Filed: August 5, 2014
    Publication date: February 12, 2015
    Applicant: STMicroelectronics (Research & Development) Limited
    Inventors: Neale Dutton, Robert K. Henderson, Salvatore Gnecchi
  • Patent number: 8941524
    Abstract: A TD converter is provided for digitally converting a delay time value into a digital value. In the TD converter, an oscillator circuit part inputs time domain data. A first-state counter circuit part measures a number of waves of an output oscillation waveform from the oscillator circuit part when time domain data is in a first state, and a second-state counter circuit part measures a number of waves of the output oscillation waveform from the oscillator circuit part when the time domain data is in a second state. An output signal generator part generates an output signal based on output count values of the first-state counter circuit part and the second-state counter circuit part, and a frequency control circuit controls the oscillator circuit part to always oscillate and to control an oscillation frequency of the oscillator circuit part.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshihiro Konishi, Shintaro Izumi, Keisuke Okuno
  • Patent number: 8941526
    Abstract: A time integrator integrates time axis information represented by a phase difference between two signals. The time integrator includes a pulse generation circuit configured to convert a time difference between edges of two input signals to a difference between pulse widths of two pulse signals, and to output the two pulse signals, a load circuit having load characteristics changed by the two pulse signals, and an oscillation circuit coupled to the load circuit, and having an oscillation frequency changing in accordance with the load characteristics of the load circuit. An output of the oscillation circuit is output as a result of time integration.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 27, 2015
    Assignee: Panasonic Intellectual Property Management Co. Ltd.
    Inventors: Shiro Dosho, Masao Takayama, Takuji Miki
  • Publication number: 20150022385
    Abstract: Examples are provided for time-interleaved analog-to-digital conversion with redundancy. The redundancy may include high-order and nested redundancies. An apparatus may include multiple analog-to-digital converter (ADC) blocks coupled to one another to form a time-interleaved ADC. Each ADC block may include multiple ADC slices, wherein a count of the ADC blocks is M and some of the ADC slices may be redundant slices. A clock circuit may be configured to provide multiple clock signals. A portion N of M ADC blocks may be configured to be active, in a normal mode of operation, where N and M are integer numbers and N is smaller than M. A remaining portion of the M ADC blocks may be redundant ADC blocks, one or more of which may be selectively active, in a healing mode of operation, and be swapped for one or more failed ADC blocks using the plurality of clock signals.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 22, 2015
    Inventors: Sandeep Louis D'SOUZA, Krishna Shivaram, Craig Allison Hornbuckle