Abstract: A switched-capacitor amplifier comprises a comparator, sample and amplification capacitors and a controller to control charge and discharge current sources in dependence on an output signal of the comparator. A closed loop control circuit is configured to determine the delay of the comparator and control an offset of the comparator in response to the determined delay.

Abstract: Fast recovery electrocardiogram (ECG) signal method and apparatus are provided. In one embodiment, an ECG apparatus includes an input for receiving a biometric cardiogram signal, such as a Wilson Central Terminal (WCT) signal, and a combiner, such as an adder, for producing a compensated signal. Processing circuitry produces an ECG reflective of the compensated signal and also outputs a signal corresponding to high frequency response of the compensated signal to compensate for low response of the biometric cardiogram signal to high frequency spikes. A resultant ECG is produced by the processing circuitry having pacing signal contribution within the biometric cardiogram signal cancelled.

Abstract: An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.

Abstract: A round robin sensor device for processing sensor data is provided herein. The sensor device includes a multiplexer stage configured to sequentially select sensor outputs from one or more sensors continuously. Continuously and sequentially selecting sensor outputs results in a stream of selected sensor outputs. The sensor device also includes a charge-to-voltage converter operatively coupled to the multiplexer stage and configured to convert a charge from a first sensor of the one or more sensors to a voltage. Further, the sensor device includes a resettable integrator operatively coupled to the charge-to-voltage converter and configured to demodulate and integrate the voltage, resulting in an integrated voltage. Also included in the sensor device is an analog-to-digital converter operatively coupled to the resettable integrator and configured to digitize the integrated voltage to a digital code.

Abstract: The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period.

Abstract: A transition-state output device includes: a ring oscillator circuit; a state machine changing in state according to a change in state of the ring oscillator circuit; a transition-state acquisition section acquiring and holding state information including a signal output from the ring oscillator circuit and a signal output from the state machine, synchronously with a reference signal; and an internal-state calculation section calculating an internal state corresponding to a number of changes in state of the ring oscillator circuit, based on the state information held by the transition-state acquisition section. A time until the internal state, after transitioning from a first internal state to a second internal state, transitions to the first internal state again is longer than a time interval of updating the state information held by the transition-state acquisition section.

Abstract: A semiconductor device includes a clock terminal to and from which a clock is allowed to be input and output, and a data terminal to and from which data is allowed to be input and output. In the semiconductor device, the data synchronized with the clock that is input to the clock terminal or is output from the clock terminal is output from the data terminal, and when the clock is output from the clock terminal, the clock is output irrespective of whether or not data transfer of the data is being executed.

Abstract: The present application discloses an analog-to-digital converter capable of cancelling sampling noise, which comprises: a sampling circuit configured to acquire an analog input signal; a sampling noise cancelling circuit has an input end connected with an output end of the sampling circuit, and is configured to cancel noise generated by the sampling circuit; a comparator has an input end connected with an output end of the sampling noise cancelling circuit, and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of output signals of the sampling noise cancelling circuit and output a comparison result to the logic circuit; and the logic circuit has an output end connected with the sampling circuit, and is configured to output a digital output signal, and process the comparison result to obtain a control signal by which an output voltage of the sampling circuit is controlled.

Abstract: A self-calibration-function-equipped AD converter that does not require a measurement device for calibration includes: a control unit including a calibration control unit configured to control an operation of calibrating the self-calibration-function-equipped AD converter, and a conversion control unit configured to control an operation of converting an input voltage to be subjected to conversion into a digital signal; a reference voltage unit configured to output a reference voltage; and an integration/conversion unit including an integrating unit configured to generate an integration voltage obtained by integrating two or more types of unit voltages, a comparator that has two inputs and is configured to compare the integration voltage and the input voltage or the reference voltage, and a crossbar switch configured to switch a connection depending on whether the integration voltage is to be input to one input of the comparator and the input voltage or the reference voltage is to be input to another input, or

Abstract: A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.

Abstract: A device of detecting a current from a sensor is disclosed. The device includes an integrating circuit including a network of capacitors for providing a gain setting and configured to convert the current to a voltage ramp over a length of integration time, the integrating circuit further including a reset switch configured to connect an input and an output of the network of capacitors; an ADC configured to digitize the voltage ramp into a plurality of voltage samples; and a set of modules including an analyzing module configured to analyze the plurality of voltage samples to determine a slope of the voltage ramp; an outputting module configured to determine a magnitude of the current based on the slope of the voltage ramp and the gain setting; and a reconfiguring module that is configured to reconfigure the network of capacitors and reset the voltage ramp via the reset switch.

Abstract: A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.

Abstract: A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.

Abstract: A method adapts a resonant frequency of a first filter of a closed control loop to a given frequency. The method includes feeding an output signal of a delta sigma modulator of the closed control loop into a frequency adaptation circuit and determining a first noise spectrum of the output signal in a first frequency band and a second noise spectrum of the output signal in a second frequency band. The first frequency band and the second frequency band are arranged symmetrically with respect to the given frequency. The method includes comparing the first noise spectrum with the second noise spectrum, generating an adaptation signal that causes a frequency adaptation of the resonant frequency if the first noise spectrum differs from the second noise spectrum, and outputting the adaptation signal from the frequency adaptation circuit to a control input of the first filter for adapting the resonant frequency.

Abstract: An optical sensor arrangement comprises a photodiode and a converter arrangement including an integration amplifier, a comparator amplifier, an integration capacitor and a result register. During a precharge phase the result register is set to a starting value. During an integration phase a current is sampled through the photodiode to update the result register in response to down charges applied to an input of the integration amplifier. During a residue phase the result register is updated in dependence on the charge remaining on the integration capacitor. Measuring the residual charge increases resolution and accuracy of the converter.

Abstract: A variable output data rate converter circuit preferably meets performance requirements while keeping the circuit complexity low. In some embodiments, the converter circuit may include an oversampling sigma delta modulator circuit to quantize an analog input signal at an oversampled rate, and output an sigma delta modulated signal, a transposed polynomial decimator circuit to decimate the sigma delta modulated signal, and output a first decimated signal, and an integer decimator circuit to decimate the first decimated signal by an integer factor and output a second decimated signal having a desired output data rate. The transposed polynomial decimator circuit has a transposed polynomial filter circuit and a digital phase locked loop circuit, which tracks a ratio between a sampling rate of the first decimated signal and the oversampled rate, and outputs an intersample position parameter to the transposed polynomial filter circuit.

Abstract: The device executes a method for determining the delay time of a first wavelet in a transmission path (I1). For this purpose, the first wavelet is transmitted into the transmission path (I1) at a time after a reference time. After passing through the transmission path (I1), the delayed and typically deformed transmission wavelet is scalar-multiplied with a second (analysis) wavelet. The result is compared to a reference value. The scalar product value adopts the reference value at a time (ts). The delay of the first and/or second wavelet in relation to the reference time is adjusted according to said time (ts) in relation to the reference time. An amplitude adjustment is not carried out.

Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Abstract: An optical sensor arrangement has an integrator, a photodiode for providing a current corresponding to a first polarity, a comparator coupled to the integrator for comparing a voltage with a threshold voltage to provide a comparison output, a reference charge circuit and a control unit. The reference charge circuit is coupled to the integrator for selectively providing first charge packages of a first size or second charge packages of a second size. The control unit is configured to control operation in a calibration phase, in an integration phase and in a residual measurement phase. During the calibration phase, the reference charge circuit provides one of the first charge packages and one or more of the second charge packages to the integrator until the comparison output changes. A reference number is determined corresponding to a number of the second charge packages provided.

Abstract: The vehicle accident recording system is configured for use with a vehicle. The vehicle further comprises a vehicle electric power source. The vehicle accident recording system comprises an acceleration sensor, a plurality of cameras, a control circuit, and a commercially provided and publically available cellular wireless network. The acceleration sensor detects the deceleration event. The plurality of cameras continuously captures video images of the area around the vehicle. The control circuit controls the operation of the vehicle accident recording system. The commercially provided and publically available cellular wireless network provides a communication link between the vehicle accident recording system and the appropriate authority. The vehicle accident recording system is isolated from the vehicle electric power source such that the vehicle accident recording system continues to operate in the event that the vehicle electric power source fails during the unfortunate incident.

Abstract: A successive-approximation ADC includes an input capacitance coupled to a first node and configured to store a sampled input charge based on an input analog signal during a first phase of an analog-to-digital conversion. A gain tuning capacitance configured to store a first portion of the sampled input charge during a second phase of the analog-to-digital conversion. A charge-redistribution DAC includes a conversion capacitance configured to store a second portion of the sampled input charge during the second phase and configured to use the second portion, a remaining portion of the sampled input charge, and a reference voltage to provide an analog signal on the first node corresponding to a digital output code approximating the input analog signal at an end of the third phase. The gain tuning capacitance sequesters the first portion of the sampled input charge from the charge-redistribution DAC during the third phase.

Abstract: The present invention provides a time-interleaved analog-to-digital converter device, wherein the time-interleaved analog-to-digital converter device includes a random number generator, a plurality of ADCs and an output circuit. The random number generator is configured to generate a random number sequence. The plurality of ADCs are configured to receive an analog input signal to generate a plurality of digital signals, respectively, and each ADC is further configured to generate a selection signal according to the random number sequence. The output circuit is configured to select one of the digital signals according to the selection signals generated by the ADCs, to generate a digital output signal.

Abstract: Various implementations described herein are directed to a device having a voltage regulator that uses a modulator to adjust an output voltage. The device may include a time-to-digital converter that measures a timing delay of a logic chain, compares the timing delay to a reference delay to determine a timing delay error, and provides the timing delay error to the modulator for adjusting the output voltage.

Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Abstract: In an embodiment, a TDC includes: a clock input configured to receive a reference clock that is synchronized with a first event; a clock generation circuit configured to generate a first clock at a first output of the clock generation circuit based on the reference clock, the first clock having a second frequency lower than the reference clock; a data input configured to receive an input stream of pulses, where the input stream of pulses is based on the first event; a sampling circuit having an input register, the sampling circuit coupled to the data input, the sampling circuit configured to continuously sample the input stream of pulses into the input register based on the reference clock; and output terminals configured to stream time stamps based on the input stream of pulses at the second frequency, where the stream of time stamps is synchronized with the first clock.

Abstract: A time-to-digital converter arrangement has a ring oscillator with a plurality of inverting elements and a first and a second counter coupled to the ring oscillator. The first counter is configured to increment a first counter value if a positive edge transition is present at one of the inverting elements. The second counter is configured to increment a second counter value if a negative edge transition is present at the one of the inverting elements. A storage element stores the first and the second counter value and logical states of the plurality of inverting elements. A decoder coupled to the storage element selects one of the first and the second counter value as a valid value based on an evaluation of the stored logical states, and outputs a total counter value based on the valid value and the stored logical states.

Abstract: This application relates to modulators for providing time-encoded signals and in particular PWM signals. A modulator (200) has a first controlled oscillator (201P) configured to receive a first oscillator driving signal and output a first oscillation signal (S1). An accumulator (204) is configured to provide an accumulator value (VAL) based on a number of pulses of the first oscillation signal and a hysteretic comparator (205) alternates between first and second output states based on a hysteretic comparison of the accumulator value with a defined reference (REF). The first oscillator driving signal is based on a combination of an input signal and a feedback signal derived from an output of the hysteretic comparator.

Abstract: An electronic device includes display circuitry with a source amplifier and a data line that drives signals provided by the source amplifier. Additionally, the display circuitry includes pixels, where each pixel includes a diode, and a scan thin-film-transistor (TFT) that selectively couples the pixels with the data line, based upon a scan control signal. Sensing circuitry of the electronic device includes a capacitor that is electrically coupled to the data line, wherein the capacitor is pre-charged by the source amplifier when the scan TFT is OFF and a sensing amplifier electrically coupled to the data line, providing a sensing output of both a diode voltage of the one or more pixels and a driving current of the one or more pixels, depending on the current operation of the sensing circuitry. Further, conversion circuitry converts the sensing output from an analog domain to a digital domain.

Abstract: Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Abstract: A device having a sample-rate converter that may be programmed to generate samples at different rates is synchronized to an external synchronization pulse by temporarily changing the sample rate to a temporary sample rate and then changing the sample rate back to the original sample rate. Synchronization in a reduced amount of time is achieved by determining the interval between the synchronization pulse and one of the output samples and determining a processing time of the device for generating the output samples at a new rate. The system calculates a temporary sample rate based on these calculations that tends to reduce an amount of time to achieve synchronization.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal.

Abstract: A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

Abstract: The average of a complex waveform measured over a time period may be determined by first converting the complex waveform to a voltage, then converting this voltage to a current and using this current to charge a capacitor. At the end of the measurement time period the voltage charge (sample voltage) on the capacitor may be sampled by a sample and hold circuit associated with an analog-to-digital converter (ADC). Then the voltage charge on the sample capacitor may be removed, e.g., capacitor plates shorted by a dump switch in preparation for the next average of the complex waveform sample measurement cycle. The ADC then converts this sampled voltage charge to a digital representation thereof and a true average of the complex waveform may be determined, e.g., calculated therefrom in combination with the measurement time period.

Abstract: A current regulator for regulating alternating current (AC) flow to a load device is provided. The current regulator can include an AC coupling device that can be electrically connected to the load device via an output electrical path, a current control device electrically connected in series with the AC coupling device, and an AC feedback circuit electrically connected to the output electrical path and the current control device. The current control device can modify a current flow through at least one component of the AC coupling device in response to receiving an error correction current. An output AC current provided to the load device can be controlled based on the current flow through the component of the AC coupling device. The AC feedback circuit can include voltage error compensation device that provides the error correction current in response to receiving a feedback voltage corresponding to the output AC current.

Abstract: Aspects of the disclosure are directed to a pulse to digital converter. In accordance with one aspect, the pulse to digital converter includes an input to receive an input pulse signal; a fractional element, coupled to the input, wherein the fractional element generates a fractional pulse width measurement of the input pulse signal; and an integral element, coupled to the input, wherein the integral element generates an integral pulse width measurement of the input pulse signal, and wherein the fractional pulse width measurement and the integral pulse width measurement are concatenated as an output signal.

Abstract: An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes a voltage reduction circuit cell that includes a first capacitor, a second capacitor, a switching circuit, and a hold capacitor. The switching circuit includes a plurality of switching devices that are coupled to the first and the second capacitors for delivering power from an input terminal to an output terminal. The plurality of switching devices includes at least two switching devices that are coupled to ground. The voltage reduction circuit cell also includes a controller for operating the switching circuit in a plurality of operational modes to deliver an output power signal at a desired voltage level.

Abstract: A universal asynchronous receiver/transmitter (UART) module is disclosed. The UART module may include a receiver unit being clocked by a programmable receiver clock configured to sample an incoming data signal and comprising a counter clocked by said receiver clock, wherein the counter is reset to start counting with every falling edge of the data signal and to trigger a BRK detection signal if the counter reaches a programmable threshold value.

Abstract: A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit.

Abstract: An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes a voltage reduction circuit cell that includes a first capacitor, a second capacitor, a switching circuit, and a hold capacitor. The switching circuit includes a plurality of switching devices that are coupled to the first and the second capacitors for delivering power from an input terminal to an output terminal. The plurality of switching devices includes at least two switching devices that are coupled to ground. The voltage reduction circuit cell also includes a controller for operating the switching circuit in a plurality of operational modes to deliver an output power signal at a desired voltage level.

Abstract: A radiation detector module for use in a time-of-flight positron emission tomography (TOF-PET) scanner generates a trigger signal indicative of a detected radiation event. A timing circuit including a first time-to-digital converter (TDC) and a second TDC is configured to output a corrected timestamp for the detected radiation event based on a first timestamp determined by the first TDC and a second timestamp determined by the second TDC. The first TDC is synchronized to a first reference clock signal and the second TDC is synchronized to a second reference clock signal, the first and second reference clock signals being asynchronous.

Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.

Abstract: A sensor device is provided with a voltage detection type sensor unit for converting a physical quantity into a voltage value and outputting a voltage signal indicating the voltage value; a chopper amplifier unit for generating a modulation signal by chopping the voltage signal output from the sensor unit with a predetermined chopping frequency, amplifying the modulation signal into an amplification signal, then demodulating the amplification signal and outputting it as an output signal; an integration unit including an operational amplifier, an input resistor connected to the inverting input terminal of the operational amplifier and a capacitor connected between the inverting input terminal and an output terminal of the operational amplifier; and a digital conversion unit for converting the output signal integrated by the integration unit into a digital signal.

Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.

Abstract: Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter.

Abstract: A time-to-digital converter adopted to transform an enabled time of a time signal into an output data and an operation method thereof are provided. The operation method includes the following steps: providing a counter clock signal by a digital phase locked loop according to a reference clock signal; providing a counter result by a counter unit according to the counter clock signal and the time signal; comparing the enabled time of the time signal with a minimum time to provide a comparison result by a comparator unit; and outputting the counter result as the output data according to the comparison result when the enabled time of the time signal is longer than the minimum time.

Abstract: A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

Abstract: A method for interference suppression of a sampling process includes sampling an analog signal with a sampling frequency f, and determining whether an interference amplitude is present. The method provides that if an interference amplitude is present, the sampling frequency f is increased or decreased, and the method begins again with the sampling of the analog signal with the increased or decreased sampling frequency. In addition, a device is described for carrying out the method.

Abstract: A capacitance reduction circuit retains a conversion digital code of a previous sampling of an input signal of a delta-sigma modulated ADC and compares a set of least significant data bits and most significant bits of the conversion digital code to a least significant and a most significant boundary codes. When the least significant bits of the conversion digital code are less than or equal to the least significant boundary code or when the most significant bits of the conversion digital code are greater than or equal to the most significant boundary code, the capacitance reduction circuitry generates a capacitance reduction enable/disable code applied to multiple summation-quantization circuits to enable or disable groups of the multiple summation-quantization circuits bits to reduce capacitive loading of the outputs of delta-sigma modulator and an input signal to improve the total harmonic distortion and noise.

Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.

Abstract: An apparatus relating generally to signal analysis is disclosed. In such an apparatus, a first comparator is coupled to receive a signal input and a first input level. A second comparator is coupled to receive the signal input and a second input level different from the first input level. A time-to-digital converter is coupled at a first port thereof, such as a start port for example, to receive a first output from the first comparator and coupled at a second port thereof, such as a stop port for example, to receive a second output from the second comparator. The time-to-digital converter is coupled to provide digital words representing the signal input.