Abstract: One or more techniques and/or systems described herein implement, among other things, a parabolic curve for a ramp signal in a data acquisition component, where the curve can be effectively calibrated and used to provide a settling period to mitigate noise. That is, a ramp generator can generate a ramp signal that has a parabolic voltage curve with two substantially mirroring halves. A comparator can compare a first portion of the parabolic voltage curve with a voltage signal indicative of a number of photons detected by a detection array. A second portion of the parabolic voltage curve is used as a temporal delay so that circuitry, such as the ramp generator, can settle.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.

Abstract: Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: Disclosed are a ramp signal generator and an image sensor. The ramp signal generator includes: a comparator comparing a first bias voltage input to a first input terminal and a second bias voltage input to a second input terminal and outputting a ramp signal from an output terminal; a ramp signal adjustment unit including a plurality of switched capacitors made up of switches and capacitors connected in series, and connected in parallel between a first input terminal of the comparator and an output terminal of the comparator; and a controller switching the switches of the plurality of switched capacitors to adjust the ramp signal output from the comparator such that the ramp signal becomes nonlinear over time.

Abstract: A method is provided. An analog signal is received. The analog input signal is compared to first and second reference signals to generate a first comparison result, and the first comparison result and a first time stamp corresponding to the first comparison result are registered. A first portion of a digital signal is generated from the first comparison result. At least one of the first and second reference signals is adjusted. A second comparison result is generated if the analog signal reaches an adjusted one of the first and second reference signals within a predetermined interval, and a second portion of the digital signal is generated from the second comparison result.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: A regular expression pattern matching circuit based on a pipeline architecture is proposed, which is designed for integration to a data processing system, such as a computer platform, a firewall, or a network intrusion detention system (NIDS), for checking whether an input code sequence (such as a network data packet) is matched to specific patterns predefined by regular expressions. The proposed circuit architecture includes an incremental improvement on an old combination of a comparator circuit module and an NDFA (non-deterministic finite-state automata) circuit module, where the incremental improvement comprises a data signal delay circuit module installed to the comparator circuit module and an enable signal delay circuit module installed to the NDFA circuit module to thereby constitute a multi-sage pipeline architecture that allows a faster processing speed than the prior art.

Abstract: There is a need to provide an AD converter capable of reducing occurrence of a noise. An AD converter includes an operational amplifier and a clip circuit. The operational amplifier receives ramp voltage and voltage for an analog signal and allows output terminal voltage to transition from an H level to an L level when a change in the ramp voltage reaches the voltage for the analog signal. The clip circuit fixes an output terminal of the operational amplifier to clipping voltage after output voltage for the operational amplifier reaches threshold voltage for a latch circuit. Therefore, the AD converter can limit a range of output voltage, as a source of noise, for the operational amplifier and eliminate an unnecessary change in the output voltage after the threshold voltage for the latch circuit is reached.

Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.

Abstract: An analog to digital converter (ADC) includes a clock control unit supplying a predetermined clock signal corresponding to luminance among a plurality of clock signals having different frequencies; and a signal conversion unit comparing a ramp signal with an inputted pixel signal to generate a comparison result signal. The ADC performs counting corresponding to the predetermined clock signal supplied by the clock control unit and stores a count value counted at a time of the generating of the comparison result signal.

Abstract: A tag communication apparatus conducts wireless communication with an RFID tag through a radio wave. The tag communication apparatus includes a data receiver that receives transmit data to be transmitted to the RFID tag, a data compressor that compresses at least a part of the transmit data obtained by the data receiver, and outputs the compressed data, and a transmitter that transmits the compressed data, which is compressed and output by the data compressor, to the RFID tag.

Abstract: An analog-to-digital converter including a comparator configured to compare a pixel signal received at a first input terminal of the comparator with a ramp signal received at a second input terminal of the comparator and generate a comparison signal as a result of the comparison; and a ramp signal supply circuit configured to provide the ramp signal to the comparator, wherein the ramp signal supply circuit generates a first signal as part of the ramp signal in response to the comparison signal and a first clock signal being received at the ramp signal supply circuit, wherein a slope of the first signal sequentially changes until the comparison signal makes a transition from one logic level to another and, after the transition, the ramp signal supply circuit generates a second signal as part of the ramp signal, wherein a slope of the second signal sequentially changes, wherein the slope of the second signal is opposite the slope of the first signal.

Abstract: An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.

Abstract: System and method for digitizing analog voltage signals. A first voltage signal may be received at a comparator. A ramp signal may be received at the comparator. The ramp signal may be generated by a ramp generator. An output signal may be generated by the comparator. The output signal may indicate whether the analog voltage signal or the ramp signal is greater. The output signal may be conveyed to logic circuitry by the comparator. Control information may be conveyed by the logic circuitry to the ramp generator. The ramp generator may generate the ramp signal based on the control information. The logic circuitry may determine a digital representation of the first voltage signal based on the output signal from the comparator and the control information.

Abstract: A ramp wave output circuit includes a ramp wave generation circuit generating a ramp wave, and a low-pass filter having a variable cutoff frequency, which receives the ramp wave. The low-pass filter operates at a first cutoff frequency for a predetermined time period after the receipt of the ramp wave, and at a second cutoff frequency, which is larger than the first cutoff frequency, after the predetermined time period has passed.

Abstract: A method of analog to digital voltage conversion including: generating a quadratic signal based on an analog time varying reference signal; generating a ramp signal based on the quadratic signal; and converting an analog input voltage to a digital output value based on a time duration determined by a comparison of the analog input voltage with the ramp signal.

Abstract: Systems, methods, and devices for obtaining data from a data location. The method may include generating a first value by sensing a data location under a first condition and generating a second value by sensing the data location under a second condition. The method may further include combining the first value with the second value to identify data conveyed by the data location.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: It is an object of the present invention to provide a solid-state imaging device for enhancing accuracy of AD conversion and active switching of up-counting and down-counting in the asynchronous counter without limiting the AD conversion frequency. The solid-state imaging device according to the present invention includes an asynchronous counter having an up-counting mode in which up-counting is performed, a down-counting mode in which down-counting is performed, and a holding mode for switching operation settings between the up-counting and the down-counting while maintaining a count value held in the asynchronous counter.

Abstract: The circuit includes, upstream from a PWM quantizer, that is between the output of the sigma-delta modulator and the input of the PWM or PWM-like quantizer, a second or ancillary sigma-delta stage of any order and architecture, with the function of controlling the minimum dynamic of the sigma-delta modulator. This second sigma-delta stage is input with the output signal of the sigma-delta modulator summed to a signal corresponding to the difference between the input signal and the output signal of the second sigma-delta stage, delayed by a delay block.

Abstract: Dual ramp analog-to-digital converters and methods allow for performing analog-to-digital conversion of an analog signal. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal and a coarse ramp to a same input of a comparator, and applying a fine ramp to another input of the comparator. Some dual ramp analog-to-digital converters and methods allow for applying the analog signal, a coarse ramp, and a fine ramp to a same input of a comparator. Various dual ramp analog-to-digital converters and methods allow for applying the analog signal to an input of a first comparator, applying a coarse ramp to the input of the first comparator through a coarse ramp switch, applying the analog signal to an input of a second comparator, and applying a fine ramp to another input of the second comparator.

Abstract: The invention relates to a method for the digital transmission of an analogue measuring signal (M), comprising the following steps: comparing momentary values of a triangular signal (D) with a value of the measuring signal (M) for generating a binary measurement pulse (PM); comparing momentary values of the triangular signal (D) with a predeterminable first reference variable (R1) for generating a binary reference pulse (PR) that corresponds to the measurement pulse (PM) and transmitting the measurement pulse (PM) and reference pulse (PR) at a constant phase.

Abstract: In a cable return path system, a method for performing digital companding adds a predetermined offset to the digital value to be companded, and employs a modified ?-law or a-law companding technique to obtain a reduced bit length digital value. One embodiment of this modified approach adds a predetermined offset (e.g., 129 for a 12-bit implementation) to the digital value before companding and then employs a two-bit chord and a 5-bit step for the 12-bit implementation. The end result is that the performance metrics are not significantly compromised by this bit reduction when compared to current transmission methods without this technique.

Abstract: An analog to digital converter (ADC) includes a digital ramp generator, an analog voltage comparator, a digital to analog converter (DAC) and a data storage device. The digital ramp generator includes first and second counters. The counter outputs an incremental code to a second counter so that the output code of the second counter varies by the incremental code. The second counter outputs a digital ramp code to respective inputs of the DAC and the data storage device. The DAC outputs an analog voltage to an input of the analog voltage comparator which switches logic states when the output analog voltage of the DAC equals an input voltage received at the analog voltage comparator. The data storage device stores a code of the digital ramp code received at the data storage device at the switching of the logic state of the analog voltage comparator. The first counter varies the incremental code by an incremental step in response to a clock signal.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: An A/D converter suitable for use in a system in which the signal power of noise increases with the signal power of the signal, such as an imaging system, utilizes a variable quantization system for converting analog signals into digital signals. The variable quantization is controlled so that at low signal levels the quantization is similar or identical to conventional A/D converters, while the quantization level is increased at higher signal levels. Thus, higher resolution is provided at low signal levels while lower resolution is produced at high signal levels.

Abstract: An image sensor comprises an active pixel sensor (APS) array, a first analog-to-digital converter (ADC), and a ramp signal generator. The APS array has includes a plurality of pixels of arranged in a second order two-dimensional matrix, and wherein the APS array generates a reset signal and an image signal for each pixel of selected columns. The first ADC has includes correlated double sampling (CDS) circuits for each column of the APS array, and wherein the first ADC generates a digital code corresponding to the difference between the reset signal and the image signal using an output ramp signal that is applied to the CDS circuits for each column. The ramp generator generates the output ramp signal in which a low illumination portion and a high illumination portion have different slopes.

Abstract: The signal processing system includes a pulse width modulator (PWM) that receives input signals from a delta sigma modulator. The PWM generates an output signal having successive frames of PWM patterns. Modifying loop filter data, such as a loop filter output signal, of the delta sigma modulator modifies a delta-sigma modulator quantizer output signal, which in turn changes the frame-to-frame duty cycles of the pulse width modulator output. PWM patterns corresponding to substantially similar delta sigma modulator input signal levels have substantially identical pulse widths. The signal processing system shifts rising and falling edges of pulse width modulator output signals relative to pulse width modulated signals generated from unmodified signals by a quanta of time greater than any deviation between the pulse widths. The signal processing system shifts pulse edges of PWM patterns to spread the spectrum of intra-channel and inter-channel harmonic frequencies.

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

Abstract: In an aspect of the present invention, methods and systems for providing an input device are disclosed. In an aspect of the present invention, the input device includes a symbol and a UV light source is provided to direct UV light on the symbol. The symbol includes an UV excitable compound. In an aspect of the invention, the UV light from the UV light source is directed onto the symbol with a light pipe. In operation, the UV light causes the symbol to glow so that the symbol is visible in a darkened environment.

Abstract: The present invention provides for background calibration of a time-interleaved analog-to-digital converter (TIADC). In one embodiment, a background calibrator includes a TIADC having a parallel array of time-interleaved main signal processors, each main signal processor including an ADC connected to a corresponding output FIR filter. The background calibrator also includes an auxiliary signal processor having an ADC connected to at least one corresponding output FIR filter. Additionally, the background calibrator further includes a timing calibration circuit, wherein the timing calibration circuit is configured to select one of the main signal processors, exchange the auxiliary signal processor with the selected main signal processor in the TIADC and connect the selected main signal processor to the timing calibration circuit. In an alternative embodiment, the timing calibration circuit is further configured to reduce a timing mismatch of the selected main signal processor.

Abstract: An amplified reading device includes an adjustable gain amplifier AMP receiving analog information and of which 2j successive gain values, respectively adjustable by 2j successive values of a first control word of j bits, follow a geometric progression of ratio a; an analog/digital converter CAN connected to the output of the amplifier, having an adjustable input full scale, of which 2k different values, respectively adjustable, for each gain value, from 2k successive values of a second control word of k bits, follow a geometric progression of ratio a1/2 k, the converter delivering a digital code corresponding to the analog information amplified by an overall gain, the value of which depends on the gain value of the amplifier and on that of the full scale, and a controller MCM designed to deliver the first and second control words.

Abstract: A transmission line analog-to-digital converter uses an unterminated transmission line driven by a current source to generate a stair-step waveform having equal time step periods for measuring the conversion time as a digital output value of an analog input. The converter has the advantages of simplicity, accuracy, high speed, low transistor count, and low power consumption. Fast successive approximation converters can be used for improved speed and accuracy of digital conversion of analog signals.

Abstract: A ramp generator includes an array of capacitors having a common top plate that provides a ramp output signal. Each of the capacitors has a bottom plate switched sequentially between a low reference voltage and a high reference voltage in response to a value in a shift register. For an upward ramp, capacitors can be switched to their high reference voltages in succession, increasing the output voltage on the common top plate; for a downward ramp, capacitors can be switched to their low reference voltages in succession, decreasing the output voltage. The capacitors can be switched by a multi-bit shift register, each bit of which controls one capacitor's voltage. Each time a clock signal is applied to the shift register, a value in the shift register shifts another capacitor between its low and high reference voltages.

Abstract: A comparator for an analog-to-digital converter comprises an input stage (in+, in−, M1, M2) for receiving an input signal; a bipolar latch stage (Q1, Q2; Q1a-b, Q2a-b) coupled to the input stage for performing a latch decision based on the input signal; means for amplifying the latch output (Va, Vb) to a level suitable for CMOS circuitry; and an output (out+, out−). The means for amplifying includes at least one tapping transistor (Q3, Q4) coupled to the latch stage for, depending on the latch decision, tapping a collector current (Ic2; Ic1) from the latch stage, while leaving the latch decision thereof unaffected, such that a current gain (&bgr;) of the latch stage can be used to amplify a latch bias current (Ia, Ib) of the latch stage to thereby provide for the amplification.

Abstract: A range recognizer applies acquired data to the inputs of a plurality of boundary comparators simultaneously, treating an entire range of values for the data as a single continuum which is partitioned by a series of internal boundaries that are monitonically increasing. Each boundary comparator compares the value of the data with its unique boundary value and provides the results to a single range encoder logic to generate a single binary word as an encoded result indicative of the comparison for the entire range. An upper boundary result of one boundary comparator is combined with a lower boundary result of an adjacent higher boundary comparator prior to input to the single range encoder logic. The result is a reduction In the number of output pins required on an integrated circuit (IC) for reporting the encoded result for a corresponding plurality of range recognizers.

Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.

Abstract: An analog-to-digital converter is provided for converting an analog signal to a one-bit digital bit stream. The A/D converter uses a multi-bit analog delta-sigma modulator coupled to receive the analog input signal, and a one-bit digital delta-sigma modulator coupled to receive the digital output from the multi-bit analog delta-sigma modulator. The analog delta-sigma modulator uses a multi-bit quantizer having minimal quantization noise, and the digital delta-sigma modulator converts the multi-bit quantizer output into a single bit delta-sigma digital format compatible with digital audio systems which require a one-bit delta-sigma format. Thus, the present A/D converter uses the benefits of a multi-bit quantizer, yet can produce a one-bit, delta-sigma modulator output. In addition to linking with the one-bit delta-sigma modulator, the multi-bit quantizer output can be fed directly into a digital audio system which uses a multi-bit encoded delta-sigma or PCM format.

Abstract: An analog/digital converter including an amplifier (1) wired as an integrator, a comparator (2) electrically downstream from the integrator, a time counter (6) which continually counts the pulses of a pulse generator (5), a bistable element (4), and additional circuitry. The bistable element (4) drives the input network of the amplifier (1) with at least one switch (3) in such a way that in one of its two positions (“off” condition) a current Ix proportional to the analog measured value is integrated, and in the other position (“on” condition) a constant reference current Iref with opposite polarity to the current Ix is integrated in addition to current Ix.

Abstract: A/D conversion of a current input is performed with integrate-and-fire spiking neurons. Techniques that upcount or downcount the number of spikes fired by one neuron in a time period established by another neuron yield quantized estimates of analog charge residues created by the input current. Recursive application of alternate upcounting and downcounting operations yields successively finer quantization estimates that are terminated by an error-correction operation to obtain the least significant bit of the conversion. A spike-based hybrid state machine (HSM) employing both analog and digital elements is configured to create a 2-step or a successive-subranging analog-to-digital converter. The speed of the conversion is augmented in a pipelined topology. In the HSM, a spike-triggered finite state machine (FSM) controls the input currents to the spiking neurons and is in turn controlled by spikes arising from these neurons.

Abstract: A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

Abstract: In a measurement device, a detector output signal indicative of a condition magnitude, e.g., radiation, pressure, temperature, etc, and a ramp signal are added, and the resulting analog summation signal is converted to a digital signal. The digital signal is sampled, integrated, and averaged over a sampling time corresponding to a predetermined sampling number, such as to achieve a condition measurement signal having reduced analog-digital conversion error.

Abstract: An apparatus for applying a curve transfer function to an input signal comprises a first set of memory for storing values representing boundary points or distance differences along a curve of the transfer function, a second set of memory for storing slope values of lines connecting adjacent boundary points along the curve, a counter unit for maintaining a position count indicating position along the curve of the transfer function with respect to the stored boundary point values, an addressing unit, responsive to the position count, for selecting, from the second set of memory memory, the slope value corresponding to the position count, an accumulator for adding the selected slope value to an accumulator output value; and a comparator and data latch for determining when the accumulator output value corresponds to the input signal, and for selecting the corresponding accumulator output value as an output signal representing the application of the curve transfer function to the input signal.