Using Charge Transfer Devices (e.g., Charge Coupled Devices, Charge Transfer By Switched Capacitances) Patents (Class 341/172)
  • Patent number: 10878858
    Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroyuki Matsuno, Shuichi Tsukada
  • Patent number: 10819363
    Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 10785435
    Abstract: An imaging system includes: an imaging device and a processing device mounted in a vehicle. The imaging device includes: a first pixel coupled to a first signal line, a second pixel coupled to a second signal line, the second signal line is different from the first signal line, a first latch that is coupled to the first signal line, and stores a first digital code, a second latch that is coupled to the second signal line, is adjacent to the first latch, and stores a second digital code, a transfer section that transfers digital codes outputted from the first latch and the second latch, and a diagnosis section that performs diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. The processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Naoki Kawazu, Atsushi Suzuki, Junichiro Azami, Yuichi Motohashi
  • Patent number: 10784883
    Abstract: In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 22, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Prateek Tripathi, Behzad Sheikholeslami, Marceline Kelly Tchambake Yapti
  • Patent number: 10778921
    Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yutaka Abe, Kazuko Nishimura, Hiroshi Fujinaka, Masahiro Higuchi, Dai Ichiryu
  • Patent number: 10732577
    Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 4, 2020
    Assignee: NXP B.V.
    Inventors: Hao Fan, Michiel Pertijs, Berry Anthony Johannus Buter
  • Patent number: 10727856
    Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 28, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Hui Wu, Jie-Fan Lai, Shih-Hsiung Huang
  • Patent number: 10720831
    Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Schaef, Vaibhav Vaidya, Suhwan Kim
  • Patent number: 10707887
    Abstract: The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Wen-Chi Wang
  • Patent number: 10615812
    Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 7, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Sandeep Monangi, Mahesh Madhavan
  • Patent number: 10516479
    Abstract: A remote node includes a first node input, a second node input, and an optical switch. The optical switch includes a first switch input optically coupled to the first node input, a second switch input optically coupled to the second node input, a first switch output switchably coupled to the first switch input or the second switch input, and a second switch output switchably coupled to the first switch input or the second switch input. The remote node includes a photodiode optically coupled to the second switch output, and a capacitor electrically coupled to the photodiode and the optical switch. When the first switch input is switchably coupled to the first switch output, the second switch input is switchably coupled to the second switch output. Light received by the second switch input passes out the second switch output to the photodiode. The photodiode charges the capacitor to a threshold charge.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 24, 2019
    Assignee: Google LLC
    Inventors: Liang Du, Yut Loy Chan, Xiangjun Zhao, Changhong Joy Jiang, Cedric Fung Lam, Daoyi Wang, Tao Zhang
  • Patent number: 10504405
    Abstract: A display device is disclosed. The display device includes a display panel including data lines, panel lines, scan lines, and pixels, a power circuit configured to output a reference voltage for initializing subpixels of the pixels, a plurality of branch lines configured to divide a path of the reference voltage into a plurality of paths, and a switch circuit configured to switch a path between the branch lines and the panel lines in response to a switch control signal. The switch circuit changes the path between the branch lines and the panel lines at intervals of predetermined time.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 10, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Hanjin Bae, Sangho Yu
  • Patent number: 10461762
    Abstract: Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Meysam Zargham, Yan Wang, Li Lu, Dinesh Jagannath Alladi
  • Patent number: 10382053
    Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 13, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Shuo Fan
  • Patent number: 10326464
    Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Christopher Rogi, Richard Gaggl, Enrique Prefasi
  • Patent number: 10164651
    Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 25, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Kenta Aruga, Yasuhiro Mizuno, Masato Yoshioka
  • Patent number: 10075177
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto
  • Patent number: 9998137
    Abstract: An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 12, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiang Li, Arvind Anumula Paramanandam, Prasanna Upadhyaya, Xiaoyue Wang
  • Patent number: 9960781
    Abstract: A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 1, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Wenlu Chen, Han Chi Hsieh, Raymond Zanoni
  • Patent number: 9843340
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: December 12, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto
  • Patent number: 9702891
    Abstract: An analogue amplification device comprises a first stage with a common base or gate transistor that receives the modulated input current on its emitter or its source and the output signal of this first stage corresponds to the signal of the collector, a second stage formed by a follower amplifier comprising a transistor with a common collector or drain setup, a third stage that comprises a transistor with a common emitter setup, and a fourth stage that is an amplifying stage with means allowing the realization of, on the one hand, an amplification, and on the other hand, a matching of impedance. The device can be applied to a laser anemometer with optical retro-injection.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 11, 2017
    Assignees: EPSILINE, INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE
    Inventors: Francis Bony, Raphael Teysseyre
  • Patent number: 9692437
    Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 27, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-deuk Jeon, Min-Hyung Cho, Yi-Gyeong Kim, Chun-Gi Lyuh
  • Patent number: 9554072
    Abstract: The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: January 24, 2017
    Assignee: Innovaciones Microelectrónicas S.L.
    Inventors: Fernando Medeiro Hidalgo, Rafael Domínguez Castro
  • Patent number: 9509926
    Abstract: A photoelectric conversion device includes analog signal output units including pixels and configured to output analog signals based on pixels, and signal processing units. Each of the signal processing units is provided correspondingly to one of the analog signal output units and including a gain application unit configured to apply a gain to an analog signal by using only passive elements and an AD conversion unit. In the gain application unit, a portion that contributes to application of a gain to the analog signal is constituted only of passive elements. The gain application unit selectively outputs a first amplified signal obtained by applying a first gain to the analog signal or a second amplified signal obtained by applying a second gain to the analog signal smaller than the first gain. The AD conversion unit converts, from analog to digital, the first or second amplified signal.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: November 29, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takashi Muto, Takeru Suzuki, Yasushi Matsuno, Daisuke Yoshida
  • Patent number: 9496888
    Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Sunny Sharma, Chin Yeong Koh, Samaksh Sinha
  • Patent number: 9413379
    Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: August 9, 2016
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Yun-Jung Kim, Jong-Boo Kim, Oh-Kyong Kwon
  • Patent number: 9300314
    Abstract: An arrangement for reading out an analog voltage signal includes a voltage signal input for applying the analog voltage signal thereto, a reference unit configured to generate an analog reference voltage, and a converting unit configured to convert an analog input signal into a digital output signal. To enable online self-calibration of the arrangement, the arrangement includes a superposition unit configured to receive the analog voltage signal and the analog reference voltage. The superposition unit includes a modulation unit configured to generate a modulated reference voltage from the analog reference voltage. The superposition unit is configured to generate a combined analog signal by superimposing the modulated reference voltage onto the analog voltage signal, and to forward the combined analog signal to the converting unit.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 29, 2016
    Assignee: ABB TECHNOLOGY AG
    Inventors: Joris Pascal, Richard Bloch
  • Patent number: 9287888
    Abstract: A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: March 15, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ming-Cheng Chiang, Wei-Cheng Tang
  • Patent number: 9219492
    Abstract: A multi-stage Successive-Approximation Register (SAR) pipeline Analog-to-Digital Converter (ADC) has an amplifier between two switched capacitor networks, each controlled by a SAR. The load capacitance of the amplifier is magnified due to the amplifier's gain. This magnified load capacitance can disproportionately increase power consumption. The back plates of the second-stage switched capacitors are connected to the amplifier input using a feedback switch during an amplification phase, so that the second-stage switched capacitors are connected between the input and output of the amplifier as a feedback capacitor, rather than a load capacitor. Reset switches are added to drive both plates of the second-stage switched capacitors to ground during a reset phase before the amplification phase. Thus the second-stage switched capacitors function as both the feedback capacitor and as the switched capacitors controlled by the second SAR.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 22, 2015
    Assignee: Hong Kong Applied Science & Technology Research Institute Company, Limited
    Inventors: Chi Fung Lok, Shiyuan Zheng
  • Patent number: 9178522
    Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 3, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Emanuele Bodano, Peter Bogner, Joachim Pichler, Mark Schauer
  • Patent number: 9154150
    Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N?2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N?2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Jiangfeng Wu, Wei-Te Chou, Rong Wu
  • Patent number: 9153297
    Abstract: An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 6, 2015
    Assignee: Infineon Technologies AG
    Inventors: Kazimierz Szczypinski, Wen-Ming Lee
  • Patent number: 9148603
    Abstract: An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 29, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ashirwad Bahukhandi, Taehee Cho, Nikolai Bock
  • Patent number: 9143144
    Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: September 22, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
  • Patent number: 9136867
    Abstract: The present invention relates to a delta-sigma-modulator and a delta-sigma-A/D converter. By speeding up the settling time constant of an integrator at the last stage with a simple configuration, the sampling frequency is sped up in the delta-sigma-modulator as a whole. Specifically, in the delta-sigma-modulator including multiple integrators connected in cascade, the integrator positioned at the last stage is a passive integrator not using an amplifier circuit, and one or more integrators positioned at stages preceding the last stage by one or more stages are active SC integrators using amplifier circuits and switched capacitor circuits, respectively. Also, each of the integrators performs integral calculation by alternately repeating a first operation phase to charge a sampling capacitor by sampling an input signal, and a second operation phase to perform a summing integration by transferring an electric charge charged in the sampling capacitor to an integration capacitor.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: September 15, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hikaru Watanabe
  • Patent number: 9136863
    Abstract: The present invention discloses a successive approximation analog-to-digital converter, comprising: a capacitor array including a designated capacitor and several sampling capacitors to sample an input signal under a sampling mode; a comparator to compare a first voltage from the capacitor array with a second voltage under a comparison mode and thereby generate a comparison result; a switching circuit to determine the charge amount stored in the capacitor array under the sampling mode and the first voltage under the comparison mode according to a control signal; and a control circuit to generate the control signal according to a sampling setting under the sampling mode and generate the control signal according to the comparison result under the comparison mode. Said designated capacitor does no sampling under the sampling mode, but appropriates the charges of the sampling capacitors under the comparison mode, so as to reduce the effective sampling value.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 15, 2015
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Sheng-Hsiung Lin
  • Patent number: 9100034
    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 4, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
  • Patent number: 9083375
    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator coupled to receive a sampled input voltage; a pair of arrays each including individually switchable binary-weighted capacitors that are switchably coupled to an output of the comparator via phase switches, respectively. A phase signal for controlling a corresponding phase switch associated with a current bit becomes asserted when a preceding bit finishes comparison, and the phase signal becomes de-asserted when the current bit finishes comparison.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: July 14, 2015
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Soon-Jyh Chang, Che-Hsun Kuo, Chung-Ming Huang
  • Patent number: 9083345
    Abstract: A circuit arrangement for determining a capacitance of a number n of capacitive sensor elements (SE1˜SEn) comprises at least one collecting capacitor (CS1˜CSm), a reference voltage source (RQ), an evaluation device (AE) connected to the at least one collecting capacitor to evaluate a voltage present at the at least one collecting capacitor, a control unit (MC) for generating at least one control signal (SS1˜SSk), and at least one integrated circuit (IC1˜ICm) connected to the reference voltage source, the sensor elements, and the at least one collecting capacitor. The at least one integrated circuit comprises a number k of changeover switches (WS1˜WSk) responsive to the at least one control signal to connect the respectively associated sensor element to the reference voltage source in a first switching position, and to the at least one collecting capacitor in a second switching position.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 14, 2015
    Assignee: E.G.O. Elektro-Gerätebau GmbH
    Inventor: Randolf Kraus
  • Patent number: 9077355
    Abstract: A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 7, 2015
    Assignee: Broadcom Corporation
    Inventor: Frank Maria Leonardus van der Goes
  • Patent number: 9077359
    Abstract: A method, comprising: selecting two Two-Tuples before and two after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time differences between each of the asynchronous samples surrounding the selected sample, and the three linear slopes of the line segments between the two points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganesan Thiagarajan, Udayan Dasgupta, Abhijit A. Patki
  • Patent number: 9069364
    Abstract: This document discusses, among other things, voltage converters and computed on-time voltage converters. In an example, an on-time generator for a voltage converter can include a timing capacitor configured to provide a timing voltage, a comparator configured to receive the timing voltage and a threshold voltage and to provide the timing signal using a comparison of the timing voltage and the threshold voltage, a current source configured to discharge the timing voltage of the timing capacitor after a start-up delay, and first and second compensation capacitors configured to bias the timing voltage of the timing capacitor to compensate for the start-up delay.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 30, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Juha-Matti Kujala, Jouni Mika Kalervo Vuorinen
  • Patent number: 9065466
    Abstract: The method includes the accumulation of electric charge in the sampling capacitor (Cn) by parallel connection of the sampling capacitor (Cn) to the source of converted voltage (UIN) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). After detection of the beginning of the next trigger signal (Px+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. The apparatus includes an array of redistribution (A), the section of the sampling capacitor (An), the control module (CM), two comparators (K1 and K2) and the current source (J) connected in a known way.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: June 23, 2015
    Assignee: AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA
    Inventors: Dariusz Koscielnik, Marek Miskowicz
  • Patent number: 9059725
    Abstract: The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 16, 2015
    Inventor: Dennis Michael Koglin
  • Patent number: 9041584
    Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
  • Patent number: 9030346
    Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
  • Patent number: 9019140
    Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics R&D (Shanghai) Co. Ltd.
    Inventors: Jian Hua Zhao, Yuxing Zhang
  • Publication number: 20150109161
    Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.
    Type: Application
    Filed: January 16, 2014
    Publication date: April 23, 2015
    Applicant: Linear Technology Corporation
    Inventor: Gerd TRAMPITSCH
  • Patent number: 9007253
    Abstract: A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8988267
    Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Hideyuki Funaki, Go Kawata, Tetsuro Itakura, Masanori Furuta