Using Charge Transfer Devices (e.g., Charge Coupled Devices, Charge Transfer By Switched Capacitances) Patents (Class 341/172)
  • Patent number: 11442578
    Abstract: Apparatuses and methods of capacitance-to-digital code conversion are described. One apparatus includes a bridge circuit and a modulator front-end circuit. The bridge circuit includes a first terminal to couple to a reference cell and a second terminal to couple to a sensor cell. The modulator front-end circuit includes a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator. The modulator front-end circuit provides a digital bitstream. A duty cycle of the digital bitstream is representative of a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 13, 2022
    Assignee: Cypress Semiconductor Corporation
    Inventor: Andriy Maharyta
  • Patent number: 11431348
    Abstract: A two-capacitor digital-to-analog converter circuit having circuitry to compensate for an unwanted capacitance is disclosed. The converter is configured to generate an average voltage on two capacitors for a sequence of bits in a digital word so that when the final bit is reached, the average voltage corresponds to an analog level of the digital word. The converter is configured to input and average the voltage on the two capacitors using different modes to minimize the effects of capacitor mismatch and switching capacitance on the accuracy of the conversion. The converter includes a buffer amp that has an input capacitance that can affect the conversion. Accordingly, the converter further includes capacitance compensation circuitry configured to provide a replica input capacitance that can be charged and discharged according to the bits of the digital word and coupled to the input capacitor to prevent the input capacitance from affecting the conversion.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: August 30, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Abdullah Ahmed, Akinobu Onishi, Taichiro Kawai
  • Patent number: 11424756
    Abstract: A successive approximation register (SAR) analog-to-digital converter includes a capacitive digital-to-analog converter (CDAC), a comparator, and a SAR control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an input of the CDAC and to an output of the comparator. The SAR control circuit is configured to provide a feedback signal to the CDAC. The CDAC is configured to apply the feedback signal to form an infinite impulse response filter.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 23, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Debapriya Sahu, Pranav Sinha, Meghna Agrawal
  • Patent number: 11418890
    Abstract: The disclosure relates to microphone and other sensor assemblies having a transduction element and an integrated circuit. The integrated circuit includes a switched-capacitor delta-sigma analog-to-digital converter (ADC) including a first integrator stage having a switched-capacitor circuit and a first plurality of parallel amplifiers. A logic circuit coupled to the integrator circuit is configured to selectably disable a subset of enabled amplifiers of the first integrator stage during a first phase of operation and to re-enable the subset of disabled amplifiers during a second phase.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 16, 2022
    Assignee: KNOWLES ELECTRONICS, LLC
    Inventors: Allan Nielsen, Emil Jakobsen, Per F. Høvesten
  • Patent number: 11418209
    Abstract: A signal conversion circuit includes a first pair of capacitors and a comparator. The first pair of capacitors includes a first capacitor and a second capacitor having a same capacitance value. Each of the first capacitor and the second capacitor is coupled to an input signal during a first sampling phase, while uncoupled from the input signal during a first conversion phase after the first sampling phase. The comparator has a first input terminal and a second input terminal. During the first conversion phase, the first capacitor is coupled between the first input terminal and a first reference signal, the second capacitor is coupled between the first input terminal and a second reference signal different from the first reference signal, and the comparator is configured to compare a signal level at the first input terminal and a signal level at the second input terminal to convert the input signal.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 16, 2022
    Assignee: M31 TECHNOLOGY CORPORATION
    Inventors: Hui Huan Wang, Meng Hsuan Wu
  • Patent number: 11405048
    Abstract: A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: August 2, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Wen-Tze Chen
  • Patent number: 11394394
    Abstract: A gain stage, such as an amplifier, e.g., an instrumentation amplifier, can receive an input signal and adjust the level of the input signal, e.g., amplify or attenuate. An output voltage of the gain stage can be applied to a subsequent circuit. Using various techniques, a second stage of an instrumentation amplifier, which can include a transconductance stage that converts a current to a voltage that can be applied to an output node of the instrumentation amplifier, can be removed. Removal of such a second stage can allow an output current from the gain stage to be applied directly from a current output node to an input node of a subsequent circuit.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: July 19, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventor: Venkata Aruna Srikanth Nittala
  • Patent number: 11296714
    Abstract: A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 5, 2022
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Xiaofeng Guo, Erkan Alpman, Jon Sweat Duster, Haigang Feng, Ning Zhang, Yulin Tan
  • Patent number: 11290009
    Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 29, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Chao Chen, Jun Yang, Xinning Liu
  • Patent number: 11290065
    Abstract: A switched capacitor digital power amplifier (DPA) or a digital-to-analog converter (DAC) is disclosed. The DPA/DAC includes a plurality of switched capacitor cells connected in parallel. Each switched capacitor cell includes a capacitor and a switch. The switch selectively drives the capacitor in response to an input digital codeword. The switched capacitor cells are divided into sub-arrays and a series capacitor is inserted in series between two adjacent sub-arrays of switched capacitor cells. All the sub-arrays of switched capacitor cells may be in a unary-coded structure. Alternatively, at least one of the sub-arrays may be in a C-2C structure and at least one another sub-array may be in a unary-coded structure. The switch in the switched capacitor cells is driven by a local oscillator signal, and a phase correction buffer may be added for adjusting a delay of the local oscillator signal supplied to sub-arrays of switched capacitor cells.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 29, 2022
    Assignee: INTEL CORPORATION
    Inventors: Ali Azam, Ashoke Ravi, Bassam Khamaisi, Ofir Degani
  • Patent number: 11283461
    Abstract: A successive approximation (SA) AD converter includes a SA control circuit generating a digital output signal based on an output from a comparator; a first capacitor coupled to an input of the comparator, receiving an analog input signal, and capable of storing electric charges; a second and a third capacitor groups coupling to a reference voltage and storing electric charges previously. The SA control circuit operates for each SA step that the second or the third capacitor group is coupled to a non-inverting input of the comparator and the other is coupled to an inverting input of the comparator based on the output from the comparator. The SA control circuit operates that capacitor terminals of the second and the third capacitor groups coupled to the input of the comparator have the same potential when the reference voltage is stored previously in the second and the third capacitor groups.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: March 22, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Reijiro Ikada
  • Patent number: 11233524
    Abstract: Disclosed are circuits and methods for a CDAC with capacitive references. Individual reference capacitors can be implemented to provide the reference voltages for each input capacitor in a CDAC. For example, each input capacitor may be allocated a high-reference capacitor and a low-reference capacitor to provide the reference voltage to the respective input capacitor. Each of these reference capacitors is charged along with the input capacitor when the CDAC is configured into a loading configuration, and then used to convert digital data to an analog signal when the CDAC is configured into a conversion configuration. Accordingly, the reference voltage for each input capacitor is provided by a separate power source. This contrasts with current solutions in which the reference voltages for the input capacitors are provided by either a singular high-reference voltage source or low-reference voltage source.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 25, 2022
    Assignee: Ethernovia Inc.
    Inventor: Klaas Bult
  • Patent number: 11233968
    Abstract: A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises a sampling switch which is coupled to a 1-column successive approximation register (SAR) analog-to-digital converter (ADC). The 1-column SAR ADC comprises a differential comparator, a local SAR control, and a digital-to-analog converter (DAC). The sampling switch is coupled between a readout column and a non-inverting input of the differential comparator. An image readout method reads one pixel with two conversions through the RC. The RC is operated by the local SAR control to set the DAC based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: January 25, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Oyvind Janbu, Tore Martinussen
  • Patent number: 11163534
    Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 2, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rie Sato, Koichi Mizushima
  • Patent number: 11159171
    Abstract: A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: October 26, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Shih-Hsiung Huang
  • Patent number: 11132933
    Abstract: A circuit device includes a first input terminal, a second input terminal, a reception circuit including a non-inverted input terminal and an inverted input terminal, a first signal line electrically coupling a non-inverted input terminal of the reception circuit and the first input terminal and having a first coupling node and a second coupling node, a second signal line electrically coupling an inverted input terminal of the reception circuit and the second input terminal and having a third coupling node and fourth coupling node, a first variable capacitance circuit having an end coupled to the first coupling node and another end coupled to the second coupling node, and a second variable capacitance circuit having an end coupled to the third coupling node and another end coupled to the fourth coupling node.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 28, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Jun Ishida, Akira Morita
  • Patent number: 11128311
    Abstract: An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 21, 2021
    Assignee: ANPEC ELECTRONICS CORPORATION
    Inventors: Ming-Hung Chang, Jui-Chu Chung
  • Patent number: 11106268
    Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 31, 2021
    Assignee: Redpine Signals, Inc.
    Inventors: Subba Reddy Kallam, Venkat Mattela, Aravinth Kumar Ayyappannair Radhadevi, Sesha Sairam Regulagadda
  • Patent number: 11050432
    Abstract: A pseudo differential analog-to-digital converter includes: a first capacitor array and a second capacitor array respectively coupled to input terminals of an analog-to-digital circuit; where an output terminal of the first capacitor array receives a first reference voltage, and an output terminal of the second capacitor array receives a second reference voltage; and where a difference between the first and second reference voltages is set between zero and a peak value of an analog input signal.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: June 29, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Xunyu Zhu, Lele Jin
  • Patent number: 11041888
    Abstract: A current detection circuit, a semiconductor device and a semiconductor system which are capable of improving current detection accuracy are provided. According to one embodiment of the invention, a current detection circuit includes a resistive element to convert an input current supplied from outside into an input voltage, a constant-current source, a resistive element to convert an output current of the constant-current source into a reference voltage, and an AD converter to AD-convert the input voltage using the reference voltage.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 22, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Keisuke Kimura
  • Patent number: 11031946
    Abstract: Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: June 8, 2021
    Inventor: Joao Pedro Santos Cabrita Marques
  • Patent number: 11012041
    Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: May 18, 2021
    Assignee: ABLIC INC.
    Inventors: Hideyuki Sawai, Tsutomu Tomioka, Tadakatsu Kuroda
  • Patent number: 10985772
    Abstract: According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 20, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Naoya Waki
  • Patent number: 10965312
    Abstract: A capacitance-to-digital converter and an associated method and computer program product are provided that have an extended measurement range. A capacitance-to-digital converter includes first and second capacitors with the second capacitor being configured to measure a change in a value. The capacitance-to-digital converter also includes first and second switches switchably connecting the first and second capacitors, respectively, to a reference voltage while the first and second switches are in a first position such that charge is stored by the first and second capacitors in response to the reference voltage. The capacitance-to-digital converter further includes a saturation detector configured to detect the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor and, in response, causing the first and second switches to switch to a second position while continuing to measure the change in the value with the charge stored by the second capacitor.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: March 30, 2021
    Assignee: Nokia Technologies Oy
    Inventors: Tomislav Matic, Marijan Herceg
  • Patent number: 10965304
    Abstract: The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2N?1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 30, 2021
    Assignee: Radiawave Technologies Co., Ltd.
    Inventors: Xiaofeng Guo, Haigang Feng, Jon Sweat Duster, Ning Zhang, Yulin Tan
  • Patent number: 10958282
    Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-t
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: March 23, 2021
    Assignee: NXP B.V.
    Inventors: Erik Olieman, Alphons Litjes, Leon van der Dussen
  • Patent number: 10951224
    Abstract: The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Terunori Kubo, Narihira Takemura
  • Patent number: 10951225
    Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: March 16, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: Donelson A. Shannon, Edmund M. Schneider, Jianping Wen
  • Patent number: 10938401
    Abstract: Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 2, 2021
    Assignee: NXP B.V.
    Inventors: Erik Olieman, Alphons Litjes, Ibrahim Candan
  • Patent number: 10917105
    Abstract: Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 9, 2021
    Assignee: SHENZHEN GOODIX TECHOLOGY CO., LTD
    Inventors: Ismail Ayman, George Botros, Elsayed Ayman
  • Patent number: 10878858
    Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Hiroyuki Matsuno, Shuichi Tsukada
  • Patent number: 10819363
    Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Cirrus Logic, Inc.
    Inventor: John Paul Lesso
  • Patent number: 10785435
    Abstract: An imaging system includes: an imaging device and a processing device mounted in a vehicle. The imaging device includes: a first pixel coupled to a first signal line, a second pixel coupled to a second signal line, the second signal line is different from the first signal line, a first latch that is coupled to the first signal line, and stores a first digital code, a second latch that is coupled to the second signal line, is adjacent to the first latch, and stores a second digital code, a transfer section that transfers digital codes outputted from the first latch and the second latch, and a diagnosis section that performs diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. The processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: September 22, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Naoki Kawazu, Atsushi Suzuki, Junichiro Azami, Yuichi Motohashi
  • Patent number: 10784883
    Abstract: In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 22, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Prateek Tripathi, Behzad Sheikholeslami, Marceline Kelly Tchambake Yapti
  • Patent number: 10778921
    Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yutaka Abe, Kazuko Nishimura, Hiroshi Fujinaka, Masahiro Higuchi, Dai Ichiryu
  • Patent number: 10732577
    Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: August 4, 2020
    Assignee: NXP B.V.
    Inventors: Hao Fan, Michiel Pertijs, Berry Anthony Johannus Buter
  • Patent number: 10727856
    Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 28, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Cheng-Hui Wu, Jie-Fan Lai, Shih-Hsiung Huang
  • Patent number: 10720831
    Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Christopher Schaef, Vaibhav Vaidya, Suhwan Kim
  • Patent number: 10707887
    Abstract: The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: July 7, 2020
    Assignee: Shenzhen Goodix Technology Co., Ltd.
    Inventor: Wen-Chi Wang
  • Patent number: 10615812
    Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: April 7, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Sandeep Monangi, Mahesh Madhavan
  • Patent number: 10516479
    Abstract: A remote node includes a first node input, a second node input, and an optical switch. The optical switch includes a first switch input optically coupled to the first node input, a second switch input optically coupled to the second node input, a first switch output switchably coupled to the first switch input or the second switch input, and a second switch output switchably coupled to the first switch input or the second switch input. The remote node includes a photodiode optically coupled to the second switch output, and a capacitor electrically coupled to the photodiode and the optical switch. When the first switch input is switchably coupled to the first switch output, the second switch input is switchably coupled to the second switch output. Light received by the second switch input passes out the second switch output to the photodiode. The photodiode charges the capacitor to a threshold charge.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 24, 2019
    Assignee: Google LLC
    Inventors: Liang Du, Yut Loy Chan, Xiangjun Zhao, Changhong Joy Jiang, Cedric Fung Lam, Daoyi Wang, Tao Zhang
  • Patent number: 10504405
    Abstract: A display device is disclosed. The display device includes a display panel including data lines, panel lines, scan lines, and pixels, a power circuit configured to output a reference voltage for initializing subpixels of the pixels, a plurality of branch lines configured to divide a path of the reference voltage into a plurality of paths, and a switch circuit configured to switch a path between the branch lines and the panel lines in response to a switch control signal. The switch circuit changes the path between the branch lines and the panel lines at intervals of predetermined time.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 10, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Hanjin Bae, Sangho Yu
  • Patent number: 10461762
    Abstract: Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 29, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mohammad Meysam Zargham, Yan Wang, Li Lu, Dinesh Jagannath Alladi
  • Patent number: 10382053
    Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 13, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventor: Shuo Fan
  • Patent number: 10326464
    Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Christopher Rogi, Richard Gaggl, Enrique Prefasi
  • Patent number: 10164651
    Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 25, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Kenta Aruga, Yasuhiro Mizuno, Masato Yoshioka
  • Patent number: 10075177
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto
  • Patent number: 9998137
    Abstract: An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 12, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiang Li, Arvind Anumula Paramanandam, Prasanna Upadhyaya, Xiaoyue Wang
  • Patent number: 9960781
    Abstract: A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 1, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Wenlu Chen, Han Chi Hsieh, Raymond Zanoni
  • Patent number: 9843340
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: December 12, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto