Abstract: An analog-to-digital converter can include: a charge distribution and holding module configured to sample a to-be-converted signal, and to perform subtraction on the to-be-converted signal and a target reference voltage by charge distribution, in order to generate a positive-phase output voltage and a negative-phase output voltage on a first and second electric rails, respectively; a common-mode voltage compensation module coupled with the first and second electric rails, and being configured to inject common-mode charges to compensate the distributed charges of the charge distribution and holding module, and to reduce a difference between a common-mode output voltage of the charge distribution and holding module and an expected value; and a comparator configured to provide a logic signal based on a comparison between the positive-phase output voltage and the negative-phase output voltage, where the logic signal corresponds to a target digital signal of the analog-to-digital converter.

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

Abstract: Disclosed is a calibration method of a capacitor array type successive approximation register analog-to-digital converter, comprising: obtaining an actual weight value of capacitors of a target bit and an error code between the actual weight value and an ideal weight value of the capacitors of the target bit; calibrating an output code of the SAR ADC to be calibrated with the error code by corresponding addition or subtraction to obtain a final calibrated output code. The calibration method breaks through the requirement that non-binary weights must meet the redundancy, and can realize a weight calibration in a traditional binary ADC and a digital calibration by simple addition and subtraction on the basis of the original code obtained by an analog-to-digital conversion, thus effectively avoiding the error problem in the traditional technology, increasing the calibration precision and accuracy, reducing the circuit complexity and calculation complexity caused by the non-binary weights calibration.

Abstract: An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

Abstract: It is described an attenuation measurement device (100), comprising: i) a detector unit (110) having a coupling capacitance (120), and an input capacitance (130), wherein the detector unit (110) is configured to produce a detector output signal (112a,b) in reply to an input signal received at the coupling capacitance (120) and/or at the input capacitance (130); ii) a test unit (140), coupled to the detector unit (110), and configured to provide a test signal (141) with at least one known signal property as a first input signal to the coupling capacitance (120); iii) a calibration unit (150), coupled to the detector unit (110), and configured to provide a calibration signal (151) as a second input signal to the input capacitance (130); and iv) a control unit configured to a) determine a first detector output signal (112a) produced by the detector unit (110) in response to the test signal (141), b) identify a specific calibration signal (151) that yields a second detector output signal (112b) that is compara

Abstract: A signal processing circuit includes a first sampling capacitor and a second sampling capacitor that are connected for an input signal path of an analog signal, and a signal processor configured to perform predetermined processing on the analog signal sampled by the first sampling capacitor and the analog signal sampled by the second sampling capacitor. The sampling of the analog signal transmitted to one capacitor of the first sampling capacitor and the second sampling capacitor, and the predetermined processing performed by the signal processor on the analog signal sampled by another capacitor of the first sampling capacitor and the second sampling capacitor can be performed in parallel.

Abstract: A dynamic scaling circuit includes: a damping control circuit; a sampling circuit; and a controller. The damping control circuit has a first input, a second input, a third input, an output, and a ground terminal. The sampling circuit has a first input, a second input, an output, and a ground terminal. The first input of the sampling circuit is coupled to the output of the damping control circuit. The controller has an input, a first output, a second output, and a third output. The first output of the controller is coupled to the second input of the damping control circuit. The second output of the controller is coupled to the third input of the damping control circuit. The third output of the controller is coupled to the second input of the sampling circuit.

Abstract: An embodiment of the present disclosure provides a conversion circuit for converting a single-ended input to a differential input, which has fewer switches and fewer capacitors. This conversion circuit increases the signal-to-noise ratio (SNR), and the conversion circuit directly uses the higher supply voltage AVDD without being bucked by the regulator, wherein the common mode voltage is AVDD/2N, and N is greater than 1. Overall, not only the circuit area is smaller and the SNR is higher, but also the manufacturing cost is reduced. In addition, compared with the prior art, the conversion circuit of the embodiment of the present disclosure has only three operation periods, so the control is simpler and the operation speed is faster.

Abstract: A SAR ADC (50) is disclosed. It comprises a differential input port having a first input (VinP) configured to receive a first input voltage and a second input (VinN) configured to receive a second input voltage, of opposite polarity compared with first input voltage. Furthermore, it comprises a (300) having a first sub circuit (310P) comprising a first plurality of capacitors (2Cu, Cu), each connected to a common node (320P) of the first sub circuit (310P) with a first terminal, and a second sub circuit (310N) comprising a second plurality of capacitors (2Cu, Cu), each connected to a common node (320N) of the second sub circuit (310N) with a first terminal.

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of a plurality of capacitor networks has a plurality of sampling capacitors for sampling over a plurality of sampling sub-phases an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC comprising a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

Abstract: A photoelectric conversion apparatus comprising: pixels; processors; and a controller. Each of the processors comprise a first column circuit and a second column circuit, each of which perform A/D conversion of converting, into a digital signal, one pixel signal output from the pixel arranged in a corresponding column of the plurality of columns. The controller comprises a generator configured to generate a first signal used in the A/D conversion, and a second signal different from the first signal and used in the A/D conversion. The apparatus further comprises a selector configured to receive the first signal and the second signal, and select and supply one of the first signal and the second signal to the second column circuit in a period in which the first signal is supplied to the first column circuit.

Abstract: A circuit includes a switched capacitor circuit and a voltage generator circuit. The switched capacitor circuit includes first, second, third, and fourth switches and first and second capacitors. The first capacitor has first and second terminals, the first terminal coupled to the first switch. The second capacitor has first and second terminals, the second terminal coupled to the second switch. The third switch has a terminal coupled to the second terminals of the first and second capacitors. The fourth switch has first and second terminals, the first terminal coupled the terminal of the third switch and to the second terminals of the first and second capacitors. The voltage generator circuit has an output coupled to the second terminal of the fourth switch and is configured to provide a common mode output bias voltage at the second terminal of the fourth switch responsive to a common mode input bias voltage.

Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT) The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

Abstract: A system may include a sampling capacitor and a switch network. The switch network may include one or more first sampling switches electrically coupled to the sampling capacitor and configured to be activated during a first phase of a sampling cycle of the system and one or more second sampling switches electrically coupled to the sampling capacitor and configured to be activated during a second phase of the sampling cycle, wherein the switch network is configured to reset the sampling capacitor to a data-independent and/or signal-independent charge during a reset phase of the sampling cycle.

Abstract: The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.

Abstract: Mixed signal multipliers and methods for operating the same include a sampling capacitor and an accumulate capacitor. A sampling switch is configured to store an analog value on the sampling capacitor when a digital bit value of a digital signal is one and to store a zero when the digital bit value of the digital signal is a zero. An accumulate switch is configured to store an average of the stored value of the sampling capacitor and a previous stored value of the accumulate capacitor. A processor is configured to alternately trigger the sampling capacitor and the sampling capacitor for each bit value in the digital signal.

Abstract: An electrical signal delay calibration system includes a device under test (DUT) and a digital signal processing chip including a plurality of signal lanes. Each signal lane includes a receive signal path in signal communication with a respective DUT receive path and a transmit signal path in signal communication with a respective DUT transmit path. A processor is configured to determine transmit pulse timestamps assigned to transmit signals transmitted on the transmit signal paths and to determine receive pulse timestamps assigned to receive signals received from the receive signal paths. The processor determines a lane asymmetry associated with each signal lane based on at least one of the transmit pulse timestamps and at least one of the receive pulse timestamps, and removes each of the lane asymmetries to minimize a signal delay in each signal lane among the plurality of signal lanes.

Abstract: Coulomb counter circuitry operable in a first mode of operation and a second mode of operation, the coulomb counter circuitry comprising: first analog to digital converter (ADC) circuitry configured to generate a first ADC output signal indicative of a current through a load coupled to the coulomb counter circuitry; second analog to digital converter (ADC) circuitry; offset correction circuitry; and accumulator circuitry configured to generate a signal indicative of a cumulative amount of charge transferred to the load, wherein in the second mode of operation, the coulomb counter circuitry is operable to enable the second ADC circuitry and to generate an offset correction factor based at least in part on a second ADC output signal output by the second ADC circuitry, and wherein in subsequent operation of the coulomb counter circuitry in the first mode of operation, the offset correction circuitry applies the offset correction factor to the first ADC output signal.

Abstract: An analog-to-digital converting device configured to convert an analog signal into a digital signal, including a meta-stability detection unit configured to output a meta-stability signal based on a comparison result, wherein the comparison result is determined by comparing a comparison voltage of each bit of the digital signal with the analog signal; a counter configured to count a number of times that the comparison voltage of each bit of the digital signal is compared with the analog signal; and a control logic configured to detect a bit at which meta-stability has occurred from among bits of the digital signal based on the meta-stability signal and the counted number.

Abstract: An angle measurement system using a magnet and provided with first and second tracks includes an absolute angle calculation unit configured to calculate an absolute angle of a position of the magnet by using a 1-1th digital signal obtained by measuring a magnetic field signal of the first track and converted into a digital signal, a 1-2th digital signal obtained by measuring the magnetic field signal of the first track and converted into a digital signal, a 2-1th digital signal obtained by measuring a magnetic field signal of the second track and converted into a digital signal, and a 2-2th digital signal obtained by measuring the magnetic field signal of the second track and converted into a digital signal.

Abstract: A method of amplifying an input voltage based on cascaded charge pump includes generating, at a set of capacitors, an input voltage corresponding to input data. The method further includes storing, by a first capacitor, first electrical charges corresponding to the input voltage to obtain a second voltage. The method further includes amplifying, a voltage amplifier, the second voltage according to the first electrical charges stored by the first capacitor to obtain a third voltage. The method further includes storing, by a second capacitor, second electrical charges according to the third voltage. The method further includes amplifying, by the voltage amplifier, the third voltage according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.

Abstract: High speed, high dynamic range SAR ADC method and architecture. The SAR DAC comparison method can make fewer comparisons with less charge/fewer capacitors. The architecture makes use of a modified top plate switching (TPS) DAC technique and therefore achieves very high-speed operation. The present disclosure proffers a unique SAR ADC method of input and reference capacitor DAC switching. This benefits in higher dynamic range, no external decoupling capacitory requirement, wide common mode range and overall faster operation due to the absence of mini-ADC.

Abstract: Embodiments of the disclosure provide a circuit structure and method to indicate a differential voltage polarity using a comparator. The circuit structure includes a digital-to-analog converter (DAC) coupled to a positive differential voltage, a negative differential voltage, and a reference voltage. The DAC generates an output based on the positive differential voltage, the negative differential voltage, and the reference voltage. A comparator has a first input coupled to one of the DAC output and the positive differential voltage, and a second input coupled to one of the reference voltage and the negative differential voltage. A multiplexer array is coupled to the comparator and transmits one of: the positive differential voltage and the negative differential voltage to the comparator, causing the comparator to output a differential voltage polarity; and the DAC output and the reference voltage, causing the comparator to output an approximated bit for the DAC output.

Abstract: A bootstrapped switch circuit coupled to a timing circuit. The bootstrapped switch circuit comprises a charge pump coupled to the timing circuit. The bootstrapped switch circuit also comprises a logic circuit coupled to the output of the charge pump and the timing circuit. The logic circuit is capable of generating multiple control signals which can independently control the turn-on of switches in the voltage path between the inputs and outputs of the bootstrapped switch circuit.

Abstract: Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution disclosed in the present invention is to apply a step function and examine the output's slow settling error waveform. A signal is input to an analog to digital converter, and the output of the converter is processed by a computation that produces calibration codes. Calibration codes are coupled to a SC circuitry to mitigate the PZ-doublet errors. The error waveform is then minimized within a specified accuracy.

Abstract: A dc-dc converter can include a plurality of switches, a piezoelectric resonator (PR) for power stage energy storage, and a means for controlling one or more switching sequences. The switches operate in accordance with the switching sequences to transfer energy from the input to the output via the PR while providing low-loss resonant soft-charging of the PR's capacitance. The switching sequences include: connected stages in which a first and second PR terminals are both connected to one of the input, the output, or the other PR terminal; and open stages in which at least one of the first or second PR terminal is not connected by a closed switch to one of the input, the output, or the other PR terminal.

Abstract: An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.

Abstract: The present disclosure relates to a high-speed and low-power successive approximation register analog-to-digital converter (SAR ADC) and an analog-to-digital conversion method. Binary redundancy reassembly is performed to improve a digital-to-analog converter (DAC) capacitor array included in the SAR ADC such that the total number of capacitors included in a capacitor sub-array of the DAC capacitor array is greater than the number of precision bits of the SAR ADC, and the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is greater than the number of precision bits of the SAR ADC is equal to the total number of unit capacitors included in all capacitors when the total number of capacitors included in the capacitor sub-array is equal to the number of precision bits of the SAR ADC.

Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

Abstract: Analog to digital conversion circuitry has an input sampling buffer, which has an input sampling capacitor for sampling an analog signal. The conversion circuitry also has a successive-approximation-register analog to digital converter (SAR-ADC) which converts the sampled analog signal to a digital signal. The input sampling buffer has an amplifier and a gain-control capacitor, and has an amplification configuration and an error-feedback configuration. In the amplification configuration, the input sampling capacitor is coupled to the amplifier and gain-control capacitor, with the gain-control capacitor connected in feedback with the amplifier, for applying gain to the sampled analog signal.

Abstract: A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ?? modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

Abstract: An analog switch circuit in a successive approximation register analog-to-digital converter for a wide sampling rate includes a first PMOS switch controlled by a voltage of a second control node, second PMOS switch controlled by a control voltage, a first control switch unit controlling voltages of first and second control nodes, a first NMOS switch controlled by a voltage of a fourth control node, a second NMOS switch controlled by the control voltage und, and a second control switch unit controlling voltages of third and fourth control nodes.

Abstract: Disclosed herein are embodiments of a wide bandwidth attenuator circuit having a tunable gain and tunable input impedance. In some embodiments, the wideband attenuator circuit comprises a serial capacitor shunted to ground by a plurality of circuit slices that are connected in parallel and switchably coupled to the output node of the attenuator. Each circuit slice has a tunable resistor that can be set to a conductive state (“enabled”) or a high impedance state (“disabled”) The number of enabled circuit slices that are connected in parallel may be used to program the attenuator gain and the attenuator impedance.

Abstract: A memory device includes an array of memory cells, a diode having a threshold voltage that changes with temperature, an analog-to-digital converter (ADC), and a pulse generator. The ADC includes a voltage comparator having a positive terminal coupled with the diode. The ADC further includes a first capacitor coupled between a negative terminal of the voltage comparator and ground, and a second capacitor selectively coupled between the first capacitor and a voltage reference node. The second capacitor has a smaller capacitance than that of the first capacitor. The pulse generator is coupled with the ADC and generates pulses. The pulses cause the first capacitor to connect to the second capacitor and equalize charge between the first capacitor and the second capacitor. An inverted signal of the pulses causes the second capacitor to be coupled with the voltage reference node to pre-charge the first capacitor.

Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

Abstract: A semiconductor circuit includes: an analog circuit that inputs a measured signal; and a digital circuit that outputs a digital output signal. The analog circuit includes: a correction element group including one or more correction elements each for correcting an offset that is an amount of shift caused by a variation in characteristics of the analog circuit to occur in a path for transmitting the measured signal; and a test element group including one or more test elements for testing the one or more correction elements. The digital circuit tests the correction element group using the test element group.

Abstract: A motion sensor with sigma-delta analog-to-digital converter (ADC) having improved bias instability is presented herein. Differential outputs of a differential amplifier of the sigma-delta ADC are electrically coupled, via respective capacitances, to differential inputs of the differential amplifier. To minimize bias instability corresponding to flicker noise that has been injected into the differential inputs, the differential inputs are electrically coupled, via respective pairs of electronic switches, to feedback resistances based on a pair of switch control signals. In this regard, a first feedback resistance of the feedback resistances is electrically coupled to a first defined voltage, and a second feedback resistance of the feedback resistances is electrically coupled to a second defined reference voltage.

Abstract: The present disclosure relates to an analog-to-digital conversion circuit comprising: N sampling and conversion modules connected in parallel, configured to simultaneously sample and sequentially convert first analog signals of N channels to output second analog signals, wherein each of the sampling and conversion modules includes a plurality of sampling capacitors connected in parallel, wherein N is an integer greater than 1; a comparator connected to the N sampling and conversion modules, configured to comparing the second analog signals respectively to obtain comparison signals; and a control module connected to the N sampling and conversion modules and the comparator, configured to control the N sampling and conversion modules to output converted digital signals based on the comparison signals.

Abstract: An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

Abstract: A readout circuit for an image sensor having a pixel array with at least one pixel group, in particular pixel column, with a plurality of pixels connected to a group bus comprises a group input for connecting to the group bus and a signal output for connecting to an input of an ADC. The readout circuit further comprises a first and a second reference terminal for receiving a first and a second reference voltage. A sampling bank comprises at least two sample-and-hold elements connected in parallel between the group input and an output of the sampling bank and further comprises a bypass switch connected in parallel to the sample-and-hold elements. A charge store is connected between the output of the sampling bank and the signal output. A first charge switch is connected between the first reference terminal and the signal output, and a second charge switch is connected between the second reference terminal and the output of the sampling bank.

Abstract: A DA conversion circuit includes a first DA conversion circuit unit corresponding to a higher bit, a second DA conversion circuit unit corresponding to a lower bit, a capacitance element provided between the first DA conversion circuit unit and the second DA conversion circuit unit, the first DA conversion circuit unit includes a capacitance element and a selection circuit, the second DA conversion circuit unit includes a capacitance element and a selection circuit, and the selection circuit supplies a potential VL or VPH to one end of the capacitance element, and the selection circuit supplies the potential VL or VPL to one end of the capacitance element. The potential VPL is different from the potential VPH, and for example, VPL>VPH.

Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors and compare signals at outputs of the switched capacitors. The SAR ADC may also determine, based on a value of a tunable time interval, whether to set a metastability flag for a first bit to be evaluated and update the value of the tunable time interval based on whether the metastability flag was set.

Abstract: A voltage detector comprises an input, a resistor divider circuit having resistors coupled in series with one another between the input and a reference node, and N intermediate nodes joining adjacent pairs of the resistors. The voltage detector has N switches coupled to the respective intermediate nodes, as well as a comparator with an input coupled to the switches, a state machine having an input coupled to the output of the comparator, and a decoder having N decoder outputs coupled to respective control terminals of the N switches.

Abstract: Lossless digital cancelation of internally generated spurious products within a signal receiver system is provided. In embodiments, the receiver system generates reference frequencies corresponding to internal components within the receiver (e.g., mixers, oscillators, clocks, analog-digital converters (ADC)) that introduce spurious products into the digitization of a received RF signal. The receiver system precisely duplicates each introduced spurious product based on the reference frequencies and filters out each corresponding spurious product out of the digitized signal. Individualized canceler circuits for each introduced spurious product adjust the corresponding duplicate spurious products to cancel out the introduced spurious product from the digitized signal, resulting in an output signal free of self-generated interference.

Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N?K)th capacitor, and a constant binary weight from the (N?K)th capacitor to a (N?K?2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

Abstract: A successive approximation register analog to digital converter includes a sampling circuitry, a comparator circuit, and a controller circuitry. The sampling circuitry generates first and second signals according to a sampled signal. The comparator circuit compares the first signal with the second signal to generate first decision signals. The controller circuitry generates digital codes according to the first decision signals, and controls the comparator circuit to perform comparisons repeatedly to generate second decision signals, in order to generate a digital output according to the digital codes, a statistical noise value, and the second decision signals.

Abstract: An analog-to-digital device includes a sampling circuit for sampling an input signal. The sampling circuit stops sampling in response to obtaining a trigger signal. The analog-to-digital device includes an analog-to-digital converter circuit which includes an analog to digital converter (ADC) for converting a sampled input provided from the sampling circuit to digital output.

Abstract: Multiple adjustment capacitors corresponding to multiple source bus lines on a one-to-one correspondence basis are arranged. Each adjustment capacitor includes a first electrode supplied with an adjustment signal and a second electrode connected to the source bus line. The adjustment capacitors are divided into multiple groups. An adjustment signal having a amplitude different from group to group is supplied to the adjustment capacitor. A potential of the adjustment signal is raised after a liquid-crystal capacitor is charged in a pixel formation region including a thin-film transistor (TFT) that is turned on with a gate driver causing a scanning signal to rise and before the gate driver causes the scanning signal to fall.