Using Charge Transfer Devices (e.g., Charge Coupled Devices, Charge Transfer By Switched Capacitances) Patents (Class 341/172)
  • Patent number: 10326464
    Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Christopher Rogi, Richard Gaggl, Enrique Prefasi
  • Patent number: 10164651
    Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 25, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Kenta Aruga, Yasuhiro Mizuno, Masato Yoshioka
  • Patent number: 10075177
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 11, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto
  • Patent number: 9998137
    Abstract: An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.
    Type: Grant
    Filed: September 17, 2017
    Date of Patent: June 12, 2018
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Xiang Li, Arvind Anumula Paramanandam, Prasanna Upadhyaya, Xiaoyue Wang
  • Patent number: 9960781
    Abstract: A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: May 1, 2018
    Assignee: Rockwell Collins, Inc.
    Inventors: Wenlu Chen, Han Chi Hsieh, Raymond Zanoni
  • Patent number: 9843340
    Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: December 12, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Funato, Yasuo Morimoto
  • Patent number: 9702891
    Abstract: An analogue amplification device comprises a first stage with a common base or gate transistor that receives the modulated input current on its emitter or its source and the output signal of this first stage corresponds to the signal of the collector, a second stage formed by a follower amplifier comprising a transistor with a common collector or drain setup, a third stage that comprises a transistor with a common emitter setup, and a fourth stage that is an amplifying stage with means allowing the realization of, on the one hand, an amplification, and on the other hand, a matching of impedance. The device can be applied to a laser anemometer with optical retro-injection.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: July 11, 2017
    Assignees: EPSILINE, INSTITUT NATIONAL POLYTECHNIQUE DE TOULOUSE
    Inventors: Francis Bony, Raphael Teysseyre
  • Patent number: 9692437
    Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 27, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Young-deuk Jeon, Min-Hyung Cho, Yi-Gyeong Kim, Chun-Gi Lyuh
  • Patent number: 9554072
    Abstract: The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: January 24, 2017
    Assignee: Innovaciones Microelectrónicas S.L.
    Inventors: Fernando Medeiro Hidalgo, Rafael Domínguez Castro
  • Patent number: 9509926
    Abstract: A photoelectric conversion device includes analog signal output units including pixels and configured to output analog signals based on pixels, and signal processing units. Each of the signal processing units is provided correspondingly to one of the analog signal output units and including a gain application unit configured to apply a gain to an analog signal by using only passive elements and an AD conversion unit. In the gain application unit, a portion that contributes to application of a gain to the analog signal is constituted only of passive elements. The gain application unit selectively outputs a first amplified signal obtained by applying a first gain to the analog signal or a second amplified signal obtained by applying a second gain to the analog signal smaller than the first gain. The AD conversion unit converts, from analog to digital, the first or second amplified signal.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: November 29, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takashi Muto, Takeru Suzuki, Yasushi Matsuno, Daisuke Yoshida
  • Patent number: 9496888
    Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Sunny Sharma, Chin Yeong Koh, Samaksh Sinha
  • Patent number: 9413379
    Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: August 9, 2016
    Assignees: Samsung Electronics Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Yun-Jung Kim, Jong-Boo Kim, Oh-Kyong Kwon
  • Patent number: 9300314
    Abstract: An arrangement for reading out an analog voltage signal includes a voltage signal input for applying the analog voltage signal thereto, a reference unit configured to generate an analog reference voltage, and a converting unit configured to convert an analog input signal into a digital output signal. To enable online self-calibration of the arrangement, the arrangement includes a superposition unit configured to receive the analog voltage signal and the analog reference voltage. The superposition unit includes a modulation unit configured to generate a modulated reference voltage from the analog reference voltage. The superposition unit is configured to generate a combined analog signal by superimposing the modulated reference voltage onto the analog voltage signal, and to forward the combined analog signal to the converting unit.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: March 29, 2016
    Assignee: ABB TECHNOLOGY AG
    Inventors: Joris Pascal, Richard Bloch
  • Patent number: 9287888
    Abstract: A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: March 15, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Ming-Cheng Chiang, Wei-Cheng Tang
  • Patent number: 9219492
    Abstract: A multi-stage Successive-Approximation Register (SAR) pipeline Analog-to-Digital Converter (ADC) has an amplifier between two switched capacitor networks, each controlled by a SAR. The load capacitance of the amplifier is magnified due to the amplifier's gain. This magnified load capacitance can disproportionately increase power consumption. The back plates of the second-stage switched capacitors are connected to the amplifier input using a feedback switch during an amplification phase, so that the second-stage switched capacitors are connected between the input and output of the amplifier as a feedback capacitor, rather than a load capacitor. Reset switches are added to drive both plates of the second-stage switched capacitors to ground during a reset phase before the amplification phase. Thus the second-stage switched capacitors function as both the feedback capacitor and as the switched capacitors controlled by the second SAR.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 22, 2015
    Assignee: Hong Kong Applied Science & Technology Research Institute Company, Limited
    Inventors: Chi Fung Lok, Shiyuan Zheng
  • Patent number: 9178522
    Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: November 3, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Emanuele Bodano, Peter Bogner, Joachim Pichler, Mark Schauer
  • Patent number: 9154150
    Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N?2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N?2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: October 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Jiangfeng Wu, Wei-Te Chou, Rong Wu
  • Patent number: 9153297
    Abstract: An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 6, 2015
    Assignee: Infineon Technologies AG
    Inventors: Kazimierz Szczypinski, Wen-Ming Lee
  • Patent number: 9148603
    Abstract: An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 29, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ashirwad Bahukhandi, Taehee Cho, Nikolai Bock
  • Patent number: 9143144
    Abstract: Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: September 22, 2015
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Jayanth Kuppambatti, Junhua Shen, Peter Kinget
  • Patent number: 9136867
    Abstract: The present invention relates to a delta-sigma-modulator and a delta-sigma-A/D converter. By speeding up the settling time constant of an integrator at the last stage with a simple configuration, the sampling frequency is sped up in the delta-sigma-modulator as a whole. Specifically, in the delta-sigma-modulator including multiple integrators connected in cascade, the integrator positioned at the last stage is a passive integrator not using an amplifier circuit, and one or more integrators positioned at stages preceding the last stage by one or more stages are active SC integrators using amplifier circuits and switched capacitor circuits, respectively. Also, each of the integrators performs integral calculation by alternately repeating a first operation phase to charge a sampling capacitor by sampling an input signal, and a second operation phase to perform a summing integration by transferring an electric charge charged in the sampling capacitor to an integration capacitor.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: September 15, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hikaru Watanabe
  • Patent number: 9136863
    Abstract: The present invention discloses a successive approximation analog-to-digital converter, comprising: a capacitor array including a designated capacitor and several sampling capacitors to sample an input signal under a sampling mode; a comparator to compare a first voltage from the capacitor array with a second voltage under a comparison mode and thereby generate a comparison result; a switching circuit to determine the charge amount stored in the capacitor array under the sampling mode and the first voltage under the comparison mode according to a control signal; and a control circuit to generate the control signal according to a sampling setting under the sampling mode and generate the control signal according to the comparison result under the comparison mode. Said designated capacitor does no sampling under the sampling mode, but appropriates the charges of the sampling capacitors under the comparison mode, so as to reduce the effective sampling value.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 15, 2015
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Sheng-Hsiung Lin
  • Patent number: 9100034
    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 4, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
  • Patent number: 9083345
    Abstract: A circuit arrangement for determining a capacitance of a number n of capacitive sensor elements (SE1˜SEn) comprises at least one collecting capacitor (CS1˜CSm), a reference voltage source (RQ), an evaluation device (AE) connected to the at least one collecting capacitor to evaluate a voltage present at the at least one collecting capacitor, a control unit (MC) for generating at least one control signal (SS1˜SSk), and at least one integrated circuit (IC1˜ICm) connected to the reference voltage source, the sensor elements, and the at least one collecting capacitor. The at least one integrated circuit comprises a number k of changeover switches (WS1˜WSk) responsive to the at least one control signal to connect the respectively associated sensor element to the reference voltage source in a first switching position, and to the at least one collecting capacitor in a second switching position.
    Type: Grant
    Filed: January 24, 2011
    Date of Patent: July 14, 2015
    Assignee: E.G.O. Elektro-Gerätebau GmbH
    Inventor: Randolf Kraus
  • Patent number: 9083375
    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) includes a comparator coupled to receive a sampled input voltage; a pair of arrays each including individually switchable binary-weighted capacitors that are switchably coupled to an output of the comparator via phase switches, respectively. A phase signal for controlling a corresponding phase switch associated with a current bit becomes asserted when a preceding bit finishes comparison, and the phase signal becomes de-asserted when the current bit finishes comparison.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: July 14, 2015
    Assignees: NCKU Research and Development Foundation, Himax Technologies Limited
    Inventors: Soon-Jyh Chang, Che-Hsun Kuo, Chung-Ming Huang
  • Patent number: 9077359
    Abstract: A method, comprising: selecting two Two-Tuples before and two after a selected synchronous ADC conversion point; calculating the coefficients of a third order polynomial based on the value of the previous time asynchronous sample, the time differences between each of the asynchronous samples surrounding the selected sample, and the three linear slopes of the line segments between the two points before and the points after the selected synchronous sample point, including the slope of the selected point; evaluating the third order polynomial at the synchronous time instant; generating the synchronous ADC value based on this calculation; and using the ADC value as the desired voltage level of the synchronous sample, wherein the synchronous ADC value is generated based on this calculation.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: July 7, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganesan Thiagarajan, Udayan Dasgupta, Abhijit A. Patki
  • Patent number: 9077355
    Abstract: A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 7, 2015
    Assignee: Broadcom Corporation
    Inventor: Frank Maria Leonardus van der Goes
  • Patent number: 9069364
    Abstract: This document discusses, among other things, voltage converters and computed on-time voltage converters. In an example, an on-time generator for a voltage converter can include a timing capacitor configured to provide a timing voltage, a comparator configured to receive the timing voltage and a threshold voltage and to provide the timing signal using a comparison of the timing voltage and the threshold voltage, a current source configured to discharge the timing voltage of the timing capacitor after a start-up delay, and first and second compensation capacitors configured to bias the timing voltage of the timing capacitor to compensate for the start-up delay.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: June 30, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Juha-Matti Kujala, Jouni Mika Kalervo Vuorinen
  • Patent number: 9065466
    Abstract: The method includes the accumulation of electric charge in the sampling capacitor (Cn) by parallel connection of the sampling capacitor (Cn) to the source of converted voltage (UIN) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). After detection of the beginning of the next trigger signal (Px+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. The apparatus includes an array of redistribution (A), the section of the sampling capacitor (An), the control module (CM), two comparators (K1 and K2) and the current source (J) connected in a known way.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: June 23, 2015
    Assignee: AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA
    Inventors: Dariusz Koscielnik, Marek Miskowicz
  • Patent number: 9059725
    Abstract: The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 16, 2015
    Inventor: Dennis Michael Koglin
  • Patent number: 9041584
    Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 26, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
  • Patent number: 9030346
    Abstract: A single-ended SAR ADC includes an additional capacitor, a self-test engine, and independent control of sample and hold conditions, which allows for quick and accurate testing of the ADC.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sanjoy K. Dey, Michael T. Berens, James R. Feddeler, Vikram Varma
  • Patent number: 9019140
    Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics R&D (Shanghai) Co. Ltd.
    Inventors: Jian Hua Zhao, Yuxing Zhang
  • Publication number: 20150109161
    Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.
    Type: Application
    Filed: January 16, 2014
    Publication date: April 23, 2015
    Applicant: Linear Technology Corporation
    Inventor: Gerd TRAMPITSCH
  • Patent number: 9007253
    Abstract: A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8988267
    Abstract: According to an embodiment, a signal processing device includes an integrator, a setting unit, and an analog-to-digital converter. The integrator is configured to integrate an electrical charge corresponding to electromagnetic waves. The integrator includes a capacitor configured to store the electrical charge corresponding to the electromagnetic waves and a discharging circuit configured to discharge the capacitor. The setting unit is configured to set a period of integration of the electrical charge with respect to the integrator. The analog-to-digital converter includes a comparator configured to compare an integration output and a threshold value and a counter configured to output, as digital data of the electrical charge, the number of times for which a value of the integration output becomes not less than the threshold value. The converter is configured to discharge the capacitor during the period of integration by supplying a comparison output of the comparator to the discharging circuit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: March 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shunsuke Kimura, Hideyuki Funaki, Go Kawata, Tetsuro Itakura, Masanori Furuta
  • Patent number: 8988263
    Abstract: A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: March 24, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Sanyi Zhan, Daniel J. Cooley, Ligang Zhang
  • Publication number: 20150077320
    Abstract: An analog to digital conversion device has a plurality of, two, for example, analog to digital converters, and a reference charge quantity interchange section arranged and configured to interchange, among the plurality of analog to digital converters, reference quantities of electric charge (e.g., reference currents or reference capacitances) to be used therein during an analog to digital conversion period.
    Type: Application
    Filed: March 28, 2013
    Publication date: March 19, 2015
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Sato, Takahiro Inoue
  • Publication number: 20150061913
    Abstract: A method includes receiving a differential voltage signal at first and second inputs of a comparator and selectively providing the differential voltage signal to one of a first conversion path and a second conversion path of the comparator during a conversion phase to determine a digital value corresponding to the differential voltage signal. The first and second conversion paths including first and second pluralities of gain stages, respectively. The method further includes coupling the selected one of the first conversion path and the second conversion path to an output to provide the digital value.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 5, 2015
    Applicant: Silicon Laboratories Inc.
    Inventors: Xiaodong Wang, Shouli Yan, Axel Thomsen
  • Patent number: 8969774
    Abstract: An image sensor includes a pixel array having pixels arranged in rows and columns, a first successive-approximation-register (“SAR”) analog-to-digital-converter (“ADC”), a second SAR ADC, and first and second control circuitry. The first SAR ADC includes a first capacitor array (“FCA”) that shares a first common terminal coupled to a first comparator and coupled to receive first analog pixel signals. The second SAR ADC includes a second capacitor array (“SCA”) that shares a second common terminal selectably coupled to a second comparator and coupled to receive second analog pixel signals. The first and second control modules are coupled to selectably switch bottom plates of the FCA from a low reference voltage to the high reference voltage at a same time as selectably switching bottom plates of the SCA from a high reference voltage to the low reference voltage.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 3, 2015
    Assignee: OmniVision Technologies, Inc.
    Inventor: Robert Johansson
  • Publication number: 20150054668
    Abstract: A system includes a first capacitor group to facilitate determination of a first bit, and a second capacitor group to facilitate determination of a second bit in combination with the first capacitor group. The system further includes a delayed clock switch to engage the second capacitor group after determination of the first bit.
    Type: Application
    Filed: September 18, 2013
    Publication date: February 26, 2015
    Applicant: Broadcom Corporation
    Inventor: Frank Maria Leonardus van der Goes
  • Patent number: 8964074
    Abstract: An amplification circuit includes an amplifier, a first capacitor including a first terminal connected to an input terminal of the amplifier, a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to an output terminal of the amplifier, and a correction unit configured to correct a difference in bias dependency between capacitance values of the first and second capacitors.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Patent number: 8963754
    Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quantizer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: February 24, 2015
    Assignees: IMEC, Stichting IMEC Nederland, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Alonso Morgado, Serena Porrazzo, Francesco Cannillo
  • Patent number: 8964860
    Abstract: To provide a digital modulator including: a signal adjuster (105) which is provided with a plurality of output lines, and which outputs, to the output line, which corresponds to a range to which a level of an input signal belongs, a signal of a level corresponding to the level of the input signal; a plurality of internal digital modulators (111-1 to 111-N), each of which is provided so as to correspond to each of the plurality of output lines and carries out delta-sigma modulation on the signal of the corresponding output line to output the modulated signal; and an encoder (113) which encodes the plurality of modulated signals respectively outputted by the plurality of internal digital modulators.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 24, 2015
    Assignee: NEC Corporation
    Inventor: Shinichi Hori
  • Patent number: 8963763
    Abstract: A method for operating an analog-digital converter including a number of charging units, each comprising a switchable capacitor and an associated reference potential source, includes evaluating a comparison potential in successive decision steps to obtain a comparison result; and successively switching one of the charging units following a previous one of the decision steps, wherein, depending on the obtained comparison result, the comparison potential is changed by the one respective charging unit by connecting the associated reference potential source to the switchable capacitor, wherein in two of the successive switching steps different reference potentials are applied to the switchable capacitor.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Lukas Kull
  • Patent number: 8957804
    Abstract: The successive approximation A/D converter includes: switch groups 105—1 to 105—x each of which is connected to the other end of each corresponding capacitor of capacitors 106—1 to 106—x to selectively switch a capacitor to be applied to a successive comparison in response to a switch group control signal Ct1; a comparator 104 for making a successive comparison of a comparison voltage VSN based on a holding voltage on each corresponding capacitor, selected through the switch groups from among the capacitors, with a predetermined reference voltage VC in synchronization with a timing control signal CLK to obtain a judgment output according to the comparison result; and a voltage application part 107 for applying a predetermined voltage to the comparison voltage based on a form-of-voltage application control signal Ct2 for a predetermined period when a predetermined time has elapsed after the successive comparison.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: February 17, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Junya Nakanishi
  • Patent number: 8957805
    Abstract: A balanced signal processing circuit includes: a comparator; a first capacitor having a first end connected to a non-inverting input terminal of the comparator; a second capacitor having a first end connected to an inverting input terminal of the comparator; a first switch configured to apply a voltage signal to the first end of the first capacitor; a second switch configured to apply a voltage signal to the first end of the second capacitor; an operation state detection section configured to detect an operation state of the comparator; and an offset voltage correction section configured to apply a predetermined offset voltage to a second end of the first capacitor and a second end of the second capacitor when the operation state detection section detects an abnormal operation state of the comparator.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Atsumi Niwa
  • Patent number: 8957803
    Abstract: A capacitive voltage divider arrangement includes a first and second voltage divider and a first and second parasitic capacitance formed between the first and second capacitive voltage divider. The first capacitive voltage divider includes: a signal terminal; first capacitance for coupling the terminal to a reference potential; second capacitance; and third capacitance that is coupleable to the reference potential, the second capacitance being coupled in-between the terminal and third capacitance.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: February 17, 2015
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Harish Balasubramaniam, Harald Neubauer
  • Patent number: 8947288
    Abstract: A differential analog-digital converter is provided. The converter comprises a decision unit for evaluating a potential difference between two input signal lines, a number of charging units for each input signal line each configured to add a predetermined charge onto the respective input signal line, a number of discharging units for each input signal line each configured to remove a predetermined charge from the respective input signal line and a control unit for selectively switching each of the charging units and discharging units so that depending on one result of evaluating the potential difference between the two input signal lines one of the input signal lines is charged by adding the predetermined charge of the respective switched charging unit while the respective other of the input signal lines is discharged by removing the predetermined charge of the respective switched discharging unit.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventor: Lukas Kull
  • Patent number: 8947286
    Abstract: An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Fujitsu Limited
    Inventor: Yanfei Chen