Abstract: According to one embodiment, an arithmetic device includes one or a plurality of arithmetic units. One of the one or plurality of arithmetic units includes a memory part including a plurality of memory regions, and an arithmetic part. At least one of the memory regions includes a memory element. The memory element is of a shift register-type.

Abstract: A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.

Abstract: A circuit device includes a first input terminal, a second input terminal, a reception circuit including a non-inverted input terminal and an inverted input terminal, a first signal line electrically coupling a non-inverted input terminal of the reception circuit and the first input terminal and having a first coupling node and a second coupling node, a second signal line electrically coupling an inverted input terminal of the reception circuit and the second input terminal and having a third coupling node and fourth coupling node, a first variable capacitance circuit having an end coupled to the first coupling node and another end coupled to the second coupling node, and a second variable capacitance circuit having an end coupled to the third coupling node and another end coupled to the fourth coupling node.

Abstract: An analog-to-digital converting system and a method with offset correction mechanisms are provided. The method includes steps of: obtaining a direct current offset of an output voltage of a digital analog conversion unit in a system; obtaining first capacitance weights and second capacitance weights sequentially from small to large; subtracting the direct current offset from a digital signal; and multiplying bit values of the digital signal respectively by the corresponding first capacitance weight value or second capacitance weight value to output a decode signal.

Abstract: The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

Abstract: A pseudo differential analog-to-digital converter includes: a first capacitor array and a second capacitor array respectively coupled to input terminals of an analog-to-digital circuit; where an output terminal of the first capacitor array receives a first reference voltage, and an output terminal of the second capacitor array receives a second reference voltage; and where a difference between the first and second reference voltages is set between zero and a peak value of an analog input signal.

Abstract: A current detection circuit, a semiconductor device and a semiconductor system which are capable of improving current detection accuracy are provided. According to one embodiment of the invention, a current detection circuit includes a resistive element to convert an input current supplied from outside into an input voltage, a constant-current source, a resistive element to convert an output current of the constant-current source into a reference voltage, and an AD converter to AD-convert the input voltage using the reference voltage.

Abstract: Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.

Abstract: A capacitance-to-digital converter and an associated method and computer program product are provided that have an extended measurement range. A capacitance-to-digital converter includes first and second capacitors with the second capacitor being configured to measure a change in a value. The capacitance-to-digital converter also includes first and second switches switchably connecting the first and second capacitors, respectively, to a reference voltage while the first and second switches are in a first position such that charge is stored by the first and second capacitors in response to the reference voltage. The capacitance-to-digital converter further includes a saturation detector configured to detect the charge stored by the second capacitor equaling or exceeding the charge stored by the first capacitor and, in response, causing the first and second switches to switch to a second position while continuing to measure the change in the value with the charge stored by the second capacitor.

Abstract: The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2N?1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital

Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-t

Abstract: The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.

Abstract: A SAR ADC may include a plurality of capacitor networks, wherein each capacitor network of the plurality of capacitor networks has a sampling capacitor for sampling an analog input signal to the SAR ADC and at least one non-sampling capacitor. The SAR ADC may also include a DAC including a plurality of sub-DACs including at least a first sub-DAC representing most significant bits of an output of the SAR ADC, wherein the output of the first sub-DAC is coupled to the sampling capacitors of the plurality of capacitor networks and a second sub-DAC representing bits of the output of the SAR ADC lesser in magnitude significance than those of the first sub-DAC, wherein the output of the second sub-DAC is coupled to a respective one of at least one non-sampling capacitor of each of the plurality of capacitor networks.

Abstract: Embodiments of an analog-to-digital converter (ADC), resistive digital-to-analog converter (DAC) circuits, and methods of operating an ADC are disclosed. In an embodiment, an analog-to-digital converter includes a DAC unit configured to convert a digital code to a first voltage in response to an input voltage of the ADC, a comparator configured to compare the first voltage with a second voltage to generate a comparison output, and a logic circuit configured to generate the digital code, to control the DAC unit based on the comparison output, and to output the digital code as a digital output of the ADC. The DAC unit includes a capacitive DAC and multiple resistive DACs. Each of the resistive DACs is connected to the first voltage through a respective capacitor.

Abstract: Successive-approximation-register (SAR) analog-to-digital conversion technique continues to be one of the most popular analog-to-digital conversion techniques, due to their versatility, which allows providing high resolution output or high conversion rates. In addition, SAR analog-to-digital converters (ADC) have a modest circuit complexity that results in low-power dissipation. A SAR ADC is, typically, composed of a single comparator, a bank of capacitors and switches, in addition to, a control digital logic. However, the comparator input capacitance is input-signal dependent, and hence introduces non-linearity to the transfer characteristics of the ADC. A simple technique is devised to significantly reduce this non-linearity, by pre-distorting the sampled-and-held input signal using the same comparator input capacitance.

Abstract: Apparatuses including input buffers and methods for operating input buffers are described. An example input buffer includes a plurality of input buffer circuits, each receiving input data and activated by a respective clock signal. An input buffer circuit includes a decision feedback equalizer (DFE) having adjustable capacitances and reference capacitances to set a reference level of the input buffer circuit. The capacitance of the adjustable capacitances may be set by a code. The DFE provides a capacitance of the adjustable capacitances to a first sense node and further provides a capacitance of the reference capacitances to a second sense node to set the reference level of the input buffer circuit. The input buffer circuit provides output data based on the input data and the reference level set by the DFE.

Abstract: This application relates to time-encoding modulators (TEMs). A TEM receives an input signal (SIN) and outputs a time-encoded output signal (SOUT). A filter arrangement receives the input signal and also a feedback signal (SFB) from the TEM output, and generates a filtered signal (SFIL) based, at least in part, on the feedback signal. A comparator receives the filtered signal and outputs a time-encoded signal (SPWM) based at least in part on the filtered signal. The time encoding modulator is operable in a first mode with the filter arrangement configured as an active filter and in a second mode with the filter arrangement configured as a passive filter. The filter arrangement may include an op-amp, capacitance and switch network. In the first mode the op-amp is enabled, and coupled with the capacitance to provide the active filter. In the second mode the op-amp is disabled and the capacitance coupled to a signal path for the feedback signal to provide a passive filter.

Abstract: In certain aspects, an analog-to-digital converter includes a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, and a comparator including a first input, a second input, and an output. The analog-to-digital converter also includes a switch circuit including a first input coupled to the first capacitive DAC, a second input coupled to the second capacitive DAC, a first output coupled to the first input of the comparator, and a second output coupled to the second input of the comparator. The analog-to-digital converter further includes a first switch coupled between the output of the comparator and the first input of the comparator, and a successive approximation register (SAR) coupled to the output of the comparator, the first capacitive DAC, and the second capacitive DAC.

Abstract: An imaging system includes: an imaging device and a processing device mounted in a vehicle. The imaging device includes: a first pixel coupled to a first signal line, a second pixel coupled to a second signal line, the second signal line is different from the first signal line, a first latch that is coupled to the first signal line, and stores a first digital code, a second latch that is coupled to the second signal line, is adjacent to the first latch, and stores a second digital code, a transfer section that transfers digital codes outputted from the first latch and the second latch, and a diagnosis section that performs diagnosis processing on the basis of the digital codes transferred from the first latch and the second latch. The processing device restricts the function of controlling the vehicle on the basis of a result of the diagnosis processing.

Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.

Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.

Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.

Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.

Abstract: The present application provides a vector quantization digital-to-analog conversion circuit, for converting a digital signal to an analog signal, characterized by includes a vector quantization circuit, configured to receive the digital signal and generate a vector quantization signal; a data weighted averaging circuit, coupled to the vector quantization circuit, including a plurality of data weighted averaging sub-circuits, configured to receive the vector quantization signal to generate a plurality of data weighted averaging signals; and a digital-to-analog conversion circuit, coupled to the data weighted averaging circuit, including a plurality of digital-to-analog conversion sub-circuits, configured to receive the data weighted averaging signal to generate the analog signal.

Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

Abstract: A remote node includes a first node input, a second node input, and an optical switch. The optical switch includes a first switch input optically coupled to the first node input, a second switch input optically coupled to the second node input, a first switch output switchably coupled to the first switch input or the second switch input, and a second switch output switchably coupled to the first switch input or the second switch input. The remote node includes a photodiode optically coupled to the second switch output, and a capacitor electrically coupled to the photodiode and the optical switch. When the first switch input is switchably coupled to the first switch output, the second switch input is switchably coupled to the second switch output. Light received by the second switch input passes out the second switch output to the photodiode. The photodiode charges the capacitor to a threshold charge.

Abstract: A display device is disclosed. The display device includes a display panel including data lines, panel lines, scan lines, and pixels, a power circuit configured to output a reference voltage for initializing subpixels of the pixels, a plurality of branch lines configured to divide a path of the reference voltage into a plurality of paths, and a switch circuit configured to switch a path between the branch lines and the panel lines in response to a switch control signal. The switch circuit changes the path between the branch lines and the panel lines at intervals of predetermined time.

Abstract: Methods and apparatuses for chopping a successive approximation register (SAR) analog-to-digital converter (ADC). The ADC generally includes a comparator comprising a first input and a second input; a switch connected between the first and second inputs of the comparator; a first capacitive array having a first terminal selectively coupled to the first input of the comparator; a second capacitive array having a first terminal selectively coupled to the second input of the comparator; and a reference buffer selectively coupled to second terminals of the first and second capacitive arrays and configured to apply inverse digital codes to the first and second capacitive arrays, wherein the switch is configured to short the first and second inputs of the comparator while the inverse digital codes are being applied to the first and second capacitive arrays such that charges of the first and second capacitive arrays are redistributed via the reference buffer.

Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.

Abstract: According to various embodiments, a multi-slope converter can have the following: an integrator circuit having a charge store; a clocked comparator; a sensor circuit having a capacitor arrangement and a charging circuit for pre-charging the capacitor arrangement, a discharging circuit; a switch arrangement and a controller circuit for actuating the switch arrangement based on a clock signal; wherein the controller circuit is set up to actuate the switch arrangement such that, alternately: in an integration cycle electrical charge is transferred from the capacitor arrangement of the sensor circuit to the charge store of the integrator circuit, and in a deintegration cycle the charge store of the integrator circuit is discharged by means of the discharging circuit, wherein after the integration cycle a residual charge remains stored in the charge store of the integrator circuit and is taken into consideration during a subsequent integration cycle.

Abstract: An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution.

Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

Abstract: An Analog-to-Digital Converter (ADC) device includes an input interface and conversion circuitry. The input interface is configured to receive an analog input signal. The conversion circuitry is configured to convert the analog input signal into a digital word by performing a sequence of iterations to determine respective bits of the digital word, wherein the sequence (i) progresses in descending order of bit significance of the bits, from a Most Significant Bit (MSB) to a Least Significant Bit (LSB), and (ii) repeats evaluation of a predefined number of Least-Significant Bits (LSBs) of the digital word multiple times, and determining a final value of the digital word by averaging the repeatedly-evaluated LSBs.

Abstract: A current-mode analog-digital conversion (ADC) circuit directly samples and digitizes an input signal in the current domain; the input signal may be a current signal or a photonic signal. Input capacitors may be coupled to the current source by a series of switches and configured to store a target charge. The target charge may be compared to a reference voltage by comparators of the system to generate digital output. The current-mode ADC circuit may be adapted to flash, successive-approximation, and pipeline architectures, or embodied in a photonic receiver incorporating current-mode ADC circuits configured to sample and digitize photonic signals.

Abstract: A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.

Abstract: An analogue amplification device comprises a first stage with a common base or gate transistor that receives the modulated input current on its emitter or its source and the output signal of this first stage corresponds to the signal of the collector, a second stage formed by a follower amplifier comprising a transistor with a common collector or drain setup, a third stage that comprises a transistor with a common emitter setup, and a fourth stage that is an amplifying stage with means allowing the realization of, on the one hand, an amplification, and on the other hand, a matching of impedance. The device can be applied to a laser anemometer with optical retro-injection.

Abstract: Provided is an analog-to-digital converting device. The analog-to-digital converting device may include a determination circuit that determination whether a reference digital signal or a determination digital signal obtained by conversion of a reference voltage or a determination voltage matches a test pattern for the reference voltage, and it is possible to monitor whether the analog-to-digital converting device normally operates, according to whether there is matching.

Abstract: The present invention relates to a two- or multiple-stage analog to digital converter. The converter preferably includes an incremental ADC in the first stage. The incremental ADC comprises an integrator and a comparator. After the predefined number of comparisons performed by the comparator, the output of the integrator appropriately scaled is provided to the second stage where it is further sampled. In particular, the scaling gain is inversely proportional to the integrator gain. The second ADC performs the conversion of the remaining least significant bits and then the output of both stages is combined. Moreover, a calibration and correction approaches are provided for the multi-stage ADC.

Abstract: A photoelectric conversion device includes analog signal output units including pixels and configured to output analog signals based on pixels, and signal processing units. Each of the signal processing units is provided correspondingly to one of the analog signal output units and including a gain application unit configured to apply a gain to an analog signal by using only passive elements and an AD conversion unit. In the gain application unit, a portion that contributes to application of a gain to the analog signal is constituted only of passive elements. The gain application unit selectively outputs a first amplified signal obtained by applying a first gain to the analog signal or a second amplified signal obtained by applying a second gain to the analog signal smaller than the first gain. The AD conversion unit converts, from analog to digital, the first or second amplified signal.

Abstract: Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2^M) times the reference voltage to support 2^M oversampling of the input voltage.

Abstract: An arrangement for reading out an analog voltage signal includes a voltage signal input for applying the analog voltage signal thereto, a reference unit configured to generate an analog reference voltage, and a converting unit configured to convert an analog input signal into a digital output signal. To enable online self-calibration of the arrangement, the arrangement includes a superposition unit configured to receive the analog voltage signal and the analog reference voltage. The superposition unit includes a modulation unit configured to generate a modulated reference voltage from the analog reference voltage. The superposition unit is configured to generate a combined analog signal by superimposing the modulated reference voltage onto the analog voltage signal, and to forward the combined analog signal to the converting unit.

Abstract: A converter with an additional DC offset includes a switch circuit, a first capacitor, a plurality of additional capacitor cells and an operational amplifier. The converter uses a first additional capacitor cell and a second additional capacitor cell having a capacitor difference with the first additional capacitor to store two charges having different polarity and magnitude with each other, and further generate an inverted DC offset according to a difference between the two charges to compensate a DC offset.

Abstract: A multi-stage Successive-Approximation Register (SAR) pipeline Analog-to-Digital Converter (ADC) has an amplifier between two switched capacitor networks, each controlled by a SAR. The load capacitance of the amplifier is magnified due to the amplifier's gain. This magnified load capacitance can disproportionately increase power consumption. The back plates of the second-stage switched capacitors are connected to the amplifier input using a feedback switch during an amplification phase, so that the second-stage switched capacitors are connected between the input and output of the amplifier as a feedback capacitor, rather than a load capacitor. Reset switches are added to drive both plates of the second-stage switched capacitors to ground during a reset phase before the amplification phase. Thus the second-stage switched capacitors function as both the feedback capacitor and as the switched capacitors controlled by the second SAR.

Abstract: A circuit contains a successive approximation register and an adjustable capacitor with a set input for adjusting a capacitance value of the adjustable capacitor. Moreover, it comprises a comparator having an input coupled to a terminal of the adjustable capacitor, and with an at least one output, wherein at least one of the outputs of the comparator is coupled to an input of the successive approximation register. The circuit also includes an analog input which is coupled to a terminal of the adjustable capacitor. The circuit may be set into a first operating state and a second operating state, wherein an output of the circuit is controlled in the first operating state by the successive approximation register and is not controlled in the second operating state by the successive approximation register, but by the comparator.

Abstract: An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.

Abstract: An analog-to-digital converter (ADC) utilizing a capacitor array during multiple conversion stages and amplifier sharing across multiple lanes. In various embodiments, the ADC includes N lanes, each of the lanes including a capacitor array. A plurality of switches coupled to each capacitor array selectively redistributes a sampled charge during N clock phases corresponding to N conversion stages, the conversion stages including a sampling stage performed on an analog input signal, at least one quantization stage, and N?2 multiplying digital-to-analog conversion (MDAC) stages for generating residue voltages. The MDAC stages utilize a plurality of N?2 amplifiers shared by the N lanes. In operation, each amplifier may be used in an interleaved manner to support, during a given clock phase, an MDAC stage of one of the lanes of the ADC. Likewise, one or more comparators of a lane may be leveraged to perform multiple quantization stages during the N clock phases.

Abstract: An electronic device may have one or more analog-to-digital converters (ADCs). The ADCs may be used in digitizing signals from an image sensor. In order to ensure that input signals received by an ADC are not clipped, the input signals may be positively or negatively offset by a desired amount. Offsetting the input signals may ensure that the offset input signals wall within the acceptable input range of the ADCs. Offset injection may be accomplished using capacitors that are also used for analog-to-digital conversion. As an example, the ADC may be a successive approximation-type ADC that uses capacitors in a binary search for the digital value most accurately representing an input analog value. The capacitors of the ADC may be used for the successive approximation process and for offset injection. The offset injection may be digitally canceled out following digitization of the input analog signal.