Bit Represented By Pulse Width Patents (Class 341/53)
  • Patent number: 10911086
    Abstract: A receiver according to an embodiment includes a receiver circuit to receive a transition in a first direction, a second transition after the first transition in a second direction, and a third transition after the second transition in the first direction and a fourth transition in the second direction of a signal. The receiver circuit is adapted to determine a first time period between the first and third transitions and to determine a second time period between the second and fourth transitions. The receiver circuit is adapted to determine a datum based on at least one of the first time period and the second time period. Furthermore, the receiver is adapted to indicate an error, if the determined first and second time periods do not fulfil a predetermined verification relationship.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 2, 2021
    Assignee: Infineon Technologies AG
    Inventors: Dirk Hammerschmidt, Wolfgang Scherr
  • Patent number: 10613517
    Abstract: This method for controlling an industrial robot comprising a moving robot arm provided with at least one electric motor suitable for moving this robot arm includes the following steps: a) the execution (1000), by a central unit, of a control program of the robot arm and, in response, the calculation and sending of position instructions of the robot arm; b) generation (1004) of supply voltages of the motor by an axis controller as a function of the calculated position instructions, implementing cascading regulators including at least one entry point receiving an input signal; and c) controlling (1006) the motor with the generated supply voltages. During step b), a sound excitation signal is superimposed with the input signal of one of the regulators to form a composite signal, the supply voltages being generated as a function of the composite signal.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 7, 2020
    Assignee: STAUBLI FAVERGES
    Inventors: Etienne Allardice, Stephane Delor
  • Patent number: 10615703
    Abstract: A DC/DC converter, including a piezoelectric element; a first switch, coupling a first electrode of the piezoelectric element to a first terminal of application of a first voltage; a second switch, coupling the first electrode of the piezoelectric element to a first terminal of supply of a second voltage; and at least one third switch connecting the first electrode to a second electrode of the piezoelectric element, said switches being cyclically controlled, at an approximately constant frequency with, between each turning-on of one of the switches, a phase where all switches are off.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Ghislain Despesse, Benjamin Pollet
  • Patent number: 10565156
    Abstract: Embodiments are directed to apparatuses and methods involving communication between a first circuit and a second circuit over a wired-data bus. An example apparatus includes an integrated circuit (IC) chip within one of the first and second circuits and a logic circuit. The IC has a first data-communication port and a second data-communication for connection to respective first and second conductors of the wired-data bus. The logic circuit communicates a code multi-bit word out of a set of code multi-bit words over the wired-data bus by using signal transitions communicated on the first and second conductors. The code multi-bit word conveys clocked data bits indicated by the signal transitions, and information unique relative to other ones of the set of code multi-bit words by a known sequential pattern of the signal transitions defined relative to timing associated with the clocked data bits.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 18, 2020
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 10381927
    Abstract: The disclosure describes a DC-DC switching converter providing a peak-current servo, employing a pulse-frequency modulation (PFM) control signal and a constant on-time. A Buck, Boost, Buck-Boost, or similar switching converter that supports PFM mode is required, using a fixed on-time scheme for PFM. A final value of the coil current is sampled, and the sampled value of the coil current is compared to a target value for the coil current, to establish whether it is greater or less than the target value. The on-time of the high side device is adjusted to bring the final value of the coil current closer to the target value, using an adaptive coil current measurement.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: August 13, 2019
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Mark Childs
  • Patent number: 10206258
    Abstract: A circuit includes: a plurality of memory locations configured to store pulse width modulation (PWM) signal generation data, the memory locations being arranged in N sets of memory locations, each including i channel memory locations, each channel memory location being configured to store a respective duty-cycle value for a respective one of N PWM modulation patterns; a selection circuit configured to selectively access a selected set of the sets of memory locations; a buffer circuit configured to store the PWM signal generation data from the channel memory locations of the selected set; and a finite state machine configured to receive PWM signal generation input data indicative of a plurality of PWM modulation patterns with a respective plurality of duty-cycle values, the finite state machine configured to activate the selection circuit to load the PWM signal generation data from the channel memory locations of the selected set to the buffer circuit.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: February 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ignazio Cala', Santi Carlo Adamo
  • Patent number: 9819417
    Abstract: The present invention can operate a reflective semiconductor optical amplifier at ultrahigh speed using a polar return-to-zero (RZ) modulation method, and operate a reflective semiconductor optical amplifier (RSOA) whose modulation bandwidth is limited at ultrahigh speed by generating signals vertically symmetrical using a newly suggested polar RZ signal generator when generating an amplitude modulation signal at a transmission end. The present invention can overcome the problem that a modulation speed cannot be increased to 10 Gb/s or above due to signal distortion by inter-symbol-interference when generating an ultrahigh speed amplitude modulation signal using an RSOA of low price having a very narrow modulation bandwidth in an RSOA-based optical network.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 14, 2017
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yun Chur Chung, Hyun Kyu Shim, Hoon Kim
  • Patent number: 9735661
    Abstract: A controller for controlling a power converter is described. The controller may be configured determine a parameter value associated with the power converter, compare the parameter value to a predefined value, and change the conduction mode of the power converter based on the comparison.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andriyanto Halim, Yew Onn Wong, Teng Long Neo
  • Patent number: 9628255
    Abstract: A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 18, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Zaher Baidas, Bogdan Staicu, Menno Tjeerd Spijker
  • Patent number: 9172394
    Abstract: A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: October 27, 2015
    Assignee: Actiwave AB
    Inventors: Erik Lindahl, Pär Gunnars Risberg
  • Patent number: 9124187
    Abstract: A control device of an insulation type DC/DC converter includes a shunt regulator that detects an error in output voltage at the secondary side of a transformer, a photocoupler that transmits the detected error voltage to the primary side of the transformer, and a DPWM control unit on the primary side that generates a control pulse signal having a pulse width at a duty ratio based on the error voltage. The DPWM control unit includes an A/D conversion circuit, an A/D output stabilization circuit, a dither circuit, and a DPWM circuit. The A/D output stabilization circuit is provided after the A/D conversion circuit, and the output end of the A/D output stabilization circuit is connected to the input end of the dither circuit.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: September 1, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tetsuya Kawashima
  • Patent number: 9118306
    Abstract: An oversampling method for data signal includes oversampling data strobe signal and data signal according to sampling phases to generate first and second sampling results, performing edge detection on the first and second sampling results to obtain first and second edge positions where edges are detected, calculating and storing first offset according to the first edge position and the corresponding second edge position when the second edge position are obtained, using first offset obtain in a previous sampling cycle as the first offset in a current sampling cycle when the second edge position aren't obtained, calculating first sampling point according to the first edge position; calculating second sampling point according to the first sampling point and the corresponding first offset, and selecting and outputting the corresponding second sampling results according to the second sampling point.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 25, 2015
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Ye Liu
  • Publication number: 20150015426
    Abstract: A signal conversion system and method for converting an input signal to a pulse width modulated signal is disclosed. The signal conversion system includes a sample rate converter coupled with an associated pulse width modulation (PWM) module. A hardware and power efficient signal conversion system for resampling an audio input signal with an arbitrary sample rate to a pulse width modulated output audio signal for use in an audio processor and/or reproduction is disclosed. The signal conversion system may be particularly suitable for use in a battery operated consumer electronics device.
    Type: Application
    Filed: March 6, 2013
    Publication date: January 15, 2015
    Inventors: Erik Lindahl, Pär Gunnars Risberg
  • Publication number: 20140353378
    Abstract: A method of decoding an encoded signal includes steps of receiving the encoded signal, creating a decoding signal by delaying the encoded signal by a predetermined amount of time ?, sampling the encoded signal using the decoding signal, and determining a value of each of a plurality of decoded bits represented by the encoded signal based on the sampling. Also, a method of operating a shift register wherein the shift register has an initialization state wherein a first binary symbol is stored in a first position and a second binary symbol different than the first binary symbol is stored in each of one or more intermediate positions and a last position. The method includes determining that the shift register is full responsive to detecting that the first binary symbol has been stored in either one of the intermediate positions or the last position.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 4, 2014
    Applicant: UNIVERSITY OF PITTSBURGH-OF THE COMMONWEALTH SYSTEM OF HIGHER EDUCATION
    Inventors: MARLIN H. MICKLE, VYASA SAI, AJAY OGIRALA
  • Patent number: 8811467
    Abstract: A finite sequence of code values is formed, and can be used for example in communications or remote sensing. A code value in said finite sequence of code values has a validity period specific to that code value. There are code values of different validity periods in said finite sequence of code values. Each of said validity periods is longer than or equal to a predetermined minimum baud length.
    Type: Grant
    Filed: June 28, 2010
    Date of Patent: August 19, 2014
    Assignee: Fracticode Ltd.
    Inventor: Juha Vierinen
  • Patent number: 8774263
    Abstract: A transmitter (TX) for transmitting a pulse density modulated signal comprises means (SDM) for generating a pulse density modulated input signal (SI) and an encoder (ENC). The encoder (ENC) comprises a first input for receiving the pulse density modulated input signal (SI) and a second input for receiving additional information (AI) comprising at least one data bit. The encoder (ENC) is configured to generate a multi-bit telegram (TG) on the basis of the additional information (AI), the telegram (TG) comprising a predefined bit-sequence, and to replace an appropriate number of consecutive bits of the input signal (SI) with the telegram (TG) in order to generate an output signal (SO).
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: July 8, 2014
    Assignee: ams AGe
    Inventors: Richard Forsyth, Thomas Fröhlich, Matthias Steiner
  • Patent number: 8731120
    Abstract: A method and apparatus is provided for reducing interference in a communication system. A feedback-controlled biased inverting limiter is used to reduce interference power by trapping the interfering signal, while passing the wanted signal through to the output. The amplitude trap triples the frequency of a signal component of a particular amplitude, thus shifting it out of the communication band and into the stopband of the receiver or transponder filter. The feedback-controlled biased inverting limiter uses a hard limiter, window comparator, feedback loop, and an exclusive NOR gate to trap the interfering signal, while allowing the wanted signal to pass through to a receiver.
    Type: Grant
    Filed: April 7, 2012
    Date of Patent: May 20, 2014
    Inventor: Cameron M. Pike
  • Publication number: 20140036987
    Abstract: A decoder for decoding an input signal coded with a pulse width modulation code as a line code to an output signal in a binary code, has a first memory, a first timer, a determination circuit and a first controller. The information on a duty duration of the PWM code, corresponding to at least one kind of the output signals, is stored on the first memory. The first timer has a capacity to measure the duty duration of the input signal. The determination circuit has a capacity to determining which kind of the output signals corresponds to the input signal, on the basis of the information stored on the first memory and the duty duration measured with the first timer. The first controller has a capacity to updating the information stored on the first memory, on the basis of the determination result and the measured duty duration.
    Type: Application
    Filed: July 30, 2013
    Publication date: February 6, 2014
    Applicant: DENSO CORPORATION
    Inventors: Hideki Kashima, Tomohisa Kishigami, Naoji Kaneko
  • Patent number: 8643514
    Abstract: Methods for decoding data are disclosed herein. The data is coded such that a transition from a first state to a second state represents a logic one and a transition from the second state to the first state represents a logic zero. An embodiment includes determining a pulse width for a first pulse and measuring the width of a second pulse, wherein the second pulse occurs directly after the first pulse. The method continues with comparing the second pulse width to at least one first predetermined period and assigning a value to the second pulse width when the second pulse width is within at least one of the first predetermined periods. The method also includes assigning a value to the second pulse width based on the value assigned to the first pulse width when the second pulse width is not within at least one of the first predetermined periods.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Fujhara Nobuo, Kenichi Tashiro
  • Patent number: 8421652
    Abstract: A decoding circuit is adapted for decoding an input signal. The input signal includes at least a break and the time length of the break is a preset time. The decoding circuit includes a decoding unit and a detecting unit. The detecting unit detects whether the voltage level of the input signal is kept at a specific logic level for more than the preset time. If the input signal is kept at the specific logic level for more than the preset time, the detecting circuit, according to the voltage level of the specific logic level, outputs the input signal or the inverted input signal to the decoding unit so as to perform a decoding process.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: April 16, 2013
    Assignee: MY-Semi Inc.
    Inventors: Chun-Ting Kuo, Chun-Fu Lin, Cheng-Han Hsieh
  • Patent number: 8384568
    Abstract: Decoder circuits and methods down-sample the samples that oversample an input signal having a differential Manchester encoding. A first input port receives first, second, and third samples. A second input port receives a state indicating whether a clock transition or a data transition precedes the first, second, and third samples. A third input port receives first, second, and third down-sampled bits. A detector circuit is configured to generate a detection signal indicating a presence of a short pulse within the samples when the state indicates the clock transition and the second and third down-sampled bits are equal and differ from the first down-sampled bit and the third sample. A generator circuit is configured to generate a fourth down-sampled bit that equals the third sample when the detection signal indicates the presence of the short pulse, and that equals the second sample when the detection signal does not indicate the presence.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: February 26, 2013
    Assignee: Xilinx, Inc.
    Inventors: Sarvendra Govindammagari, Veerender Kumar Soma, Heramba Aligave, Douglas M. Grant
  • Patent number: 8284830
    Abstract: Systems and methods for the demodulation of pulse edge modulated signals for communications systems which are useful in body implanted electronics. A pulse edge modulated signal is generated by retarding or advancing each pulse edge of a carrier to be modulated relative to its original position in time, depending on the state of the digital bit to be modulated on that edge. Each modulated edge of a pulse edge modulated signal is demodulated by determining the position in time of the modulated edge relative to the original respective position of the modulated edge prior to modulation.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: October 9, 2012
    Assignee: Alfred E. Mann Foundation For Scientific Research
    Inventors: Edward K. F. Lee, Eusebiu Matei
  • Patent number: 8237980
    Abstract: A serial I/F has: a FIFO portion to which m- or n-bit (m<n) parallel data is written based on PCLK; a FIFO reader that reads the parallel data written to the FIFO portion m bits at a time based on FCLK; a parallel/serial converter that converts the m-bit parallel data read by the FIFO reader into 1-bit serial data based on PLLCLK; a PLL circuit that produces PLLCLK by multiplying PCLK by a factor of m or n; and a frequency divider circuit that produces FCLK by dividing the frequency of PLLCLK by m. Here, the multiplication factor of the PLL circuit is so controlled as to be changed according to the number of bits of the parallel data written to the FIFO portion. This makes it possible to flexibly deal with parallel inputs having different bus widths without unduly increasing a device scale and cost.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: August 7, 2012
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuhiko Murata, Masayu Fujiwara, Tomoki Yamamoto, Takeshi Matsuzaki
  • Patent number: 8207877
    Abstract: An apparatus for transferring serial data (e.g., a serial interface using a single wire) generally includes a detector configured to detect a first level time period and a second level time period of an input signal, and a computing unit configured to compute a duty or duty cycle of the input signal and generate an output signal based on the duty or duty cycle.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 26, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Chang Woo Ha, Sung Hoon Bea, Sang Heum Yeon
  • Patent number: 7991359
    Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventor: Hirotaka Tamura
  • Patent number: 7961120
    Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.
    Type: Grant
    Filed: April 27, 2010
    Date of Patent: June 14, 2011
    Assignee: Marvell International Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 7952508
    Abstract: Class-D amplifiers have evolved from using binary pulse-width modulation (PWM) modulators to three-level PWM modulators. Three-level PWM drivers for audio applications offer the benefits of eliminating costly elements at the output of an audio system. However, they also introduce increased common-mode interference. Three-level PWM generates three states, but one state has two interchangeable representations which can be scrambled in order to shape the common-mode output spectrum.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: May 31, 2011
    Assignee: Conexant Systems, Inc.
    Inventors: Lorenzo Crespi, Ketan B Patel, Kyehyung Lee
  • Patent number: 7919932
    Abstract: Provided is an apparatus for controlling lighting brightness including a light control unit that generates a control signal for controlling the brightness of a plurality of lightings; a digital signal generating unit that converts a signal corresponding to the control signal at each period so as to generate non-periodic digital signals; and a driving voltage generating unit that generate driving voltages by converting the digital signals into analog signals.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: April 5, 2011
    Assignee: Samsung LED Co., Ltd.
    Inventors: Joon Hyung Lim, Tah Joon Park, Koon Shik Cho, Kwang Mook Lee, Bo Il Seo
  • Patent number: 7822800
    Abstract: The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 26, 2010
    Assignee: Camco Produktions-und Vertriebs GmbH fur Beschallungs-und Beleuchtungsanlagen
    Inventors: Thomas Schulze, Carsten Wegner
  • Patent number: 7800518
    Abstract: A pulse modulation method divides code comprising 4N-bit data into 2-bit units of data. For each pulse signal having a fixed pulse width tw, a code modulated signal is generated by pausing between pulse pause intervals Tr. An adjusted time width of between ½ and 1 times the fixed pulse width tw is taken to be ?t. One of time widths 0, ?t, 2?t, and 3?t is added to a fixed pause period tm of time intervals according to a corresponding value of the 2-bit data. If the sum total time TD of the code modulated signal is an interval of at least [(2tw+2tm+3?t)N+?t], each pulse pause interval Tr is substituted by a pulse pause interval Tr corresponding to the inverted 2-bit data. An inversion flag signal expresses that inversion information is added to the code modulated signal.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: September 21, 2010
    Assignee: SMK Corporation
    Inventor: Kenichi Miwa
  • Patent number: 7782238
    Abstract: A pulse width modulation (PWM) signal generator includes a quantizer for generating a quantized signal by quantizing an input signal, an asymmetric pulse width modulator, and an error correction unit. The asymmetric pulse width modulator generates an asymmetric PWM signal by comparing the quantized signal with a reference signal, with the asymmetric PWM signal being asymmetric with respect to a center of a period of the reference signal. The error correction unit is coupled between the quantizer and the asymmetric pulse width modulator to correct an error generated from the asymmetry of the asymmetric PWM signal. The quantizer is part of a delta sigma modulator having an operating frequency that is twice that of the reference signal.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., ltd.
    Inventor: Yong-Hee Lee
  • Patent number: 7764734
    Abstract: Digital pulse width modulation with variable period and error distribution that improves the tradeoff between resolution and clock speed in pulse width modulation circuits so that a higher resolution can be achieved with a lower clock speed. A preferred method includes, for a signal sample S and each value of P in a range Pmin to Pmax of pulse periods P, determining a pulse width V=round(P*S), where round(P*S) is the closest integer value of P*S, and the magnitude of the error |E|=|S?V/P|, for the value of V (Vopt) and P (Popt) associated with the lowest value of the magnitude of the error |E|, providing an output pulse of a pulse width Vopt during the pulse period Popt, and successively repeating a) and b). Other aspects of the invention may include error distribution, error squelching to prevent idle-tone, idle-noise artifacts, 2-samples-per-pulse and non-uniform sampling and pulsing. Other features are disclosed.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 27, 2010
    Assignee: Winbond Electronics Corporation
    Inventor: Samuel Chi Hong Yau
  • Patent number: 7763843
    Abstract: The controller of the present invention includes an optical navigation system which is responsive to movement, velocity of position of a rotatable platter. The optical navigation system is responsive to rotation of the rotatable platter and is further responsive to at least one degree of freedom of tilting of the rotatable platter. The rotatable platter typically includes a textured pattern so that the optical navigation system can acquire sequential surface images of the textured pattern.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: July 27, 2010
    Assignee: Stanton Magnetics, Inc.
    Inventors: Alan Flum, James Mazur
  • Patent number: 7760120
    Abstract: The present invention relates to a generation method of a variation form of an analogue signal generated by a PWM signal whose cyclic ratio and period are programmable. A signal can thus be generated whose evolution is linear over time. A succession of generation steps of a PWM signal during which different period and cyclic ratio values are applied, as well as pairs have different periods with the same cyclic ratio, thus enabling the analogue signal to be varied with great precision. According to an improvement, each generation step of a new PWM signal with different period and cyclic ratio values is applied over time slots of equal time. The present invention also relates to a generation system of a variable analogue signal implementing the method.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: July 20, 2010
    Assignee: Thomson Licensing
    Inventors: Philippe Mace, Xavier Guitton, Philippe Benezeth
  • Patent number: 7733947
    Abstract: A special data including communication wire continuous dominant levels of a number of N more than the transceiving bit number of n of communication wire continuous dominant levels, set in a character as one unit of communication data, can be transceived by a widely-used serial communication interface such that a predetermined transmission rate is changed to n/N times the transmission rate only when the special data is transmitted, whereby the special data can be easily transceived at a low cost.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: June 8, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Katsuyuki Sumitomo
  • Patent number: 7724161
    Abstract: A noise shaper truncates the widths of pulses it supplies to a pulse-width modulator whose pulse-width modulated signals control a tri-level amplifier. The amplifier is filterless and DC free. Pulses that are narrower than a predefined minimum width are eliminated by the noise shaper. Other pulses are subjected to an algorithm that includes a multitude of ranges, each range defined by a minimum pulse width characterizing a lower bound of that range and a maximum pulse width characterizing an upper bound of that range. Associated with each range is a number of clock cycles defining the modified width of a pulses whose detected width falls within that range. To ensure that delays associated with a feedback loop disposed in the amplifier are accounted for, the reference voltage of a comparator tracks an output voltage of an integrator. Both the comparator and integrator are disposed in the loop.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: May 25, 2010
    Assignee: Marvell International Ltd.
    Inventor: Sasan Cyrusian
  • Patent number: 7706438
    Abstract: A pulse width modulation system including a pulse width modulation stage for generating a pulse width modulated signal in response to an input signal and an other pulse width modulation stage for generating an other pulse width modulated signal in response to an other input signal. Additional circuitry ensures that transitions of the pulse width modulated signal and the other pulse width modulated signal are spaced in time by a selected amount for small levels of the input signal.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: April 27, 2010
    Assignee: Cirrus Logic, Inc.
    Inventors: Johann Guy Gaboriau, John Laurence Melanson, Lingli Zhang, Melvin L. Hagge
  • Patent number: 7701367
    Abstract: A computer-implemented method to decode a digital signal includes following steps. A micro control unit (MCU) receives a digital signal. The MCU reads a low voltage period of the digital signal and stores a time duration of the low voltage period into a first register as a value TL. The MCU reads next high voltage period of the digital signal and stores a time duration of the high voltage period into a second register as a value TH. The MCU reads the value TL of the first register and the value TH of the second register, and computes a ratio TR=TH/TL. The MCU compares the ratio TR with two predetermined values M and N, if TR=M, the decoded result is a logical “1.” If TR=N, the decoded result is a logical “0.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: April 20, 2010
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Sheng-Jie Sang, Liang-Yan Dai
  • Patent number: 7683809
    Abstract: A bit coding method modifies the bit-steam information in such a way as to provide a very high compression during lossless symbol coding and may be used as a preprocessor for Huffman and arithmetic encodings or on its own. A bit rearrangement scheme (BRS) improves the run length within a data symbol set and achieves a more efficient data-to-symbol mapping. The BRS is implemented on the data symbol set in a column-by-column fashion. The BRS can be combined with any available lossless coding scheme, providing for a more efficient lossless bit coding scheme (ALBCS).
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: March 23, 2010
    Assignee: Aceurity, Inc.
    Inventor: Pankaj Patel
  • Patent number: 7626451
    Abstract: A method and accompanying circuitry for asynchronous data demodulation uses sorted pulsewidth measurement based on an asynchronous clock. Lock-on of the data stream by such a system is accomplished by measured pulsewidth, rather than inferred frequency. The method broadly comprises the steps of measuring a temporal aspect of the asynchronous clock, and locking onto the data stream in accordance with the measured periods. In the preferred embodiment, the temporal aspect is a ratio of measured periods. Conveniently, a ratio of 2:1 may be used.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: December 1, 2009
    Inventor: Larry Kirn
  • Patent number: 7626519
    Abstract: Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: December 1, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Lars Risbo
  • Patent number: 7612696
    Abstract: A method and system of decimating a Pulse Width Modulated (PWM) signal (537) is provided. The method includes computing one or more timestamps (553) of the PWM signal (537), the PWM signal being at a first sample rate (567). The one or more timestamps (553) are computed at a second sample rate (568), which is lower than the first sample rate (567). Thereafter, the method generates a plurality of pre-filter signals (557-n) based on each of the one or more timestamps (553) and a plurality of translation factors (555-n). The plurality of pre-filter signals (557-n) is then filtered at the second sample rate (568) using a plurality of Infinite Impulse Response (IIR) filters (560-n) to generate a plurality of intermediate decimated Pulse Code Modulated (PCM) signals (563). The plurality of intermediate decimated PCM signals (563) is combined to generate a PCM signal (569).
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: November 3, 2009
    Assignee: Motorola, Inc.
    Inventor: Poojan A. Wagh
  • Patent number: 7593500
    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: September 22, 2009
    Assignee: Microchip Technology Incorporated
    Inventor: Bryan Kris
  • Patent number: 7586425
    Abstract: A method for coding spatial and quality enhancement information in scalable video coding using variable length codes. Conventional systems have been capable of using variable length codes only with nonscalable video coding, In the present invention, the coded block pattern for each block of information, significance passes, and refinement passes can all be coded with different types of variable length codes. The present invention also provides for a variable length encoder/decoder that dynamically adapts to the actual symbol probability. The encoder/decoder of the present invention counts the number of times each symbol is coded. Based upon these counts, the encoder/decoder selects how many symbols to group when forming a code word. The encoder also uses these counts to select the specific codeword that should be used.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: September 8, 2009
    Assignee: Nokia Corporation
    Inventors: Justin Ridge, Xianglin Wang
  • Publication number: 20090153377
    Abstract: Time to digital converters (TDCs) with high resolution are disclosed. The TDC includes a first time to digital converting module, a selection and time amplifying module, a second time to digital converting module and a decoder, and is applied in estimating a time difference between a first signal and a second signal. As the delay time of the delay units of the time to digital converting modules is the unit of the time difference measurement, the first and second time to digital converting modules are responsible for the integral portion and the fractional portion of the estimated time difference, respectively. Moreover, by introducing the normalization process, the linearity of the converting characteristic of the TDC can be improved; by adding an error detection circuit to the TDC, the possible metastable problem can be prevented.
    Type: Application
    Filed: February 18, 2009
    Publication date: June 18, 2009
    Applicant: MEDIATEK INC.
    Inventor: Hsiang-Hui Chang
  • Patent number: 7515072
    Abstract: A circuit for converting from an input serial pulse code modulated (PCM) digital signal to an output pulse width modulated (PWM) digital signal for driving a switching audio amplifier requiring a pulse width modulated input signal, the circuit comprising a sample rate converter receiving the input serial PCM digital signal at a first sampling frequency and converting the input serial PCM digital signal to a second serial PCM digital signal at a second frequency if the first sampling frequency is lower than the second frequency, a digital filter stage for up-sampling the second serial PCM digital signal to a third frequency and converting the second serial PCM digital signal to a parallel digital signal, a volume control stage receiving the parallel digital signal and generating a volume adjusted parallel digital signal in accordance with a digital volume command control signal, a digital cross-point estimator stage for calculating a cross-point between the volume adjusted parallel digital signal and a digital
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: April 7, 2009
    Assignee: International Rectifier Corporation
    Inventor: Ana Borisavljevic
  • Patent number: 7508899
    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 24, 2009
    Assignee: Microchip Technology Incorporated
    Inventor: Bryan Kris
  • Patent number: 7508901
    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 24, 2009
    Assignee: Microchip Technology Incorporated
    Inventor: Bryan Kris
  • Patent number: 7508900
    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 24, 2009
    Assignee: Microchip Technology Incorporated
    Inventor: Bryan Kris
  • Patent number: 7502436
    Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: March 10, 2009
    Assignee: Microchip Technology Incorporated
    Inventor: Bryan Kris