Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected to a clock source, an edge detection circuit detecting rising and falling edges of the input signal. The edge detection circuit is connected to the up/down counter to start up counting from a reset value upon detection of an edge in a first direction and to start down counting from a current count upon detection of an edge in a second direction. The decoder further comprises a bit value deciding circuit that delivers a first logic value when the count of the up/down counter is above the reset value on detection of an edge in the second direction and delivers a second logic value when the count of the up/down counter is at or below the reset value on detection of an edge in the second direction.

Abstract: Digital audio circuitry including modulation circuitry (35; 135) for generating a pulse-width modulated (PWM) signal from processed pulse-code modulated (PCM) audio signals. The modulation circuitry includes a duration quantizer function (32) that generates a sequence of duration values d(k) from received PCM samples, quantized to integer multiples of periods of a master PWM clock (CLKpwm). The duration quantizer function also produces a feedback PCM value x(k) from each quantized duration value d(k) that is applied to a loop filter (36), the output of which modifies the received PCM sample stream to suppress quantization noise. Transient effects caused by modulation or abrupt changes in the desired PWM period are suppressed by digitally filtering (34; 134) the PWM period sample stream.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A method is disclosed for generating pulse width modulated pulse control signals for controlling switches in a switching power supply. First, a count value is determined of a master clock within a switching cycle of the power supply from beginning to end thereof. A separate state machine providing for each edge in each of pulse control signals and each is operated to generate the associated edge as a function of the sum of a fixed reference count value from the beginning of the switching cycle and a determined count value when the sum is determined to equal the actual count value.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: A switching amplifier system and method is disclosed. In a particular embodiment, a pulse width modulation frame size is determined based on a sample rate of a digital input signal. Data associated with the first digital input signal is modified based on the pulse width modulation frame size. A pulse width modulation signal is generated in response to the modified data.

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract: A cycle time to digital converter comprises a dual delay lock loop, multi phase sampling detector and VDL sampling detector. The dual delay lock loop generates the first voltage corresponding to the first delay time and the second voltage corresponding to the second delay time. The multi phase sampling detector receives first start signal, first stop signal and first voltage to detect a coarse delay time, generates the first group signals according to the coarse delay time, delays the first stop signal by a common delay time to generate the second stop signal, and delays the first start signal by the coarse delay time and the common delay time to generate the second start signal. The VDL sampling detector receives first voltage, second voltage, second start signal and second stop signal for detecting a fine delay time and generates the second group signals according to the fine delay time.

Abstract: In an optical coupled isolation circuit, a PWM encoder encodes a one-bit binary data signal supplied from a sigma-delta analog-digital converter in synchronization with a clock signal of a cycle T to produce a pulse width modulation signal. The pulse width modulation signal includes a narrower pulse having a width of 1/T and a wider pulse having a width of 3/T according to binary codes “0” and “1”. The pulse width modulation signal is transmitted to a decoder as a recovered pulse width modulation signal through a light emitting device, a light detector and an optical recovery circuit. A decoder decodes the recovered pulse width modulation signal at timing of a half of the clock cycle from each rising edge of the recovered pulse width modulation signal. The rising edge is synchronized with the clock signal. Thus, the clock signal and the data signal can be transmitted in one channel.

Abstract: The invention relates to a method and a device for converting a digital, pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein the digital signal PCM, f(t) is multiplied by at least one derivative (f?(t), f?(t), . . . , f(n) (t)) of the signal (f(t)). The invention also relates to a technique for converting a digital pulse-coded signal (PCM) to a pulse-width-modulated signal (PWM), wherein to obtain a sampling rate sufficient for the pulse-width-modulated signal an oversampling of the digital signal is implemented with a first oversampling factor before the conversion and an second oversampling factor after the conversion, such that the product of the oversampling factors before and after conversion of the digital signal to the pulse-width-modulated signal corresponds at least to the value of the required oversampling factor.

Abstract: An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys information that is encoded by a level of the at least one other signal line at n consecutive edge transitions of the clock signal, where n?2.

Abstract: Data from both a positive edge sample and negative edge sample are used to determine a data bit. The primary and secondary clocks capture two copies of the data. A sample is taken with a positive edge of one clock and the negative edge of the other clock each bit period. These two captured data values are combined along with the data value captured by the previous negative edge to determine the data bit value. The captured data may be dynamically de-skewed previous to being clocked into a buffer based on the clock edges sampling the data.

Abstract: A digital pulse-width modulator is provided that receives a digital command input signal and a secondary control input signal and provides a pulse-width-modulated output signal. The pulse-width-modulated output signal comprises a pulse-width that corresponds to an integer number of slots each having a time duration. The integer number of slots corresponds to a value of the digital command signal, and the time duration is determined based upon the secondary control input signal. In one embodiment, the digital pulse-width-modulator comprises a plurality of delay cells arranged in series for propagating a clock signal through the plurality of delay cells. A time delay for each of the delay cells is determined by the secondary control input signal.

Abstract: Dithering for the output of a digital pulse width modulator is provided by a pulse-density modulator formed from an adder incrementing a pulse-density count and generating a carry signal latched to a plus-one generator, which in turn adds a phase-division period to each of one or more selected pulses within a predetermined series of pulses from the digital pulse width modulator. Selected pulses are advanced by triggering a leading edge of the pulse at a time one phase-division period before the system clock edge, allowing trailing edges to be extended and providing minimal latency delay.

Abstract: A data transmission method capable of suppressing communication errors with a simple microcomputer processing is provided. Upon a pulse signal in which specific data is made up of H and L levels, either one of which has a pulse width taken as a first fundamental signal length T1 and the other of which has a pulse width taken as a second fundamental signal length T2 equal to an integer multiple of the first fundamental signal length T1, a correction is performed by increasing or decreasing the second fundamental signal length T2 by a length equal to an integer multiple of a value resulting from dividing the first fundamental signal length T1 of the transmission-side pulse signal by an integer.

Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: The present invention relates to a method for pulse placement to form a binary pulse signal, said binary pulse signal having a constant pulse rate being reciprocal of a constant pulse rate period, comprising the steps of generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period, synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N=0, 1, 2, . . , and selecting said bit clock period individually for successive pulses of said binary pulse signal.

Abstract: Binary information is subjected to RZ encoding and multi-level encoding, and the encoded signal is optically modulated.

Abstract: The present invention relates to the reduction of artifacts introduced by sending data at a higher rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: A multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices in response to changes detected at the bus circuit inputs. The delay penalty associated with leaving the standby mode is overcome by reducing cross-talk induced delay via a cross-talk noise minimization encoding and decoding scheme. A subgroup of bus wires is encoded and decoded, simplifying the encoding, decoding and change detection logic and results in the bus subgroup being taken out of standby mode only when changes occur in one or more of the subgroup inputs, further reducing the power consumption of the overall bus circuit.

Abstract: A circuit, method and microcontroller apparatus for performing an analog to digital conversion with continuously variable resolution is disclosed. The circuit includes a integrating modulator for converting an analog input signal, corresponding to an input voltage, to a digital signal at its output over an integrate time. The circuit also includes a counter with an enable input coupled to the integrating modulator output. The counter accumulates the number of cycles where the digital signal is positive during the sample period and provides a corresponding conversion result. Further, the circuit has a pulse width modulator; its output gates a clock to the counter enable input. The pulse width modulator is user programmable on-the-fly to set said integrate time and said sample period.

Abstract: In digital-to-analog conversion systems, a method and system for increased effective resolution in an N-bit DAC are provided. Additional resolution may be provided in an N-bit DAC by increasing the number of periods that an N-bit PWM may utilize to generate an output train of pulse widths with a desired duty cycle. An increased resolution bits parameter may correspond to the additional bits necessary to provide the increased resolution. An iterative process by which a desired value is converted into a sequence of N-bit control words may be based on a desired analog value and the increased resolution bits parameter. In addition to higher resolution, most of the output pulse AC energy is concentrated at the N-bit PWM basic frequency and above, allowing for simpler analog filtering of the pulse width modulated signal.

Abstract: Pulse width modulation of a digital signal using a nonlinear type of pulse generator is described. The nonlinear pulse generator is characterized by its transfer characteristic which has alternating stable and unstable operating regions. The pulse width modulated signal is generated by varying the operating point between among the unstable and stable operating regions.

Abstract: A communications signal which carries a purely digital wrapper signal and a method and system for generating it and extracting overhead information therefrom. The wrapper signal can be received by a high-performance format-specific receiver at the end of the network as part of the overall payload, but can also be detected by a low-bandwidth payload-bit-rate-insensitive receiver at an intermediate node. This is achieved by using alternating payload and wrapper segments and providing special digital coding on the wrapper segments. Specifically, each wrapper segment consists of a contiguity of signal level sequences, each of which is a multi-bit symbol that encodes a bit in the overhead bit stream. Each of the symbols is thus a signal level sequence having one of two possible transition patterns, with the appropriate symbol being chosen depending on whether the overhead bit is a logic “zero” or a logic “one”.

Abstract: A PWM signal generator and generating method for generating one or two pulses having a pulse width or a total pulse width corresponding to a value represented by a pulse code modulation digital signal and placed in a symmetric positional relationship with respect to the position of one half of a predetermined length. A first pulse and a second pulse are generated in accordance with a value represented by the digital signal. The difference in pulse width between the first and second pulses is output as a first pulse width modulation signal. When the value represented by the digital signal is zero, the first pulse and second pulse are equal in pulse width. When the value represented by the digital signal changes by one, one of the first and second pulses does not change in pulse width, while the other of the first and second pulse changes in pulse width by two slots.

Abstract: A touch screen display circuit is disclosed which includes means for measuring a voltage at two separate input terminals which represent a location on a touch screen where pressure was applied. The display circuit includes means for defining a time period during which the voltage is measured and means for converting the measured voltage to a digital value. The means for measuring a voltage includes an amplifier and a capacitor which are configured as an integrator. The means for converting comprises a counter that measures an amount of time required for the capacitor to dissipate its charge. A touch screen display system having a touch screen which includes first and second sheets of conductive materials positioned in a spaced apart relationship is disclosed.

Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2M possible data values of an M-bit group corresponds to one of 2M distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and using the delayed outputs to clock flip-flop registers to sample the non-delayed signal. The registered output is interpreted by logic gates to obtain the corresponding M-bit groups. The decoder circuit may have two substantially identical pulse width determining blocks, one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.

Abstract: A method and apparatus for providing information from a speed and direction sensor is disclosed. The method and apparatus detect the presence of a ferromagnetic object as it moves past a sensor. The sensor determines speed and direction information regarding the ferromagnetic object, and further provides information relating to the environment surrounding the sensor or object, such as the status of an air gap between the sensor and the moving object, and the temperature of the environment in which the sensor or object is disposed.

Abstract: The present invention relates to a coding apparatus for encoding data represented by 8 bit input symbols into 12 bit output codes for serially transmitting the codes along a communication channel, the codes being represented in the channel by signals having a limited minimum and maximum pulse width and sampled by a receiver at each receiver's clock period. The invention reduces artifacts introduced by sending data at a higher payload rate than the bandwidth of the communication channel, such as the voltage and current offsets introduced in the data at the receiver as a function of the preceding data.

Abstract: The invention relates to a method for encoding a stream of bits of a signal relating to a binary source into a stream of bits of a signal relating to a binary channel, the binary source comprising a main source and a secondary source, the main source being encoded in a main channel and the secondary source being encoded in a secondary channel, the secondary channel being embedded in the main channel in order to form the binary channel, wherein the binary channel is divided in blocks, each block comprising a number of user bits and that in at least one of the blocks the secondary channel also is used for encoding non-user bits.

Abstract: A method, system, and apparatus for remotely calibrating data symbols received by a radio frequency identification (RFID) tag population are described. Tags are interrogated by a reader, which may be located in a network of readers. The reader transmits data symbols to the tags. Tags respond to the interrogations with symbols that each represent one or more bits of data. To calibrate the tags, the reader transmits a plurality of pulses of different lengths to the tag population. The tags receive the plurality of pulses. A characteristic of each pulse, such as a pulse length, is stored by the tags. The stored pulse lengths are used to define different data symbols that are subsequently received by the tags from the reader.

Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.

Abstract: An ultra-wideband pulse modulation apparatus, system and method is provided. The pulse modulation method increases the available bandwidth in an ultra-wideband, or impulse radio communications system. One embodiment of the present invention comprises a pulsed modulation system and method that employs a set of different pulse transmission, or emission rates to represent different groups of binary digits. The modulation and pulse transmission method of the present invention enables the simultaneous coexistence of the ultra-wideband pulses with conventional carrier-wave signals. The present invention may be used in wireless and wired communication networks such as CATV networks.

Abstract: A method and apparatus (20) for adjusting a duty cycle of a binary signal (36) having a high phase and a low phase. The method includes applying a delay to the binary signal to create a delayed signal, and performing a Boolean logical operation on the binary signal and the delayed signal, so as to generate an output signal (40, 52) having a duty cycle different from the duty cycle of the binary signal.

Abstract: To correct non-linearity and noise in the conversion of a pulse code modulated signal (PCM) into a uniform pulse width modulated signal (UPWM), a model is made of the known non-linearity in the conversion by dividing a plurality of non-linearity components in the model, where the polynomial components are separately weighed with filter coefficients. The model is used as a basis for the construction of a filter of the Hammerstein type whose non-linear parts consist of a division of the PCM signal into a plurality of powers, and whose linear parts are approximated by means of the model made. With the circuit of the invention it is now possible to construct a purely digital amplifier which has a great efficiency, low weight, etc.

Abstract: A method and apparatus for achieving relatively low compression ratios based on the realization of using a longer history and longer common strings of the input data stream as an initial evaluation of the input data prior to applying a particular compression process. More particularly, the input data is preprocessed by applying string-matching to the extract long common strings. The input data is divided into a series of blocks with each individual block having a uniform size, illustratively, 1000 characters in length. Further, a so-called fingerprint is computed and stored for each block. Thereafter, the input data stream is traversed and comparison is made between a particular set of character of the input stream and the computed fingerprints. In particular, the input stream is traversed as a function of a sliding window wherein the present window of characters of the input is compared to the computed fingerprints.

Abstract: A one-wire protocol is described, wherein a one-wire bus has either a wired-AND configuration or a wired-OR configuration. In this protocol, data is encoded using time modulation. In one embodiment, two devices communicate with each other through the one-wire bus. One device is configured to transmit data by driving the one-wire bus high, while the other device is configured to transmit data by driving the one-wire bus low. In a preferred embodiment, transmission of data by each of the two devices is interleaved in such a fashion so that there is a bit-for-bit exchange between one device and the other device. In another embodiment, more than two devices may communicate through the one-wire bus.

Abstract: A method for modulating digital data and apparatus therefor is capable of determining a digital data stream coded by Run Length Limited swiftly and precisely so as to record data in a recording medium. The digital data modulating method includes the steps of comparing a preset critical value and DSV (Digital Sum Value) of a certain digital data stream, computing the penalty of the digital data stream by multiplying the number of the time that the DSV of the digital data stream is larger than the critical value by a preset weight value of the critical value, comparing the penalty of the digital data and a penalty of another digital data stream and selecting a digital data stream with a smaller penalty as the digital data stream. Therefore, with the method for modulating digital data and apparatus therefor, the digital data stream which will be modulated among a number of digital data streams can be selected precisely and swiftly.

Abstract: A system uses an event based equivalent time sampling method for ascertaining a value of each bit of a data frame repeated in a digital signal of indeterminate phase. The system measures time intervals between rising edges of the digital signal and a reference time and between falling edges of the digital and that reference time in response to pulses of a periodic arming signal. The measured time intervals are then normalized to equivalent time intervals and those intervals analyzed to determine values of each bit of the data frame.

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Abstract: A PWM converting circuit includes a pulse generator for generating two pulse signals for each bit of a basic clock pulse train in response to the value of digital input data, and a differential amplifier for outputting a differential amplification component between the two pulse signals as a PWM signal. The pulse generator varies a pulse width of one of the two pulse signals on a bit-by-bit basis of the basic clock pulse train in response to the value of the digital input data, and holds a level of the other of the two pulse signals throughout the entire bits of the basic clock pulse train within the period of the pulse of the PWM signal.

Abstract: A method for transmitting data of a wireless keyboard device having a track-ball, which transmits track-ball data and keyboard data more effectively, and thereby simplifies the process and reduces the current consumption of the keyboard device. The data transmission method transmits a leader signal composed of five chips including three consecutive low signals followed by a high signal and a low signal, thereafter transmits data that contains track-ball data and keyboard scan data recorded in the same data format, and, instead of check-sum code, allocates the complementary value of the code value of the third byte (Byte3) into the fourth byte (Byte4) and transmits it so that the transmission error can be checked by simply comparing the third byte and the fourth byte.

Abstract: A pulse density modulator generates output pulses that are optimized as to their even distribution over time. More particularly, the invention represents parallel or serial digital input signals as serial binary output signals, where the binary output pulses are evenly spaced over time to the greatest extent possible. The output signal includes a pattern that repeats during successive “cycles.” The number of pulses in each cycle varies in proportion to the magnitude of the digital input signal. When a digital input signal is provided to an accumulator, the accumulator repeatedly updates a current N-bit sum value by adding the digital input signal thereto. According to this computation, the accumulator either (1) provides a first prescribed signal on a carry output if the current sum cannot be expressed in N bits, or (2) provides a different prescribed signal on the carry output if the current sum can be expressed in N bits.

Abstract: A method and apparatus for pulse position modulation begins when a digital data stream is received. The encoding process continues by obtaining a set of bits from the digital data stream and modulating the set of bits into a pulse having a pulse width. Next, a transition edge of the pulse is positioned at one of a plurality of time intervals within a time chip based on the set of bits, wherein the pulse width is greater than each of the plurality of time intervals.

Abstract: A recording medium for a computer contains sectors, each of which represents a section of data that has originally been supplied by a user. As the user data is sent to the recording medium from the memory of the computer, an adjust bit determining circuit determines the adjust bit for a block of the write data. The adjust bit-value is such that the sum of the DC levels for the write data at a given point is equal to zero or approaches zero. The user data is converted using RLL(1,7) codes and PWM is performed to derive the write data. The circuit includes an encoder for receiving the user data two bits at a time. The encoder outputs DSV values for the 2-bit user data. A first circuit group for accumulating the DSV values from the encoder is used acquire block DSV values of data belonging to the plurality of blocks of the data section. A second circuit group accumulates these block DSV values computed by the first circuit group and calculates a temporary sector DSV value.