Abstract: A method for coding a message of a plurality of m-state symbols into a coded message of n-state symbols wherein n>m is disclosed. A method to make the distribution of states of n-state symbols a uniform distribution is also disclosed. A coding rule is initiated based on a distribution of states of m-state symbols. A method of coding the coding rule by transposition is also provided. In one embodiment a coded message of n-state symbols has symbols that each have a unique state. A system for executing the coding and decoding methods is also disclosed.

Abstract: An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘?1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.

Abstract: A method and system for generating a composite binary phase shift keying (BPSK) code from three independent component BPSK codes that is representative of each of the three component BPSK codes. According to one embodiment the method involves gain weighting each of first, second and third BPSK codes by its respective code power ratio to form first, second and third gain weighted codes. The first, second and third gain weighted codes are processed in accordance with an algorithm to form a composite BPSK code. The composite BPSK code has a fifty to seventy-five percent probability of matching each one of the component BPSK codes. A system for generating a composite BPSK code from three component BPSK codes is also disclosed.

Abstract: An apparatus and method are disclosed to encode binary data into trinary data. Applicants' method provides binary data, and encodes that binary data into trinary data. By “binary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value and a second value. By “trinary data,” Applicants mean a plurality of bits, wherein each of those bits comprises a value selected from the group consisting of a first value, a second value, and a third value. The trinary data may be stored in ROM optical disks, nano-sized indentations in a thin-film, or multi-level magnetic storage. The trinary data may be also transmitted via three light levels in an optical communications network.

Abstract: A system and method for realizing a Wyner-Ziv encoder may involve the following steps: (a) apply nested quantization to input data from an information source in order to generate intermediate data; and (b) encode the intermediate data using an asymmetric Slepian-Wolf encoder in order to generate compressed output data representing the input data. Similarly, a Wyner-Ziv decoder may be realized by: (1) applying an asymmetric Slepian-Wolf decoder to compressed input data using side information to generate intermediate values, and (b) jointly decoding the intermediate values using the side information to generate decompressed output data.

Abstract: An encoder and decoder for encoding data bits of a binary source signal into a stream of data bits of a binary channel signal and vice versa includes a conversion table used to map m-bit source words to codeword having a variable code length with a basic code length of n bits and a total code length of n*i bits, i being an integer of at least 1. The conversion table preserves the parity of the m-bit source words over the codeword and limits a characteristic of the codeword specified for each starting bit position in the code word.

Abstract: An MPEG (Moving Picture Experts Group)-4 encoding/decoding method, medium, and system. The decoding method may include detecting information for identifying an array structure of binary data describing a scene, and decoding the binary data based on the detected information. Since, a conventional process of converting data into a binary file and an inverse transforming process, which require a copying operation, are not required, memory and power use can be reduced.

Abstract: Methods and apparatus for coding binary and multi-value sequences into higher value sequences are disclosed. Correlation methods for comparing lower-value sequences by first coding to higher value sequences and then calculating a correlation number are also disclosed. Methods and apparatus for resetting the coding rule during multi-value coding are also disclosed.

Abstract: An ultra-wideband pulse modulation system and method is provided. One method of the present invention includes transforming data into a ternary data set with data being represented with states of zero, positive one and negative one. The modulation and pulse transmission method of the present invention enables the simultaneous coexistence of the ultra-wideband pulses with conventional carrier-wave signals. The present invention may be used in wireless and wired communication networks such as hybrid fiber-coax networks. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Abstract: The present invention abandons the conventional approach of incrementing bits-per-cell b by 1, but allows increments of states-per-cell N by as little as 1 between product generations. Because N is no longer an integral power of 2, b takes a fractional value, resulting in a fractional-bit system. In a fractional-bit system, cells are decoded in unit of word. By adjusting the word-width, the system efficiency can be optimized. Hybrid N-ary system can be used to improve manufacturing yield and endurance lifetime.

Abstract: A communication system for transmitting a six-phase modulated signal and including an efficient error correction system suitable for the six-phase modulated signal is disclosed. A transmitting apparatus comprises a ternary error correction encoding circuit for generating a ternary transmit sequence, a parity generation circuit for generating a parity, a parity insertion circuit for inserting the parity into a binary transmit sequence, and a six-phase modulator for performs six-phase modulation.

Abstract: A chip to chip interface comprises a driver configured to receive a data signal and provide an output signal at a first level in response to receiving an odd number of consecutive logic highs in the data signal, at a second level in response to receiving an odd number of consecutive logic lows in the data signal, at a third level in response to receiving an even number of consecutive logic highs in the data signal and at a fourth level in response to receiving an even number of consecutive logic lows in the data signal.

Abstract: Systems, methods and devices are described for placing a controlled device into a desired operating state in response to the position of a multi-position actuator. Two or more switch contacts provide input signals representative of the position of the actuator. Control logic then determines the desired state for the controlled device based upon the input signals received. The desired operating state is determined from any number of operating states defined by the input values. In various embodiments, ternary switching may be used in combination with binary switching to efficiently implement multi-state rotary or linear switches capable of identifying six, twelve, eighteen or any other number of switchable states.

Abstract: A delta modulation method and system is provided for processing signals in a digital communications system. The method quantizes an input signal using a tri-state quantizer into a quantized value selected from a set of three different quantized values including a low value, a middle value, and a high value. The selection of the quantized value is based on a comparison between the input signal and a predicted signal of a corresponding sampling period. The method generates from the quantized value an output signal representative of the input signal, determines a predicted signal of the next sampling period, and then feeds the predicted signal of next sampling period back to the tri-state quantizer.

Abstract: A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid-rail value for tri-state detection, and with less dependence on variations in product, process and temperature. In accordance with an exemplary embodiment, an exemplary tri-value decoder circuit comprises a switch circuit, a feedback loop and a sequence detector. An exemplary switch circuit is configured to facilitate sampling of a tri-state input signal through control by the feedback loop, with the sequence detector configured for decoding the tri-state input signal into a two-bit digital signal by detecting at least two samples of the tri-state input signal during a sampling period.

Abstract: Ternary data as corresponds to a movable barrier operator is provided (21) and converted (22) into corresponding binary information. In a preferred approach this comprises converting each ternary trit into a corresponding binary pair. Pursuant to a preferred approach binary bits as correspond to, for example, fixed and/or non-fixed information (32 and 33) are provided (31) and then converted (34) into the aforementioned ternary data.

Abstract: Methods and apparatus for coding binary and multi-value sequences into higher value sequences are disclosed. Correlation methods for comparing lower-value sequences by first coding to higher value sequences and then calculating a correlation number are also disclosed. Methods and apparatus for resetting the coding rule during multi-value coding are also disclosed.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A data compression algorithm which computes from a given probability density, in continuous or histogram form, a “probability centrifuge” probability density and also the Fisher information of the density. The density preserves Shannon entropy of the original density and the Fisher information represents the minimum Fisher information obtainable by “lateral” adiabatic reduction. The data compression algorithm can alternately be used to perform a “vertically” adiabatic reduction, a “radial” adiabatic reduction, or a “sectoral” adiabatic reduction. Said algorithm may provide alternate information for applications such as image reconstruction and protein folding analysis.

Abstract: Methods, software, circuits, architectures, and systems for encoding, decoding and error checking/correcting information, particularly pulse amplitude modulated information. The present invention enjoys particular advantage when used to encode x-unit sequence values of N-ary information into y-unit sequence values of M-ary information and to decode y-unit sequence values of M-ary information into x-unit sequence values of N-ary information, where Nx<My (and particularly where Nx<My, but Nx>My?M). The present invention advantageously provides a straight-forward mechanism for coding information that enables one to take advantage of coding overhead (e.g., unused states in the encoded, transmitted sequence) to accomplish other coding objectives, such as conforming to coding constraints, reducing transmission errors (or increasing the likelihood of successfully correcting such errors), dc balancing the coded information, and under certain conditions, even reducing power consumption.

Abstract: A communication system comprises a transmitting apparatus and receiving apparatus for transmitting/receiving a N-ary signal, based on a prime number exceeding 2, inclusive of an efficient error correction system. The transmitting apparatus includes a binary to N-ary converting unit for converting a binary transmit signal into an N-ary signal, as an information sequence, where the N of the N-ary number is a prime number exceeding 2, an encoding unit for generating a transmit sequence, comprised of BCH code on a Galois field with the number of elements being a prime number exceeding 2, and a multi-level modulating unit for multi-level modulating the transmit sequence and for transmitting the multi-level modulated transmit sequence to a receiving apparatus.

Abstract: A device and associated method for processing a digital information signal from a channel signal. The digital information signal is runlength limited with one or more constraints. The device comprises receiving means for receiving the channel signal and means for comparing a detected runlength with a predetermined value indicative of a minimum runlength constraint or a maximum runlength constraint of the channel signal and for generating a control signal when the detected runlength violates said constraint. The device further comprises substitute means for in response to the control signal deleting or inserting an element in the channel signal.

Abstract: To provide a code conversion circuit and a code converting method which are effective in reducing the circuit size. A 2N-bit signal, composed of a N-bit signal and a signal obtained on inverting respective N-bits of said N-bit signal, where N is an integer not less than 2, is received as an input, one of the 2N-bits is inverted to output 2N types decoded signals, in which one bit or plural neighboring (N−1) bits of the 2N-bits are of a first value, with the remaining bits being of a second value.

Abstract: In a method for position coding, positions are coded in a first dimension on a surface in accordance with a primary number sequence that has the property that the place in the primary number sequence of each partial sequence of a first predetermined length is unambiguously determined. Each position in the first dimension is coded by one of the partial sequences. The primary number sequence is built up of at least two secondary number sequences that have a smaller base than the base of the primary number sequence and that are used for determination of the partial sequences of the primary number sequence which correspond to the positions in the first dimension. This makes possible, among other things, realization of the method in devices with limited memory capacity, as the secondary number sequences require less memory in total than the primary number sequence. The secondary number sequences can also be used for decoding the position code.

Abstract: The data compressor utilizes a plurality of subdictionaries arranged in levels for storing strings of data characters. The subdictionary at the first level stores two character strings and a subdictionary at a subsequent level stores strings that are one character longer than the strings stored in the subdictionary at the level prior thereto. A plurality of data characters are fetched from the input into an input buffer and applied to the respective levels. The subdictionary at a level is searched for the string comprising the string matched at the prior level extended by the fetched character applied to the level. The string code of a string matched at a level is cascaded to the next level. The longest match with the fetched characters is determined by one of the fetched characters resulting in a mismatch at one of the levels. The string code associated with the longest match is output.

Abstract: Ternary weighted arrangements, for example, arrangements (delay circuits, devices, systems) including a variable delay determined on a ternary basis for use in testing set-up and hold times of a latch.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: The data compressor utilizes a plurality of character tables arranged in levels for storing strings of data characters, the character tables corresponding to respective characters of the alphabet. A string is stored by storing the string code associated with the string in a character table corresponding to the extension character of the string in a location of the character table corresponding to the code of the string prefix. The character tables at the first level store 2-character strings and the character tables at a subsequent level store strings that are one character longer than the strings stored in the character tables at the level prior thereto.

Abstract: The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.

Abstract: A signal processor circuit that buffers a ground-referred, signal-dependent, current. A ground-referred node in the circuit is preferably maintained at a ground level. The ground-referred, signal-dependent, current is preferably buffered such that the ground-referred node is preferably maintained at a ground level independent of changes to the ground-referred, signal-dependent, current.

Abstract: A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

Abstract: Disclosed is transmission of a signal over a single interconnect between functional blocks of the IC. A scaled or encoded signal responsive to a first digital signal is generated by summing currents responsive to the first control signal. The summed currents, which may be the sum of one or more currents, is the scaled signal. The encoded signal is transmitted over a single interconnect. This transmission occurs in one clock period in contrast to the at least two clock periods required to serially transmit data. The encoded signal is then used to generate a second digital signal. The generation of the second digital signal preferably includes mirroring the current of the encoded signal. The mirrored current is can then generate one or more separate voltages which are used to generate the second digital signal.

Abstract: The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assume that, for encoding, the previously encoded non-null symbol and the previously encoded symbol must be stored in a memory system. The sequence of symbols is transmitted in lieu of the binary sequence of data bits and decoded by a receiving device in order to restore the binary sequence of data bits from the received sequence of symbols. The decoding procedure assumes that three symbols must be received before a bit can be recovered. Hence, the system and method allow a self-delineation or self-sampling of a very-high speed data communication interface that is insensitive to large timing variations and skews.

Abstract: The present invention is for an implementation of a digital decimation filter and/or digital interpolation filter and a method of decimating and/or interpolating a multi-bit input signal, where n/2 additions are performed, where n=the number of bits in each filter coefficient. Scaling and multiplication of data with coefficients is performed using a common DSP architecture. Coefficient values, having an associated scaling factor, are stored in memory. The coefficients are stored in coded form, and are then decoded prior to multiplication by the data values.

Abstract: The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.

Abstract: A coding circuit of the present invention converts n-bit binary data word at a prescribed clock cycle (t) into to an m-trit ternary code word, where n and m are integers and n.gtoreq.m. The coding circuit includes an (x) number of storage elements or latches and a (y) number of coders, each storage element or latch receiving (m.div.x) bits of the binary data word at a clock cycle of (t.div.x). After a prescribed delay period, a corresponding storage element or latch outputs the sampled bits to a corresponding coder at an increasing or decreasing edge of the clock signal. Each coder codes the sampled bits to (m.div.y) ternary code. The each of the coders outputs (m.div.y) ternary code onto a corresponding signal line of a bus. Hence, the coding circuit outputs m-trit ternary code word onto the bus. An exemplary coding circuit is illustrated where n=8, m=6, t=25 MHz, x=2 and y=2, and D flip-flops are used for the storage elements and latches.

Abstract: A method and circuit, for use with a parallel data bus of defined width, which provide a parallel data transmission and reception rate which is greater than the defined width of the parallel data bus. With respect to improving transmission, provided is a width-reduction circuit element, having at least two inputs through which are received a first set of parallel digital data signals and having one or more outputs through which are transmitted a second set of parallel digital data signals where the second set is both smaller than the first set and representative of the information contained within the first set. The one or more outputs interface with a parallel connector which is sufficient to form an operable connection with the parallel data bus of defined width.

Abstract: A redundant binary code conversion circuit consists of first to third RBC conversion circuits 261 to 263. The circuit 261 consists of decoders 30 to 38 of the same construction, the circuit 262 consists of RBC 2-digit conversion circuits 40 to 47 of the same construction and the circuit 263 consists of decoders 50 to 58 of the same construction. The circuit 261, as an exception, converts RBC patterns `...TT011...`(`T` is -1), `...110TT...`, `...TT1...` and `...11T...` of n digits to RBC patterns `...T10T0T...`, `...1T0101...`, `...T10T...` and `...1T01...` of (n+1) digits, respectively, circuit 262 converts RBC patterns `...1T...` and `...T1...` to RBC patterns `...01...` and `...0T...`, respectively, and circuit 263 converts RBC patterns `...10TT...` and `...T011...` to RBC patterns `...0101...` and `...0T0T...`, respectively.

Abstract: Method and apparatus for encoding digital information to be recorded on a magnetic medium is disclosed. The invention provides for receiving a sequence of (2.sup.m n+d) user bits, mapping the sequence of user bits to 2.sup.m dc-free codewords, and recording the 2.sup.m dc-free codewords on a magnetic medium. A modulation coder, which includes a memory containing multiple non-intersecting subconstellations of dc-free codewords, performs the mapping in a non-equiprobable manner such that a particular codeword from a larger subconstellation is more likely to be used than a particular codeword from a smaller constellation. Less desirable codewords, such as those containing relatively long strings of bits having the same value, are assigned to the smaller subconstellations, thereby lessening the likelihood of loss of timing and gain parameters in the system, as well as maximizing the transmission rate and efficient use of the set of possible dc-free sequences of a given length.

Abstract: Light is obliquely irradiated onto the surface of a document in braille, and its reflected light is received, to obtain a first gray image. The first gray image is subjected, while being scanned in a direction corresponding to a direction parallel to the direction of light irradiation, to differentiation processing in the scanning direction, to produce a second gray image whose light and dark portions respectively produced by projected points have a particular pattern. The second gray image is subjected to such ternary-coding processing that the particular pattern of the light and dark portions respectively produced by the projected points in the second gray image is emphasized, to produce a ternary-coded image. Each of the projected points is extracted by pattern matching with respect to the ternary-coded image.

Abstract: A system for encoding data by converting an input value into one of a plurality of voltage levels. The multi-level encoding system allows for increased data transfer rates and conservation of bandwidth, and provides self-synchronization for decoding.

Abstract: A method for encoding a binary input sequence x(0,1) to obtain a duobinary output sequence y(+1,0,-1) is provided. The duobinary coding technique always provides an output bit y.sub.k =0 when the corresponding bit x.sub.k =0; bits y.sub.k alternatively assume a logical level "+1" and "-1" whenever an input bit x.sub.k-1 =0 changes to x.sub.k =1, and the output bit y.sub.k maintains the logical level "+1" or "-1" whenever the corresponding bit x.sub.k maintains the logical level "1". A coding device for encoding a binary input sequence x(0,1) to a duobinary output sequence y(+1,0,-1) is also provided, comprising a D-type flip-flop for generating a binary switch signal. A first AND circuit receives the input sequence and the switch signal, and provides a first binary sequence a(0,1), while a second AND circuit receives the input sequence and the complement of the switch signal and provides a second binary sequence b(0,1).

Abstract: A method of encoding first and second symbols each having n binary bits into first and second code words each having n-1 ternary trits is disclosed. The method involves using a preselected bit from each of the first and second symbols to determine which one of at least two groups of code words comprising n-1 trits is used for encoding. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: An Ethernet-type local area network having multiport repeaters and nodes within a specified distance of the hub is able to communicate high speed digital data over multiple pairs of twisted-pair wires using long symbol group-type ternary coding. Bundle mode termination minimize impedance mismatches. Low-frequency collision detection circuitry permits detection of packet collisions on an a.c.-coupled network. Precise serialized digital to analog conversion is realized using chains of gates to form delay elements with precise delays.

Abstract: A method of encoding a five bit symbol into a four trit code word is disclosed, comprising defining out of forty-eight combinations of four trit code words three groups, each group containing sixteen code words, each code word within a group having a Hamming distance of at least two from any other code word in the group, and each code word being associated with a particular combination of four bits selected from said five bit symbol. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract: Rate 24/25 modulation encoding methods and apparatus improve efficiency in a PRML magnetic recording channel. The rate 24/25 code word uses rate 8/9 RLL encoding of one byte of user data, combined with interleaved unencoded bytes to achieve improved code rates with reasonable global run length constraint. Use of the the rate 8/9 RLL (0,3) subcode results in a rate 24/25 RLL (0,11) code, while a rate 8/9 (0,6/5) subcode results in a rate 24/25 RLL (0,14/13) code.

Abstract: The off-state of the binary transitions is used in order to possibly generate symmetrical transitions of the active state of the binary transitions in relation to the off-state, in order to replace the two-state logic of at least one binary transition capable to go to the rest-state by a three-state logic.

Abstract: A decoding method for tri-state read-only memory is disclosed herein. The cells of the tri-state memory are read the storage bits of all cells are combined to form a storage code. Each bit represents one of a first state, a second state and a third state. The storage code is first decoded to convert the storage code into an intermediate code. The intermediate code includes a plurality of conversion codes, each of which is one of a first code, a second code, and a third code corresponding respectively to the first, second, and third states. The intermediate code is further decoded into the binary output code. The resulting binary code has a greater number of bits than its corresponding storage code. Thus, the read-only memory, in accordance with the present invention, can store more than one bit of data in a single memory cell.

Abstract: A method for encoding binary data for transmission over a serial link as a ternary code. Binary data is received and mapped into a binary code. The binary code is translated into a ternary code, and the ternary code is transmitted over the serial link. The ternary code is selectively inverted according to a predetermined protocol such that the serial link maintains a time-averaged zero DC balance.

Abstract: Existing infrastructures such as DS1 or E1 are used at currently accepted rates to carry a third more information by using a hybrid encoding technique wherein a 4B3T encoding is done for the payload bits, while a 1B1T encoding technique is used for framing information. In this way, for example, a DS1 can be used at 1.54 Mbit per second to carry 2.058 Mbits of binary payload, while respecting the 8 kilobits of framing expected by DS1 hardware. Similarly, for example, an E1 infrastructure can be used at the accepted 2.048 Mbit per second rate to carry 2.560 Mbits of binary payload plus 128 kilobits of binary framing/CRC without having to change the accepted E1 framing techniques.