Abstract: An Ethernet-type local area network having multiport repeaters and nodes within a specified distance of the hub is able to communicate high speed digital data over multiple pairs of twisted-pair wires using long symbol group-type ternary coding. Bundle mode termination minimize impedance mismatches. Low-frequency collision detection circuitry permits detection of packet collisions on an a.c.-coupled network. Precise serialized digital to analog conversion is realized using chains of gates to form delay elements with precise delays.

Abstract: A full duplex data transceiver for transmitting and receiving trinary frequency-modulated ("FM") signals representing binary data includes separate transmit and receive antennas, and a single oscillator which serves as both the radio frequency ("RF") signal source for the transmitter and the local oscillator ("LO") signal source for the receiver. During signal transmission, the oscillator output is frequency-modulated to provide a FM transmit signal to the transmit antenna. The oscillator output is frequency-modulated with binary transmit data by modulating an error feedback signal which serves as the control voltage for a voltage-controlled oscillator in a phase-lock-loop, thereby producing the FM transmit signal. During signal reception, the oscillator output, in the form of the transmitted FM signal, is received via the receive antenna along with a FM receive signal for mixing therewith to down-convert the FM receive signal.

Abstract: A data transmitter circuit includes a pseudoternary conversion circuit for converting a binary logic signal to a differential pseudoternary signal having symmetric rise and fall characteristics. The output of the pseudoternary conversion circuit is filtered and passed to an electrically conductive medium via an isolation transformer. The conversion circuit includes a symmetric arrangement of toggle circuits which respond to transitions in respective complementary binary signals constituting a differential binary input signal. Voltage dividers are connected to the output terminals of the toggle circuits for providing three levels of output voltages in response to the logical states of the toggle circuits.

Abstract: An apparatus and method for transmitting an 8-bit binary format data word as a 6-trit ternary code word includes an encoder, a decoder, and a code assignment that produce, for each 8-bit data word value, an unique 6-trit ternary code word that is particularly optimized for transmission over twisted-pair cable. The logic circuitry of the invention is optimized to accomplish the translation using a small number of combinatorial logic gates. The present invention thus has advantages in size, speed and performance over other possible means for encoding an 8 bit data word to a 6 trit code word.

Abstract: In a Viterbi decoding method, there are four playback states which are state S0, state S1, state S2, and state S3. When the signal e(t) that violates the predetermined state transition rules is inputted, bit error correction is performed by detecting the incorrect state and determined the original state. According to the predetermined state transition rules, for example, when the signal e(t) of "-1" is inputted during state S0, it makes a transition to state S0 and the value of the output signal f(t) is made "0".

Abstract: A 3-value input buffer circuit is configured by a first N-channel MOS transistor whose source is connected to an input terminal, a first P-channel MOS transistor which is connected to the first N-channel MOS transistor, a first inverter whose input is connected to a drain of the first P-channel MOS transistor, a second P-channel MOS transistor whose source is connected to the input terminal, a second N-channel MOS transistor which is connected to the second P-channel MOS transistor, a second inverter which is connected to a drain of the second N-channel MOS transistor, and a voltage applying circuit which is constituted by P-channel MOS transistors and which applies a constant voltage to a gate of each of the first N-channel MOS transistor and the second P-channel MOS transistor. The first N-channel MOS transistor and the second P-channel MOS transistor are cut off when the input terminal is in an open state. Thus, the power consumption can be significantly suppressed.

Abstract: Loss of synchronization, due to a digital data signal having the same signal value for an extended number of bit or symbol periods, is overcome through the use of a coding scheme which assures transitions after each such period despite the absence of transitions in the signal to be encoded. Broadly, within the encoder, a digital input signal having m signal levels is transformed into a coded digital output signal having n possible signal values, where m<n. The transformation alters the current digital input signal value as a function of the previous coded digital output signal value and the current digital input signal value performed in a number system whose modulus is n. In a disclosed embodiment, a binary input signal is coded into an output signal having three signal levels.

Abstract: An apparatus for transmitting information with a reduced number of bits without decreasing a transmission speed of a serial-signal and without omitting any information in the serial-signal includes an encoding unit (20) for encoding a serial-signal with binary-value into a serial-signal with quaternary-value and for outputting the encoded serial-signal with the quaternary-value, and a decoding unit (30) for receiving the encoded serial-signal with the quaternary-value output from the encoding unit (20) and for decoding the received serial-signal with the quaternary-value into the serial-signal with the binary-value.

Abstract: A circuit for developing a binary bitstream signal from a ternary analog signal having positive and negative amplitude peaks includes an analog-to-digital converter for receiving the analog signal and providing digital samples in accordance with the amplitude and polarity of the analog signal. The most significant bit of digital sample indicates the polarity of an analog signal sample. A threshold value is compared to a current amplitude sample to indicate a level change in the analog signal when the sample value exceeds the threshold value and the polarity differs from that of the preceding sample which exceeded the threshold value. The current sample value which exceeds the threshold value is compared with preceding sample values which exceeded the threshold value, and a level change is indicated by the sample value which most exceeds the threshold value. Incorrect sample values are inverted in a correction circuit.

Abstract: The run length limited encoding/decoding system of this invention includes a clock swap logic circuit, a read reference clock multiplexer circuit, a write clock skip logic circuit, an encoder start logic circuit, an encoder circuit, a read clock skip logic circuit, a decoder start logic circuit, a decoder circuit, an input data buffer and a three-state output data buffer. The encoder circuit includes a deserializer for receiving serial data from a disk controller and blocking the data into m bit words. Each m bit data word is supplied directly to an encoding combinatorial logic circuit which in turn generates an n bit code word. The n bit code word is loaded in a serializer and serially transmitted out of the serializer. The decoder circuit includes a deserializer/serializer and a decoding combinatorial logic circuit. The deserializer/serializer receives a serial stream of encoded data and converts the data into n bit code words.

Abstract: An encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m/n, where m and n are each an integer satisfying m<n, in accordance with a rule of a run-length-limited coding system and contains an encoder which inputs parallel m bits of the original data, and outputs parallel n bits of coded data corresponding to the input. Successive bits of data which are to be encoded are cyclically divided into a plurality of groups, and the data in the plurality of groups are input in a plurality of shift registers, respectively. Each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder, synchronizing with a clock. The n bits of the output of the encoder is received in parallel in another shift register, and are serially output from the shift register, synchronizing with a second clock.

Abstract: As to a differential code (DPCM) transmission system for an input signal as such as an audio signal, in case higher frequency components thereof are dominant, every another samples of the input signal are alternately into two groups, in each of which differential coding effected, so as to maintain a dynamic range in higher frequency range; in case no frequency components exceeding one fourth of the sampling frequency are contained in the input signal, successive 3 MSB's having a pattern "1, 0, 1" or "0, 1, 0" are corrected into "1, 1, 1" or "0, 0, 0" respectively; and in case 2 symbols of a tertiary code converted from 3 bits of a binary code are transmitted and restored, peripheral bit arrangement of a matrix having rows consisting of the first symbols of the converted tertiary codes and columns consisting of the second symbols thereof are allotted such as Gray codes are obtained, while an inner 2.times.2 matrix of a 4.times.

Abstract: Binary encoded information having a word size of 3N bits, where "N" is a positive integer, plus a parallel data clock are converted to corresponding control signals. Signal drivers with three-state outputs respond to the control signals and communicate corresponding signals via transmission lines, one transmission line per signal driver, to receiving circuits capable of detecting three-state signals, an embodiment of said circuits produce bipolar signals corresponding to the state of the transmission lines with which they communicate. A code converter produces binary signals and a data clock corresponding to the bipolar signals from the receiving circuits. The net result is that the binary word and data clock produced at a receiving end of the transmission lines logically matches the binary code and data clock applied at a sendng end, and that the produced data clock has the same timing relationship with the received binary word as does the originating data clock have with the originating binary word.

Abstract: The apparatus converts an AMI signal into three unipolar signals by selectively amplifying the AMI signals so that higher frequency components are amplified greater than lower components and then comparing the AMI signal with a positive and negative threshold to provide a first unipolar signal having information relating to positive levels of said AMI signal, a second unipolar signal having information relating to negative levels of said AMI signal and a Or gate for combining said first and second signals to provide a third signal having information related to both positive and negative levels.

Abstract: An electronic circuit for converting trinary level input signals on a first line into binary level signals on two or more output lines using contemporary CMOS field effect transistor integrated circuits. According to one embodiment, conversion is accomplished using two CMOS inverters each asymmetrically configured to exhibit transconductances which differ by a factor in excess of 5. In another form, the circuit provides hysteresis through positive feedback to limit binary output state perturbations attributable to trinary signal level input noise. The invention also encompasses the use of decode logic and logically combined delay elements to eliminate "glitches" and facilitate selective enablement of the decoded states representing the intermediate of the trinary input levels.

Abstract: A binary-to-ternary converter arrangement which achieves protective resistance against high outside voltages without having to compromise the voltage level of the positive and negative output ternary pulses. In so achieving, the minimum amplitude requirement of a CCITT recommendation of an output pulse for a given supply voltage is satisfied. This converter arrangement includes a parallel circuit of first and second series circuits. The first series circuit forms a main current path of two transistors and the second series circuit forms a current path of a diode, two resistors, and a third transistor. The different elements of these two circuits, along with a capacitor element, are interconnected in such a way as to eliminate the need for the use of a transformer altogether. The control electrodes of the first and second transistors serve as input ports and the junction port of the two resistors serves as the output port.

Abstract: A binary-to-bipolar converter converts two binary signals into positive and negative bipolar pulses alternately corresponding to a "1" logic state of two binary signals. The bipolar pulses are defined by the low output impedance states of two transfer gates. The main object of the invention is to reduce the transient trailing of the rear edges in the bipolar pulses. This can be obtained by delaying the drop from the low impedance state to the high output impedance state by means delaying control signals on the transfer gates, or by an integrator circuit applying calibrated pulses onto the output of the transfer gates, in response to the rear edges of the "1" logic states in the binary signals. The converter also calibrates the rise times of the bipolar pulses and allow the use of CMOS circuits upstream of the converter.

Abstract: The system uses a 3B2T line code, i.e. one in which sets of three or triplets of binary digits are converted into pairs or duplets of ternary elements. All nine of the possible ternary duplets are used, in such a way that the same ternary duplet does not occur twice consecutively. This is done in one version by using the ninth duplet 00 as a repeat indicator, and in the other version by a conversion process in which each conversion operation takes into account the result of the preceding operation.

Abstract: A method is provided for encoding and decoding data to be transmitted over a communication network via transformer coupling. The data is pulse width modulated, and split into separate first and second data streams containing alternate pulses. The first data stream is inverted, and recombined with the second data stream to produce a pulse width modulated bi-polar data signal having an alternating pulse sequence. The data is decoded at the receiver by inverting the pulses of one polarity, and combining them with the pulses of the other polarity to form a pulse width modulated data stream.

Abstract: A Simple Code encoder/decoder converts a ternary, or bipolar, signal having a strong clock component into a binary signal while maintaining the strong clock component for processing with digital equipment. The Simple Code is high for each positive value of the bipolar signal, low for each negative value of the bipolar signal, and alternates high/low for each zero value of the bipolar signal. The encoder uses an extractor circuit to generate a +PULSE signal, a -PULSE signal and a CLOCK signal from the bipolar signal. The +PULSE and CLOCK signals are combined to produce an intermediate binary signal, and the intermediate binary signal is combined with the -PULSE signal to produce the Simple Code binary signal. The decoder extracts the CLOCK signal from the Simple Code binary signal and uses the CLOCK signal to generate positive and negative pulse signals corresponding to the highs and lows of the binary signal of a duration equal to the period of the CLOCK signal.

Abstract: A method termed Even Mark Modulation (EMM) is disclosed for coding input strings for input-restricted (1+D) or (1+D).sup.2 partial response channels that require at least one pair of consecutive signals of one state in order to record or transmit data to a receiving device. EMM provides improved coding gains and is especially suitable for optical recording.An input string is encoded into a binary code string in which all one-state signals (e.g., "1's") are in the form of runs of at least one contiguous pair; however, signals of an opposite state (e.g., "0's") may be of any length or duration. The EMM signals are detected with a maximum likelihood detector using an algorithm based on a three-state trellis structure for (1+D) channels and a five-state trellis structure for (1+D).sup.2 channels adapted to the particular partial response channel. In a preferred embodiment, the coding rate is 2/3 and the coding gain is at least 3 dB unnormalized and at least 2.2 dB when normalized.

Abstract: In a device which is for use in a receiver of a multivalued digital communication system and which includes a reference voltage producing circuit (51) for producing signal discriminating reference voltages and signal regenerating reference voltages related to one another, a level discriminating circuit (31) for discriminating a multivalued received signal with reference to the signal discriminating reference voltages to produce a local encoded signal, a signal decoding circuit (32) for decoding the local encoded signal into a decoded signal, a signal regenerating circuit (33) responsive to the local encoded signal for regenerating a multivalved regenerated signal having the signal regenerating reference voltages, a comparator (34) for comparing the received and the regenerated signals to produce a result of comparison, and an integrator (35) for integrating the result of comparison to produce a result of integration, the signal discriminating and regenerating reference voltages are regulated by the result of

Abstract: A detector logic circuit restores the value 0 or .+-.1 of a ternary symbol converted into a signal on five levels 0, .+-.1 and .+-.2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.