Abstract: A noise generator includes a selection unit suitable for outputting first elements corresponding to first seeds based on a first function, and outputting second elements corresponding to second seeds based on a second function, a first permuter suitable for generating first pair elements based on a first correspondence relationship in which the respective first elements and the respective second elements correspond to each other, and a first calculation unit suitable for generating a first noise based on the first pair elements, wherein a product of the first function and the second function is a Gaussian random variable.

Abstract: Methods and systems for indicating an end of an idle sequence, including: encoding a first frame, encoding a basic idle sequence including code words, producing an idle sequence by replacing certain M code words of the idle sequence with M alternative code words, and encoding a second frame. Each one of the M alternative code words appears in the basic idle sequence. And a second communication node, which is unable to determine a starting point of the second frame based only on a received idle sequence, is able to determine a start of the second frame based on a difference between the received idle sequence and the basic idle sequence.

Abstract: Methods and systems for indicating an end of an idle sequence residing between first and second frames, while maintaining bounded running disparity, including: encoding the first frame; encoding a basic idle sequence utilizing a first line-code; producing an idle sequence by replacing M code words of the basic idle sequence with M alternative code words; encoding the second frame; transmitting the first frame, the idle sequence, and the second frame; and receiving the second frame by a second communication node. Each one of the M alternative code words is equal to a code word of the basic idle sequence. And the second communication node is unable to determine a starting point of the second frame based only on the idle sequence and the second frame, but is able to determine the starting point of the second frame based on difference between the basic idle sequence and the idle sequence.

Abstract: Apparatus, systems, and methods to reduce power delivery noise for partial writes are described. In one embodiment, an apparatus comprises a processor and a memory control logic to insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold. Other embodiments are also disclosed and claimed.

Abstract: Provided are methods and systems for reducing a transition rate in transmitting data between analog and digital chips in Sigma-Delta Modulator (SDM) based Digital to Analog Converters (DACs) and Analog to Digital Converters (ADCs) intended to be used in audio signal processing. An example method may comprise receiving, by a digital chip, SDM binary data, mapping the SDM binary data to transition binary codes, and transmitting the transition binary codes to an analog chip. The mapping can be carried out according to a principle that the more commonly used SDM binary data codes correspond to transition binary data codes that require that fewer transitions occur in the signals between the chips. The methods and systems described provide for lowering the power needed for carrying out the data transmission between digital and analog chips.

Abstract: Systems and techniques are disclosed to express sequences of codes, and in particular sequences of ASCII characters, in a lossless compressed format. The techniques may include dividing a universe of expressible codes into smaller subsets, called code sets, such that every code exists within one code set, but no code exists within two code sets. The code sets are then utilized for compression based on the heuristic that it is more likely that a next code in the sequences of codes is in the same code set as a previous code in the sequences of codes, rather than that the next code in sequences of codes being in any other code set (sentence structure).

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system. As an example, a data processing system may include an encoder circuit. The encoder circuit includes at least a first encoder and a second encoder, and is operable to generate a first level encoded output that is the same length for a given code rate whether the first encoder or the second encoder is selected.

Abstract: A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced.

Abstract: A method for run time zero byte compression of data on a communication bus of a vehicle includes determining a number of zero byt.es provided in a data frame. When there are enough zero bytes, an encoding byte is generated that maps the locations of the zero bytes in the data frame. A data length code related to the number of non-zero data bytes and the encoding byte is provided in a device header. The data length code has a value less than an uncompressed data frame. The compressed data frame is transmitted with the encoding byte and the uncompressed non-zero data bytes. To decompress the compressed data frame, the encoding byte maps the locations of the zero bytes for a data frame. The non-zero data bytes are then provided at the proper locations to recreate the data frame.

Abstract: A circuit arrangement, method, and program product communicate data over a communication bus by selectively encoding data values queued for communication over the communication bus based at least in part on at least one data value queued to be communicated thereafter and at least one previously communicated encoded data value to reduce bit transitions for communication of the encoded data values. By reducing bit transitions in the data communicated over the communication bus, power consumption by the communication bus is likewise reduced.

Abstract: An apparatus is disclosed for communication of data signals in a current-encoded format. The apparatus includes a first logic block and a second logic block. The first logic block includes a first voltage-mode logic (VML) circuit configured to provide a first voltage-encoded binary signal and an encoder circuit configured to convert the voltage-encoded binary signal to a current-encoded binary signal. The second logic block includes a decoder circuit configured to receive the current-encoded binary signal from the first logic block and convert the current-encoded binary signal to a second voltage-encoded binary signal. The logic states encoded by the second voltage-encoded binary signal are equal to the logic states encoded by the first voltage-encoded binary signal. The second logic block also includes a second VML circuit coupled to the decoder circuit and configured to receive and process the second voltage-encoded binary signal.

Abstract: A method for updating a run length encoded (RLE) stream includes: receiving an element having an insertion value to be inserted into the RLE stream at an insertion position, the insertion value having one of a plurality of values, the RLE stream having elements arranged in runs, and each of the elements having one of the values; identifying a run containing the insertion position; determining whether the insertion value is the same as the value of the element at the insertion position; when the insertion value is different from the value of the element at the insertion position: determining whether the insertion position is adjacent to one or more matching runs of the runs, each element of the matching runs having a same value as the insertion value; and extending one of the matching runs when the insertion position is adjacent to only one of the matching runs.

Abstract: Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

Abstract: In a DTV transmitter the bits of shortened BCH codewords that exhibit undesirably low densities of ONEs are ONEs' complemented before being further coded, and used to modulate carrier waves. In a DTV receiver the further coding is decoded after demodulation. The results of such decoding are processed to recover successive shortened BCH codewords, some of which are in TRUE form and others of which have had their bits ONEs' complemented. Each shortened BCH codeword is extended to full length with ZEROs, and decoding is attempted. Successful decoding confirms that the shortened BCH codeword was received in TRUE form. If decoding is unsuccessful, the bits of the shortened BCH codeword as received are ONEs' complemented, extended to full length with ZEROs, and decoding is attempted. Successful decoding confirms that the shortened BCH codeword was received in ONEs' complemented form and has subsequently been converted to TRUE form.

Abstract: Systems and methods are disclosed for precisely determining the delay between data being received at the pins of a circuit and being processed by gearbox circuitry, to being processed by a time-stamp unit of the circuit. In an exemplary embodiment, the gearbox circuitry may output a data valid signal which may be monitored by the time-stamp unit. By monitoring the data valid signal, the time-stamp unit may synchronize a local state machine with the internal state of the gearbox circuitry and thus determine the total delay through the combined processing circuitry with high accuracy.

Abstract: A running disparity computation predictor is configured to analyze a frame of data, a control value, and an input tracking value and generate a predicted output tracking value. A frame selector is configured to generate an encoded frame of data based on this predicted output tracking value. A frame insertion module is configured to insert the encoded frame of data into a data stream wherein the predicted output tracking value matches an output tracking value generated by the data stream. This combination of elements can bypass an encoder built into a Hard IP block or proprietary hardware when the running disparity value is required to select control words.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a reduced representation of an input sequence of characters by replacing a repetition of a sequence of one or more characters by a code representing the repetition of the sequence of one or more characters. The second circuit may be configured to generate a compressed representation of the input sequence of characters in response to the reduced representation of the input sequence of characters. The second circuit is generally configured to recognize the code representing the repetition of the sequence of one or more characters and take into account the repetition of the sequence of one or more characters during a compression operation.

Abstract: A method and apparatus for symbol-space based compression of patterns are provided. The method comprises generating an output sequence responsive of an input sequence, the input sequence being of a first length and includes a plurality of symbols, by extraction of all common patterns, wherein a common pattern includes at least two symbols and the output sequence is of a second length that is shorter than the first length; and storing in a memory the output sequence as a data layer.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: Provided is a transmitter for transmitting signals by means of the STBC method or the DSTBC method, wherein communication is carried out effectively. The transmitter for transmitting signals by means of the STBC method or the DSTBC method has the following configuration. A frame in which synchronization words are arranged at specified positions is used. An encoding means in the transmitter encodes the entire frame to be transmitted including the synchronization words, by means of the STBC method or the DSTBC method. It is also possible to implement a communication system and a communication method for communicating signals by means of the STBC method or the DSTBC method.

Abstract: A coding method, a decoding method, a coder, and a decoder are disclosed herein. A coding method includes: obtaining the pulse distribution, on a track, of the pulses to be encoded on the track; determining a distribution identifier for identifying the pulse distribution according to the pulse distribution; and generating a coding index that includes the distribution identifier. A decoding method includes: receiving a coding index; obtaining a distribution identifier from the coding index, wherein the distribution identifier is configured to identify the pulse distribution, on a track, of the pulses to be encoded on the track; determining the pulse distribution, on a track, of all the pulses to be encoded on the track according to the distribution identifier; and reconstructing the pulse order on the track according to the pulse distribution.

Abstract: A multilevel amplitude modulation device for generating, from digital data, a multilevel amplitude modulation signal having four or more signal levels and outputting the generated signal, including: an average level calculator that selects one of a plurality of preliminarily prepared different candidates for a code word building method such that average level of a symbol array, obtained by adding a symbol for a code word of digital data to be transmitted to one or more already outputted symbols included in a multilevel amplitude modulation signal already outputted, is most approximate to voltage center of the four or more signal levels, and outputs a selection signal indicating the selected method; a signal converter that forms a codeword of the digital data in accordance with the method indicated by the selection signal; and a multilevel modulator that generates a multilevel amplitude modulation signal using the codeword and outputs the generated signal.

Abstract: The invention provides a two-dimensional run-length limited (RLL) (1,3) code method and apparatus. The codec comprises an encoder and a decoder comprising a data buffer and grouping module, a two-dimensional code word generating module, a two-dimensional word unit page constructing module, a two-dimensional code word write array module, and a protection word stuffing module. The five modules are sequentially connected, and send output through the protection word stuffing module to a two-dimensional data recording device. The decoder comprises a two-dimensional data buffer module, a two-dimensional word unit page constructing module, a one-dimensional data word decoding module, and a one-dimensional data stream assembly module. The five modules are sequentially connected, and send output through the one-dimensional data stream assembly module.

Abstract: It is an objective of the present invention to provide a technique, when using fixed-length run-length limit codes based on enumeration, that generates fixed-length channel bit words satisfying maximum run-length limitation using a simple configuration. A channel bit word processor according to the present invention includes an avoidance list that describes a difference between a user bit word satisfying a maximum run-length limitation of run-length limit code and a user bit word not satisfying the maximum run-length limitation. The channel bit word processor, if a user bit word does not satisfy the maximum run-length limitation, generates a channel bit word using a user bit word after the difference is added.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table selected according to the number of already-processed run values.

Abstract: A plurality of random bit sequences is generated. Each of the random bit sequences is different and is based at least in part on an input bit sequence. A plurality of metrics corresponding to the plurality of random bit sequences is generated. The plurality of metrics is associated with one or more transition run lengths. One of the random bit sequences is selected based at least in part on the metrics. An output bit sequence is generated that includes the selected random bit sequence and an index associated with demodulating the selected random bit sequence.

Abstract: Embodiments of the present invention generally relate to binary block transmission codes for high-speed network transmissions. More specifically, embodiments of the present invention relate to bounded-disparity run-length-limited forward error correction codes and methods of constructing and utilizing same. In one embodiment, a method for generating binary block bounded-disparity run-length-limited forward error correction transmission codes comprises selecting an existing base code, deriving a sub-code from the existing base code, having properties indicated by disparity bound, run-length limit and minimum distance, ascertaining a plurality of codewords and control characters from within the sub-code, encoding Messages to be transmitted with at least one codeword from the plurality of codewords, transmitting codewords from a transmitter to a receiver, and decoding the codewords into Messages.

Abstract: A method for producing N-bit output words of RLL-encoded data having both a global constraint Go and an interleave constraint Io on bits of a first value includes receiving N-bit input words of RLL-encoded data having both a global constraint Gi and an interleave constraint Ii on bits of like value; and producing the output words from respective input words by sliding-window encoding of each input word to replace predetermined bit-sequences with respective substitute sequences such that Go<Gi; wherein each substitute sequence is unique and violates a run-length limit associated with the interleave constraint Ii such that Io>Ii.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: A method and apparatus for symbol-space based compression of patterns are provided. The method comprises receiving an input sequence, the input sequence being of a first length and comprising a plurality of symbols; extracting all common patterns within the input sequence, wherein a common pattern includes at least two symbols; generating an output sequence responsive of the extraction of all common patterns, wherein the output sequence has a second length that is shorter than the first length; and storing in a memory the output sequence as a data layer, wherein the output sequence is provided as a new input sequence for a subsequent generation of a data layer.

Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

Abstract: A method of data compression includes obtaining a data set comprising a sequence of data blocks comprising a predetermined number of data items, partitioning said data set into one or more groups each comprising a predetermined number of data blocks, and performing data compression on one or more groups of data blocks. Data compression is performed by associating a control data item with each of said blocks, generating a control vector comprising the control data items assigned to each of said blocks within a group, removing data blocks comprising entirely data items having said specified value, compressing data blocks comprising at least one data item having a value different from said specified value using a fixed-rate compression scheme, providing a compressed data stream comprising said compressed data blocks, and providing an associated control vector stream to enable control of said compressed data stream.

Abstract: A reconfigurable operation apparatus includes a reconfigurable circuit, a storage unit and a control unit. The reconfigurable circuit has a plurality of small circuits and reconfigures a circuit using the small circuit selected from the plurality of small circuits based on recorded circuit information. The storage unit stores first and second circuit information which corresponds to first and second compression circuits, respectively. The control unit reconfigures the reconfigurable circuit into the first or second compression circuit by recording the first or second circuit information in the reconfigurable circuit in accordance with an input data string.

Abstract: An encoding device for converting m-bit data words into n-bit (both n and m are integers and 2n?2m×2) code words includes a first encoding table in which 2m code words selected from the 2n n-bit code words correspond to 2m m-bit data words, a second encoding table in which 2m code words, which do not overlap with the code words in the first encoding table, of the 2n n-bit code words correspond to 2m m-bit data words, and an encoding unit which selects and outputs a code word, in which an absolute value of a code string DSV is smaller, from code words corresponding to the input m-bit data words in the first encoding table and code words corresponding to the input m-bit data words in the second encoding table.

Abstract: An apparatus includes an encoder adapted to encode data bits for transmission via a communication link. The encoder includes a logic circuit. The logic circuit is adapted to perform a logic operation on a pattern of bits and the data bits in order to reduce a run-length of the data bits.

Abstract: The invention provides a two-dimensional run-length limited (RLL) (1,3) code method and apparatus. The codec comprises an encoder and a decoder comprising a data buffer and grouping module, a two-dimensional code word generating module, a two-dimensional word unit page constructing module, a two-dimensional code word write array module, and a protection word stuffing module. The five modules are sequentially connected, and send output through the protection word stuffing module to a two-dimensional data recording device. The decoder comprises a two-dimensional data buffer module, a two-dimensional word unit page constructing module, a one-dimensional data word decoding module, and a one-dimensional data stream assembly module. The five modules are sequentially connected, and send output through the one-dimensional data stream assembly module.

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract: A method for producing N-bit output words of RLL-encoded data having both a global constraint Go and an interleave constraint Io on bits of a first value includes receiving N-bit input words of RLL-encoded data having both a global constraint Gi and an interleave constraint Ii on bits of like value; and producing the output words from respective input words by sliding-window encoding of each input word to replace predetermined bit-sequences with respective substitute sequences such that Go<Gi; wherein each substitute sequence is unique and violates a run-length limit associated with the interleave constraint Ii such that Io>Ii.

Abstract: An array f(n) is received for n=1, . . . , N where N is a length of a codeword. An array g(n) is received for n=1, . . . , N where N is a length of a codeword. Input data is encoded to satisfy an MTR constraint and a RLL constraint using the array f(n) and the array g(n).

Abstract: Disclosed are systems, apparatus, and methods for encoding data transmitted in a data line. In various embodiments, a device may include a first input port operative to receive a first data value. In some embodiments, the device may further include a first memory device operative to look up a second data value based on the first data value, where the second data value is a representation of the first data value encoded according to an encoding scheme that allows clock recovery, and where the memory device is operative to be configured according to a plurality of line encoding schemes. In various embodiments, the device may further include a first output port operative to provide an output signal, where the output signal comprises one or more data values including the second data value.

Abstract: A prediction error calculation part calculates a prediction error for each input data. A prediction error encoding part generates a prediction error code by encoding the value of the prediction error. A run-length counting part counts the run-length of the prediction error. When the value of the prediction error changes, a run-length encoding part generates a run-length code by encoding the run-length counted. A code connecting part generates a connected code by connecting the run-length code to the prediction error code of a corresponding prediction error. When the value of the prediction error is a particular value, a prediction error checking part selects a connected code for the prediction error, as an output code. When the value of the prediction error is a different value, the prediction error checking part selects a prediction error code for the prediction error, as an output code. A code output part outputs the output code selected.

Abstract: Methods and systems for digital control utilizing oversampling.

Abstract: Systems and methods for encoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word that can be subdivided into portions of eight bits or less to be encoded using code words having one extra bit than the corresponding portion of the data word. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table. In some embodiments, data words may be less than eight bits wide.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

Abstract: A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.

Abstract: Information that includes first information identifying integer quotients obtained by divisions using prediction residuals or integers not smaller than 0 that increase monotonically with increases in the amplitude of the prediction residuals, as dividends, and a separation parameter decided for a time segment corresponding to the prediction residuals or a mapped integer value of the separation parameter, as a modulus, and second information identifying the remainders obtained when the dividends are divided by the modulus is generated as a code corresponding to the prediction residuals, and each piece of side information that includes the separation parameter is subjected to variable length coding.

Abstract: Methods and apparatus for entropy decoding are disclosed. Compressed input data representing one or more signals is loaded into one or more registers. A first candidate value for a most probable signal case is prepared from the input data. A second candidate value for a least probable signal case is prepared from the input data. A final signal value for the one or more signals is selected from the first and second candidate values and an output bin value is generated based on the final signal value. A processor readable medium having embodied therein processor readable instructions for implementing the method for entropy decoding is also disclosed. In addition, a method of avoiding a branch instruction in an electronic processing algorithm is disclosed.