Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is encoded using a Non Return to Zero Inverted (NRZI) code and a 17 Parity Preserve/Prohibit (17PP) code, determining a 17PP modulated bit stream based upon the coded bit stream using a first selected decoding method, and generating a plurality of decisions by processing the 17PP modulated bit stream using a second selected decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in a source information.

Abstract: A data-processing device includes a plurality of data generation units, a plurality of bit change number calculation units, a bit change number comparison unit, a first data selection unit, and a bit-coupling unit. The data generation unit arranges input data to generate first conversion data based on each prescribed arranging method. The bit change number calculation unit compares values of respective bits in the first conversion data output at the n-th time and the (n+1)-th time by the corresponding data generation unit, and calculates a bit number based on the comparison result as a bit change number. The bit change number comparison unit compares values of the respective bit change numbers, selects the data generation unit, and outputs selection information. The first data selection unit outputs any one first conversion data selected based on the selection information as selection data. Then, the bit-coupling unit couples the selection information.

Abstract: The simulation of film grain in a video image occurs by first creating a block (i.e., a matrix array) of transformed coefficients for a set of cut frequencies fHL, fVL, fHH and fVH associated with a desired grain pattern. (The cut frequencies fHL, fVL, fHH and fVH represent cut-off frequencies, in two dimensions, of a filter that characterizes the desired film grain pattern). The block of transformed coefficients undergoes an inverse transform to yield a bit-accurate film grain sample and the bit accurate sample undergoes scaling to enable blending with a video signal to simulate film grain in the signal.

Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is generated by encoding source information using a Non Return to Zero Inverted (NRZI) code, selecting an NRZI decoding method based on one or more parameters associated with noise in the received coded bit stream, and generating a plurality of decisions by processing the received coded bit stream using the selected NRZI decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in the source information.

Abstract: An improved transmission protocol is used to transmit a signal between two components of an electronic device. The improved transmission protocol is configured to reduce the number of simultaneous channel transitions that occur when multiple signal channels are transmitted in parallel. Reducing the number of simultaneous channel transitions is beneficial because a signal that is subject to skew, distortion, or electromagnetic interference during transmission may have a shorter settling time when fewer channels undergo a transition simultaneously. When the protocol is used to transmit a signal from a controller to an optical pickup unit in an optical data storage system, the reduced settling times allow for a higher data transmission rate.

Abstract: In a method for decoding digital information, a bit-stream signal comprising binary information is received at a digital receiver utilizing wired communication. The received bit-stream signal is sampled for each binary value at least two different sampling points within an eye pattern associated with the related binary value in order to obtain a hard-bit value for each sampling point. A single soft-bit value for each binary value based on the hard-bit values of the relevant binary value is generated and the bit value of the binary value is determined by subjecting the soft-bit values to a soft-decision algorithm.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: According to one embodiment, method for decoding encoded data comprises a hardware module including circuitry to process a data stream. The data stream includes one or more encoded symbols each including a code assigned to a corresponding symbol. A set of least frequently occurring symbols are assigned a common code to encode those symbols within the data stream. Data blocks are generated each containing a data stream portion. One or more encoded symbols within each data block are identified by comparing data block portions to maximum code values for corresponding code lengths to determine a code length for each data block portion. A starting location for the identified encoded symbols within each data block is determined based on the determined code lengths.

Abstract: According to one embodiment, an apparatus for decoding encoded data comprises a hardware module including circuitry to process a data stream. The data stream includes one or more encoded symbols each including a code assigned to a corresponding symbol. A set of least frequently occurring symbols are assigned a common code to encode those symbols within the data stream. Data blocks are generated each containing a data stream portion. One or more encoded symbols within each data block are identified by comparing data block portions to maximum code values for corresponding code lengths to determine a code length for each data block portion. A starting location for the identified encoded symbols within each data block is determined based on the determined code lengths. Embodiments of the present invention further include related methods and computer program products for decoding encoded data.

Abstract: A method of compressing data is provided. In one implementation, the method includes compressing data with a plurality of compression schemes, where the compressing is computer implemented. Also, in one implementation, the plurality of compression schemes include a first compression scheme and a second compression scheme and the compressing includes compressing a first portion of the data with the first compression scheme and compressing a second portion of the data with the second compression scheme, where the second compression scheme is different from the first compression scheme. In one implementation, the method further includes determining a suitable compression scheme from the plurality of compression schemes with which to compress each portion of the data, where the determining is computer implemented. In one implementation, the data is configuration data for configuring an IC.

Abstract: A method for encoding data to be placed into a weight constrained memory array includes designating a set of crosspoints within a crossbar memory array as indicator crosspoints and a set of crosspoints within the memory array as data crosspoints, the set of indicator crosspoints selected so that a net number of times that each data crosspoint has been flipped can be determined from a subset of the set of indicator crosspoints, placing an input stream of data into a matrix corresponding to crosspoints within the memory array, bits of the input stream being placed into matrix elements that correspond to data crosspoints of the memory array, setting each matrix element corresponding to indicator crosspoints to a value corresponding to a fixed resistive state, and flipping each bit corresponding to a conductor of the memory array until no conductors within the memory array violate a weight constraint.

Abstract: A compressed state sequence s is determined directly from the input sequence of data x. A deterministic function ƒ(x) only tracks unique state transitions, and not the dwell times in each state. A polynomial time compressed state sequence inference method outperforms conventional compressed state sequence inference techniques.

Abstract: A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2m pieces of code words selected to have a tendency that the number of symbols “1” is small among the 2n pieces of code words of n bits are associated with the 2m pieces of data words of m bits and a coding unit that encodes input data words of m bits on the basis of the transform table.

Abstract: An encoding apparatus that converts m-bit data words into n-bit code words, where m and n are both integers and satisfy an expression 2n?2m×2, includes a first conversion table in which 2m m-bit data words are associated with 2m n-bit code words selected from 2n n-bit code words, a second conversion table in which the 2m m-bit data words are associated with 2m n-bit code words that have been selected from the 2n n-bit code words and that do not overlap with the 2m n-bit code words in the first conversion table, and an encoder configured to select and output an n-bit code word with which an m-bit data word that has been input is associated in the first conversion table or an n-bit code word with which the m-bit data word that has been input is associated in the second conversion table, the selected and output n-bit code word having a smaller number of symbols “1”.

Abstract: Method and apparatus for variable length code (VLC) encoding is described. In some examples, a symbol of frequency transform values having a run and a level is VLC encoded. An address is generated, at a processor, for a lookup table (LUT) in a memory based on the run and the level, the LUT storing VLC entries for all possible combinations of run values ranging from minimum to maximum runs and level values ranging from minimum to maximum levels, each of the VLC entries including a flag indicative of an escape mode. A VLC entry is read from the LUT using the address. A VLC code and bit length are obtained from the VLC entry if the flag in the VLC entry is a first value. A fixed length VLC code is generated from an escape code, the run, and the level if the flag in the VLC entry is a second value.

Abstract: This application relates to decoding signals that carry clock and data information. In particular, it relates to construction a time-varying histogram of inter-arrival times between pulse edges and using the histogram to identify whether a pulse edge encodes a single length interval, a double length interval or some longer length interval. Further details and embodiments of the technology disclosed are provided in the drawings, detailed description and claims.

Abstract: Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is ??? or less in an RLL code word over a range from bit p?? to bit p+??1 of the RLL code word and that a ?-bit error correcting code parity sequence is inserted between bit p?1 and bit p of the RLL code word, where ? is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.

Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.

Abstract: A prediction error calculation part calculates a prediction error for each input data. A prediction error encoding part generates a prediction error code by encoding the value of the prediction error. A run-length counting part counts the run-length of the prediction error. When the value of the prediction error changes, a run-length encoding part generates a run-length code by encoding the run-length counted. A code connecting part generates a connected code by connecting the run-length code to the prediction error code of a corresponding prediction error. When the value of the prediction error is a particular value, a prediction error checking part selects a connected code for the prediction error, as an output code. When the value of the prediction error is a different value, the prediction error checking part selects a prediction error code for the prediction error, as an output code. A code output part outputs the output code selected.

Abstract: Systems and methods are disclosed for storing deduplicated images in which a portion of the image is stored in encoded form directly in a hash table, the method comprising: organizing unique content of each data object as a plurality of content segments and storing the content segments in a data store; receiving content to be included in the deduplicated image of the data object; determining if the received content may be encoded using a predefined non-lossy encoding technique and in which the encoded value would fit within the field for containing a hash signature; if so, placing the encoding in the field and marking the hash structure to indicate that the field contains encoded content; otherwise, generating a hash signature for the received content and placing the hash signature in the field and placing the received content in a corresponding content segment if it is unique.

Abstract: Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. A decoder receives and decodes the codewords by comparing symbols on node pairs for which the symbols expressed in the prior code word were alike and decoding the results of those comparisons.

Abstract: A data demodulator includes: a conversion means for converting an RLL code obtained by converting data in which information bits including specific bits are inserted at fixed intervals which is included in an input signal in accordance with a modulation table having variable-length conversion rules into data in accordance with a demodulation table corresponding to the modulation table; a determination means for determining control segments for performing calculation intended by the information bits from the converted data; a calculation means for executing calculation intended by the specific bit inserted in the control segment different from a calculation target with respect to the data of the control segment as the calculation target; and a correction output means for selecting one of first data converted by the conversion means and second data obtained by converting the RLL code of the input signal corrected based on the calculation result in accordance with the demodulation table and outputting the data.

Abstract: Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0?i<k×m) is assigned to each symbol of k×m error correction code words and xij is denoting the number of symbols included in n symbols of a jth (j is an integer satisfying relations 0?j<m) code word of m error correction code words to serve as symbols corresponding to the address i of an information word of an RLL code, for any j, the interleaving section interleaves a series inside an information word of the RLL code word so that the following relations are satisfied: ? i ? x ij = n ? ? and ? ? x ij > 0.

Abstract: M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2m) of data patterns in the m-bit data but that the n-bit data has Hamming Weights (HWs) with minimum (smallest possible) variation. Specifically, encoder logic is configured to receive 2m of m-bit data patterns and encode the 2m of m-bit data patterns to n-bit encoded data patterns, n being greater than m and me being a positive integer greater than one. The encoder logic is configured to map the 2m m-bit data patterns to a subset of 2m of the n-bit encoded data patterns, and the n-bit data patterns in said subset has a minimum (smallest possible) range of Hamming Weight variation while the number of the n-bit data patterns in said subset is not less than 2m.

Abstract: The invention relates to the digital signal requantization, at a given quantization step size, of a first word received in a first period of time and encoded in a first number of bits, into a second word, with a quantization error equal to a third number. A sequence of third words is outputted, equal to the second word, with the sequence subdivided into a first group comprising a number of third words that is equal to the third number and a second group of third words. Before outputting them, the correction means adds a least significant bit to the third words of the first group and adds or subtracts least significant bits to or from the third words of the second group, such that the sum of the least significant bits added to and subtracted from the second group is zero.

Abstract: A data modulation apparatus includes: insertion means for inserting information bits into data at a predetermined interval; conversion means for converting the data into which the information bits are inserted into an RLL code based on a modulation table that has a variable-length conversion rule; setting means for setting a control section that is used for calculating a value of the information bit; and determination means for determining the value of the information bit inserted into the control section that is different from a calculation target by calculating the code of the control section.

Abstract: Method and system are disclosed for expanding a reference number range without altering existing data storage length. Such reference numbers may include employee numbers, social security numbers, customer account numbers, and the like. The method/system takes advantage of the way decimal numbers are stored by computers to allow text to be used in numeric reference numbers. In one implementation, letters A-Z are used for the leftmost position, increasing the domain count of reference numbers from 10 to 36 for that position. A reference number expansion utility is then used to convert the additional reference numbers to and from the existing data storage format.

Abstract: A method of satisfying a specified run length constraint is disclosed. A systematically error correction encoded sequence of received symbols is received, wherein the received symbols include data symbols and parity symbols. The parity symbols are interleaved with the data symbols to produce interleaved symbols that satisfy the specified run length constraint.

Abstract: Embodiments provide for a method for eliminating pathological sequences in a serial bit stream. Parallel data words having a first bit length are received. The received data words may be analyzed for a pathological sequence. If a pathological sequence is present in a data word, the data word containing the pathological sequence may be segmented into data segments having bit lengths less than a pathological sequence. The data word may be reformatted by generating reformatted data words having a second bit length. The reformatted data words may contain at least one of the data segments and the second bit length is greater than the first bit length. The reformatting may be performed by adding framing bits to the segments to form the reformatted data words. The reformatted data words are transmitted in place of the data word containing the pathological sequence.

Abstract: A compression engine starts compressing data by a preset first compression rule, compresses the following data by a second compression rule when the characteristics of the data satisfy a predetermined switching condition, and returns to the first compression rule when the characteristics of the data do not satisfy the switching condition to compress the data and the following data. A decompression engine starts decompressing compressed data by a first decompression rule corresponding to the first compression rule, decompresses the following compressed data by a second decompression rule corresponding to the second compression rule when the characteristics of the data after decompression satisfy the switching condition, and returns to the first decompression rule when the characteristics of the data after decompression do not satisfy the switching condition to decompress the data and the following compressed data.

Abstract: An encoder performs context-adaptive arithmetic encoding of transform coefficient data. For example, an encoder switches between coding of direct levels of quantized transform coefficient data and run-level coding of run lengths and levels of quantized transform coefficient data. The encoder can determine when to switch between coding modes based on a pre-determined switch point or by counting consecutive coefficients having a predominant value (e.g., zero). A decoder performs corresponding context-adaptive arithmetic decoding.

Abstract: An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.

Abstract: A modulation apparatus includes: a modulation section that modulates, in accordance with a correlation table where a data sequence with a predetermined number of bits is associated with a code sequence with a predetermined number of bits, the data sequence into the code sequence to allow a predetermined demodulation section to demodulate the code sequence into the data sequence in accordance with the correlation table, wherein the code sequence is, on NRZI method, a MSN code sequence where a null point of a frequency spectrum on a recording channel or communication channel of the code sequence is matched with a null point of a frequency spectrum of a PR equalized signal including the code sequence and a minimum run length is limited to be greater or equal to one.

Abstract: A coding apparatus includes a transform table in which with regard to data words of m bits and code words of n bits where n and m are both integers and also n>m is established, 2m pieces of code words selected to have a tendency that the number of symbols “1” is small among the 2n pieces of code words of n bits are associated with the 2m pieces of data words of m bits and a coding unit that encodes input data words of m bits on the basis of the transform table.

Abstract: Systems and methods are provided for encoding and decoding constrained codewords using an enumerative coding graph. The constrained codewords may contain run-length and DC level limits. The enumerative coding graph contains a series of states and each state has multiple branches that lead to other states. Each state in the enumerative coding graph is associated with at least two bits of an enumerative codeword. Configuring the structure of the graph and cardinalities associated with each state allows the encoder to generate a code that conforms to defined constraints.

Abstract: In a coding system, input data within a system is encoded. The input data might include sequences of symbols that repeat in the input data or occur in other input data encoded in the system. The encoding includes determining a target segment size, determining a window size, identifying a fingerprint within a window of symbols at an offset in the input data, determining whether the offset is to be designated as a cut point and segmenting the input data as indicated by the set of cut points. For each segment so identified, the encoder determines whether the segment is to be a referenced segment or an unreferenced segment, replacing the segment data of each referenced segment with a reference label and storing a reference binding in a persistent segment store for each referenced segment, if needed.

Abstract: A high-rate constrained code is provided to encode/decode channel data. A transformer translates binary channel data into an arbitrary alphabet size. The transformer selects an indicator word and makes forbidden prefix substitutions in the data to be transformed. A finite-state encoder imposes some user-defined constraint on the transformed data before the data is transferred to the channel. The high-rate constrained coding technique may be used to produce high-rate DC-limited and run-length-limited codes. The high-rate code can be used in tandem with error-correcting codes.

Abstract: The invention provides a decoding apparatus which guarantees a decoding speed of a predetermined unit. To this end, the decoding apparatus includes a shifter which detects a start bit of a codeword from coded data, a table which stores decode values of a plurality of symbol data at one address, a table which is used to store a shift amount of the shifter, a table which generates a data length of the decode values of the plurality of symbol data, a decoder which is used to generate an address of the first table from the coded data, a decoder which is used to generate an address of the second and third tables from the coded data, and a packer which couples or separates the decoded values of the plurality of symbol data to data for the predetermined fixed number of bits.

Abstract: The present disclosure includes apparatus, systems and techniques relating to lossless data compression. In some implementations, an apparatus includes a memory module to store data. The memory module includes a first buffer portion to store encoded symbols of the data, and a second buffer portion to store symbols of the data to be encoded. The apparatus includes an encoder to compare the symbols stored in the second buffer portion with the encoded symbols stored in the first buffer portion and to compress the data. The encoder can operate in a first encoding mode to encode the symbols in the second buffer portion with corresponding codewords until detecting a repeated pattern of symbols in the second buffer portion that matches the encoded symbols in the first buffer portion. The encoder can operate in a second encoding mode responsive to detecting the repeated pattern.

Abstract: In one of many possible embodiments, a system for optimizing bit utilization in data encoding is provided. The exemplary system includes a data processing subsystem configured to identify a total number of unique characters within a set of data, which number represents an original base of representation of the set of data. The data processing subsystem is further configured to convert the set of data to a base of representation that is higher than the original base of representation and then encode the base-converted data with a fixed-length encoding scheme.

Abstract: A method, a codebook, and a Base Station (BS) for precoding are provided. The precoding method includes: obtaining a total uplink power of a User Equipment (UE); if the total uplink power is greater than ¾ of a rated total transmit power of antennas, selecting a codeword from a first codebook with imbalanced power between layers; otherwise, selecting a codeword from the first codebook and a second codebook with balanced power between layers, so as for precoding data to be transmitted according to the selected codeword. Thus, a loss of an antenna performance at a high signal-to-noise ratio is reduced, and the loss of the power amplification of the antenna is reduced if the transmit power of the antenna is restricted.

Abstract: A storage device includes a signal processor that receives an input signal that includes a direct current (DC) voltage offset. An encoder receives the input signal from the signal processor and selectively inverts portions of the input signal based on at least one of an average DC value and a weighted DC value of the input signal.

Abstract: An encoding scheme generates an encoded nine bit code word from each input eight bit data word. The coding scheme is such that the encoded data words have advantageous properties, such as a minimum of two polarity transitions in each encoded data word, and a maximum of five bits without a polarity transition. Five of the bits from the input eight bit data word appear unchanged in the encoded data word, while the other four bits of the encoded data word are obtained by applying appropriate logical operators to the remaining three bits of the input data word in combination with two of the five bits that appear unchanged in the encoded data word. Exception codes can also be defined, that is, nine bit code words that cannot be obtained from any eight bit data word by means of the coding scheme, and can be used to embed control information into the data stream. For example, the exception codes may advantageously have six or seven bits without a polarity transition.

Abstract: Example embodiments may provide a memory device and memory data programming method. The memory device according to example embodiments may encode a first data page to generate at least one first codeword and encode a second data page to generate a second codeword. The memory device may generate the first codeword with at least one of a maximum value of a number of successive ones and a second maximum value of a number of successive zeros. The memory device may program the at least one first codeword and the at least one second codeword to a plurality of multi-bit cells.

Abstract: An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency.

Abstract: A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of ‘1’ bits and ‘0’ bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.

Abstract: A method, apparatus and system employing a 17B/20B coder is disclosed. The 17B/20B coder to receive an incoming stream including a 17B block and a 20B block, and partition the 17B block into first blocks, and partitioning the 20B into second blocks. The coder is further to code 17B to 20B of memory using one or more serial lines for communication is performed, wherein coding includes coding the first blocks of the 17B block and the second blocks of the 20B block, wherein the coding of the first and second blocks is performed such that a maximum run length is maintained.

Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2k evaluation values and outputting the maximum value as an evaluation result.

Abstract: Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is ??? or less in an RLL code word over a range from bit p?? to bit p+??1 of the RLL code word and that a ?-bit error correcting code parity sequence is inserted between bit p?1 and bit p of the RLL code word, where ? is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.