Abstract: A run-length limited (RLL) DC-free encoder includes a determination module that receives input words and that determines whether each input word is a member of one of a first input set and a second input set, a first mapping module that maps the first ones of the input words of the first input set to corresponding output words that are run-length limited and DC-free, a second mapping module that maps the second ones of the input words of the second input set to corresponding output words that are run-length limited and have a negative digital sum, and an inverter module that selectively inverts the output words from the second mapping module based on a cumulative digital sum of the output words.

Abstract: A modulation method for symbols in a frame of a compact disc includes the steps of receiving a plurality of data words, modulating each data word into a code word of a corresponding data symbol, and providing a plurality of combinations of potential merge bits to be inserted between successive symbols of the frame. At least one combination of candidate merge bits is generated according to the plurality of combinations of potential merge bits, a data symbol immediately preceding the location of the candidate merge bits, and a data symbol immediately succeeding the location of the candidate merge bits. The combination of candidate merge bits which minimizes (optimizes) the absolute cumulative DSV is selected when a subsequent group of possible combinations of candidate merge bits is detected or after a predetermined delay, and the selected combination of candidate merge bits is inserted between the two successive data symbols.

Abstract: A method and apparatus for encoding and decoding data for a recording system. The method of encoding data involves encoding input data into a predetermined code and precoding the predetermined code so that output levels of a channel can be detected, the channel being defined by a predetermined channel polynomial.

Abstract: Method of converting information words, which includes receiving m-bit information words, where m is an integer, and converting the m-bit information words into n-bit code words based on a code conversion table including a plurality of coding states, where n is an integer greater than m. The plurality of coding states are categorized into a first kind or a second kind and a number of coding states of the first kind is greater than a number of coding states of the second kind. Each coding state includes at least two code words of a same value representing information words of a different value, and a minimum number of zeros between consecutive ones in the n-bit code words is 1.

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: A modulation system includes an encoder for transferring data words to tentative code words. A DSV control bit generator determines the value of a DSV control bit according to the data words or the tentative code words to optimize the cumulative DSVs corresponding tentative code words, wherein the DSV control bit generator determines the value of a current DSV control bit when at least a subsequent DSV control bit is detected. A final code word generator generates final code words according to the determined DSV control bit and the tentative code words.

Abstract: A method and a system for communicating data in a communication channel are provided. The method includes the identification of a sequence of bits recurring in the data, and generating a locking pattern. The locking pattern includes locking symbols and a random bit pattern. The method also includes sending the locking pattern within the data. The locking pattern is received by a receiver and is used to lock the receiver and ignore the recurring bit sequence.

Abstract: A data word is error correction encoded to provide a worst case codeword without bit transitions between worst case codeword bits. A modulation bit is calculated as a function of the worst case codeword. The modulation bit has a bit polarity opposite a bit polarity of the worst case codeword bits. The worst case codeword bits are added with the modulation bit to form a modulated code word.

Abstract: The claimed embodiments provide methods, apparatuses and systems directed to run-length limited (RLL) coding of data. In one implementation, concatenatable RLL codes with run lengths of zeroes not exceeding k are constructed for any rate N/(N+1) where N?2k?2+k?1. As code rates increase, the value of k departs from the minimum possible value more slowly than that of many other codes. Further, occurrences of k-bit run lengths occur only at the juncture of two codewords. Due to this, the codes are mostly k?1. This quality makes the codes ideal for parity bit insertion applications such as LDPC channels. The method, in one implementation, places the bit addresses of violating sequences in a table at the beginning of the codeword, and the user data, occupying the locations where the table entries are placed, are moved into the locations of the violating sequences. This is done iteratively and in a way which provides for cases in which the violating sequence is inside the address table itself.

Abstract: A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.

Abstract: An MTR encoder includes convolution units that perform convolution of input data using additional bits, MTR encoding units that MTR-encode data obtained by the convolution units, RDS calculating units and on-bit sequence checking units that calculate RDSs and counts the number of sequential on-bits of the data MTR-encoded by the MTR encoding units, respectively, and a selecting unit that selects optimum data based on the RDSs and the number of sequential on-bits.

Abstract: An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

Abstract: Disclosed is a method of digital data conversion. The method includes binding input digital data into unit blocks constituted by a plurality of bytes, modulation-coding each byte of the input data blocks by using a code conversion table, and allocating a merging bit in block unit for the modulation-coded input data in block unit.

Abstract: An EFM/EFM+ encoder and a method thereof, performing digital sum value (DSV) protection in an Eight-to-Fourteen/Eight-to-Fourteen Plus (EFM/EFM+) encoding system to generate a data frame to be recorded on a recording medium. The method comprises modulating source data to the data frame having a predetermined number of channel bits, determining merging bits and DSV based on the channel bits, and changing the predetermined number of the channel bits in the data frame based on the DSV and the merging bits. The changing the predetermined number of the channel bits comprises inserting or removing a channel bit at the end of the data frame.

Abstract: A variable-length coding apparatus having a smaller circuit scale, which flexibly handles identifier insertion processing in correspondence with various coding schemes, and which performs fine code amount control and adaptive erroneous operation control, and an image coding apparatus having the variable-length coding apparatus. The variable-length coding apparatus converts quantized data obtained by quantizing image data into variable-length code data, generates a code data string having a predetermined data structure, and inserts padding bits and identifier into the variable-length code data based on an externally-input instruction. Further, the image coding apparatus having the variable-length coding apparatus changes quantization values based on the total code amount of code data string generated by the variable-length coding apparatus.

Abstract: A position in runlength compression data corresponding to a desired position in original data can be found fast. Index correspondence information is generated for representing correspondence between indexes representing predetermined positions in data arrangement of the original data having a plurality of values and positions corresponding thereto in the runlength compression data. The index closest to the desired position in the original data and an offset of the desired position from the index are found. Based on the index correspondence information, the corresponding index in the runlength compression data is found. The position corresponding to the desired position is then found in the runlength compression data, based on the corresponding index and the offset.

Abstract: A method of converting m-bit information words to a run-length constrained modulated signal includes converting the information words into n-bit code words. The available code words are distributed over at least one group (G1) of a first type and at least one group (G2) of a second type. The selection of a code word belonging to the group of the first or second type establishes a coding state of the first type (S1) or one of a number r of coding states (S2, S3) of the second type, depending on the current information word. For each information word, a subset of code words is available, this subset having at least one disjunct code word for each of the r coding states. The selection from the subset of the code word to be delivered is based the coding state, on dynamically verifying the run-length constraint for the sequence of code words, and on an additional criterion, like the low frequency content of the modulated signal.

Abstract: A data identification method including: a first step; a second step; a third step; and a fourth step, and the third and fourth steps being repeated until an identification result included in the table of recording modulation codes is obtained at the third step.

Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2^k different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2^k evaluation values and outputting the maximum value as an evaluation result.

Abstract: We describe a voltage level coding system and method. The voltage level coding system includes a level encoder having an input to receive data segments coded using a first code and an output to supply second data codes indicating one of 2N plus at least one additional voltage level to which each data segment is assigned. A converter converts the second data codes into such voltage levels. A controller output supplies the voltage levels. A method for coding digital data includes determining a first data transition, generating a code that includes at least one additional level that minimizes data skew in the first data transition, and coding the first data transition with the additional level in the code.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b2 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1(b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: A modulation method for a first data string having a plurality of symbols is disclosed. The method includes: appending a data string to the first data string to form a second data string; and converting the second data string to a code word sequence by converting each of the symbols in the first data string to a code word according to predetermined modulation rules and a symbol set selected from the second data string. Each code word has a first fixed number of bits, each symbol has a second fixed number of bits, and each symbol set has a fixed number of symbols.

Abstract: The present invention allows two different block codes to be encoded by one-type of encoding section. A first-point-fixed encoding section divides m-bit data into a first-half code and a second-half code, and encodes them into an n-bit provisional code with fixed start-point state. A code A/B counter receives a reset-signal and outputs a code selection signal to a code-order reversing section and a top-code correction section. The code-order reversing section receives a codeword excluding the top code from the start-point-fixed encoding section; and outputs the codeword as is, when the code selection signal indicates a code B, and reverses the order of the codeword to generate a new codeword, and outputs the new codeword to a latch, when the code selection signal indicates a code A. The top-code correction section determines whether the top code needs to be modified, and modifies the top code, if necessary.

Abstract: A modulation table for converting data with a basic data length of m bits into a variable length code (d,k;m,n;r) is provided. The modulation table includes a basic table for converting data patterns into code patterns and a replacement table for replacing data patterns with code patterns. The replacement table includes minimum-run-successive-occurrence limiting data patterns for limiting the number of times of successive occurrence of the minimum run to N (N>1) or less and minimum-run-successive-occurrence limiting code patterns corresponding to the minimum-run-successive-occurrence limiting data patterns. At least one of the minimum-run-successive-occurrence limiting code patterns includes an undetermined code.

Abstract: A modulation table configured to convert data having a basic data length of m bits into variable length code (d, k; m, n; r) is provided. The modulation table includes a maximum constraint length r>1, a minimum run of d (d>0), a maximum run of k, and a basic codeword length of n bits. The modulation table includes: a basic table configured to convert patterns composed of data having a data length of m bits into patterns composed of codes of variable length code having a codeword length of n bits; and a substitution table configured to replace patterns composed of substitution data with patterns composed of substitution codes. The substitution table includes patterns composed of minimum run successive occurrence limiting data limiting the minimum run to a maximum of N (N>1) times and code patterns composed of substitution codes corresponding to the minimum run successive occurrence limiting data.

Abstract: An encoder and decoder for encoding data bits of a binary source signal into a stream of data bits of a binary channel signal and vice versa includes a conversion table used to map m-bit source words to codeword having a variable code length with a basic code length of n bits and a total code length of n*i bits, i being an integer of at least 1. The conversion table preserves the parity of the m-bit source words over the codeword and limits a characteristic of the codeword specified for each starting bit position in the code word.

Abstract: This invention provides an encoding apparatus including a group generating unit that puts plural information values to be compressed together and generates a group of information values to be compressed; a code assignment unit that assigns a code to each group generated by the group generating unit; and an information encoding unit that encodes the information values to be compressed belonging to each group, using the code assigned to each group.

Abstract: A digital sum value (DSV) control apparatus inserts a DC control bit for each DC control block. The apparatus includes a first DSV accumulated value comparator for setting a target flag to a DC control bit for a first DC control block, a second DSV accumulated value comparator for comparing a first DSV accumulated value accumulated and calculated from DSV values of the first DC control block with a second DSV accumulated value accumulated and calculated from DSV values of a plurality of DC control blocks subsequent to the first DC control block, and a DC control bit determination output section for determining a value of a DC control bit for the first control block according to an output of the first and the second DSV accumulated value comparators.

Abstract: A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (10A), a DSV change amount calculator (15) calculates change amounts (?DSVa, ?DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (11). A modulated code determinator (13) compares the change amounts (?DSVa, ?DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector (14) selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (13), and outputs the selected code as a modulated code (CODE) for source data (DATA).

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo-random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo-random data streams. An encoder RLL-modulates the plurality of types of pseudo-random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: In a data demodulating method and apparatus, and a code arranging method, a multiplexer multiplexes an input data stream divided by a predetermined length into a plurality of types of pseudo random data streams using multiplexed information of predetermined bits by applying a predetermined multiplexing method to each of the pseudo random data streams. An encoder RLL-modulates the plurality of types of pseudo random data streams to create a modulated code stream including a minimum of DC components. The multiplexer generates the random data streams by inconsecutively scrambling the input data stream using the multiplexed information. The encoder weak DC-free RLL-modulates each of the multiplexed data streams without using a DC control sub code conversion table to which additional bits are added and provides a code stream including a minimum of DC components among multiplexed, RLL-modulated code streams.

Abstract: A dual mode decoder which includes an MB810 decoder; an 8B/10B decoder; a mode detection unit, a first low pass filter; a second low pass filter; an IDLE code detection unit which detects IDLE code and transfers to the mode detection unit; a first switch unit which selectively outputs the 10-bit code input from the first low pass filter and the second low pass filter; a parallel conversion unit which outputs a 10-bit parallel code; a first selection unit which provides the 10-bit parallel code to the decoder determined as the operation decoder between the MB810 decoder and the 8B/10B decoder; and a second selection unit which selectively outputs an 8-bit code corresponding to the 10-bit parallel code input form the decoder determined as the operation decoder.

Abstract: A communications channel comprises a seed selector that selectively removes X M-bit symbols of user data from a seed set comprising Y M-bit symbols and that selects a scrambling seed from Y-X symbols remaining in the seed set, where X, Y and M are integers greater than one. A Hamming weight coding device that determines a Hamming weight of symbols of scrambled user data that are generated based on the user data and the selected scrambling seed and that selectively codes the symbols depending upon the determined Hamming weight.

Abstract: An information recording processing apparatus includes a modulating portion operable to modulate write data on an information recording medium and to create code data thereby; and a DC level calculating portion operable to calculate a DC level corresponding to a given run length based on a coefficient defined in accordance with the run length of a component bit of the code data, wherein DC-controlled code data is created or selected based on a DC level addition result based on the DC level corresponding to the given run length, and the created or selected data is defined as write data onto the information recording medium.

Abstract: RLL (Run Length Limited) code is a well-known channel coding technique, which has no error correction ability itself. The present invention discloses a decoding method, which corrects the channel bit errors via a modified demodulation table with added demodulation rules without increasing any modification circuit, to reduce channel bit errors of RLL code sequences and improve the decoding accuracy of error correction table.

Abstract: A recording method for converting m-bit data into n-bit (where n>m) bit data whose run length is restricted and recoding the converted data on a recording medium, the recording method comprising the steps of when at least preceded data is data containing a special data pattern, lightening the restriction of the run length; and recording data so that the cumulative value of DC components per unit time increase when the data is reproduced in the state that the run length is restricted.

Abstract: A method of generating and allocating codewords includes allocating one of two selectable codewords b1 and b2 as codeword “b” when a preceding codeword “a” and a following codeword “b” form a code stream X, in which the codewords b1 and b2 have opposite INV values which are parameters indicating whether the number of ‘1s’ contained in a codeword is an odd number or an even number. When the code stream of the preceding codeword “a” and the following codeword b1 is X1, and when the code stream of the preceding codeword “a” and the following codeword b2 is X2, the codewords are allocated such that the INV values of X1 and X2 are maintained to be opposite when the preceding codeword “a” or the following codeword b1 (b2) (b1 or b2) should be replaced by another codeword in compliance with a predetermined boundary condition given between codewords. The codewords are allocated so that a DC suppression capability of the code stream can be maintained.

Abstract: In the coding device and method, m-bit information words are converted into n-bit code words such that the coding rate m/n is greater than ?. The n-bit code words are divided into a first type and a second type, and into coding states of a first kind and a second kind such that an m-bit information word is converted into an n-bit code word of the first or second kind if the previous m-bit information word was converted into an n-bit code word of the first type and is converted into an n-bit code word of the first kind if the previous m-bit information word was converted into an n-bit code word of the second type. In one embodiment, n-bit code words of the first type end in zero, n-bit code words of the second type end in one, n-bit code words of the first kind start with zero, and n-bit code words of the second kind start with zero or one.

Abstract: Context-based adaptive arithmetic coding and decoding methods and apparatuses with improved coding efficiency and video coding and decoding methods and apparatuses using the same are provided. The method for performing context-based adaptive arithmetic coding on a given slice in an enhancement layer frame of a video signal having a multi-layered structure includes steps of resetting a context model for the given slice to a context model for a base layer slice at the same temporal position as the given slice, arithmetically coding a data symbol of the given slice using the reset context model, and updating the context model based on the value of the arithmetically coded data symbol.

Abstract: Techniques for encoding N-binary symbol (NB) source data vectors into M-binary symbol (MB) encoded vectors, M>N>0, are provided. Techniques for decoding are also provided. Exemplary coding and decoding apparatuses are presented, as is an exemplary 8B/10B encoding scheme. Encoded vectors may be disparity dependent or disparity independent. In assigning encoded vectors that have one or more individual binary symbol changes compared with their source data vectors, preference can be given to encoded vectors that are balanced and disparity independent. Whole-vector complementation and individual changes of one or more binary symbols can advantageously be performed substantially in parallel.

Abstract: An MB810 encoder and/or decoder, dual mode encoder and/or decoder, and a method for generating MB810 codes are provided. Twelve state points in the form of a 4×3 matrix on a state transition map are formed with binary unit digital sum variation & alternate sum variation (BUDA). A 10-bit code from 8-bit data is generated outputting a 10-bit code from a predetermined state point to form the matrix. Codes forming a complementary pair from a set of codes capable of arriving at state points forming the matrix are selected. Codes forming the 12 state points by supplementing state points lacked in the codes forming a complementary pair are selected. Control codes including IDLE code from the codes forming the 12 state points are selected. Codes generating the IDLE code by a bit string between neighboring codes among the codes forming the 12 state points are removed.

Abstract: A recording method for converting m-bit data into n-bit (where n>m) data whose run length is restricted and recording the converted data on a recording medium, the recording method comprising the step of selecting first n-bit data according to an immediately preceded n-bit data, first n-bit data immediately followed thereby, and second n-bit data immediately followed thereby so that the cumulative value of DC components per unit time becomes small.

Abstract: An improved method is provided for identifying a repeated codeword in an incoming bit stream. The method includes: receiving an incoming bit stream having an expected codeword repeated a number of times; determining whether a group of incoming data bits correlates to the expected codeword, where each of the incoming data bits in the group need not match the corresponding data bit of the expected codeword; and determining whether the expected code word is repeated over a sequence of incoming data bits.

Abstract: A digital sync signal added in a modulator to a train of codes having a digital sum value, and detected in a demodulator. The digital sync signal has a pattern that breaks a maximum run and a pattern that preserves a minimum run and a maximum run. The digital sync signal has a bit that is selectively determined to be a “0” or a “1” for controlling the digital sum value of the train of codes. The minimum run is repeated no more than a predetermined number of times irrespective of whether the digital sync signal includes the minimum run.

Abstract: A communication system includes an encoder that receives user data and includes running digital sum encoding and turbo encoding. The running digital sum encoding is preserved in an encoder output to a channel. A decoder receives a channel output and comprises running digital sum decoding and turbo decoding to reproduce the user data in a decoder output.

Abstract: Embodiments of the invention allow relatively simple circuits to provide a coding device capable of coding longer bit-length data suitably for disk apparatus and a decoding device capable of decoding the data coded by the coding device. In one embodiment, a coding device comprises: a coder which, based on an M bits code string, produces an (M+1) bits coded string where each of the plural bits which may appear in the M bits code string is limited in run length; a preprocessor which produces an M bits code string by removing (N?M) bits respectively from predefined (N?M) positions of an incoming N bits code string and outputs the M bits code string to the coder; and a postprocessor which produces and outputs an (N+1) bits code string by inserting the (N?M) bits, which are removed by the preprocessor, into predefined (N?M) respective insertion positions of the (M+1) bits coded string output from the coder.

Abstract: A communications channel such as a data storage system removes unwanted bit patterns from user data without using run length limited coding on the user data. A buffer receives the user data. A data dependent scrambler communicates with the buffer and selects one of a plurality of scrambling sequences based the user data stored in the buffer or generates a scrambling sequence based on the user data stored in the buffer. A scrambling device communicates with the data dependent scrambler and scrambles the user data stored in the buffer with the selected scrambling sequence from the data dependent scrambler.

Abstract: A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

Abstract: An integrated circuit like a programmable logic device (“PLD”) includes a communication channel employing 8B/10B coding. Disparity information determined by 8B/10B decoder circuitry in the communication channel is supplied to other circuitry of the PLD so that any requirement for disparity to have a particular value in conjunction with certain received codes can be checked. On the transmitter side, circuitry is provided for selectively forcing the 8B/10B encoder to use a commanded disparity (which can be either positive or negative) under particular circumstances.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part, and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.