Data Rate Conversion Patents (Class 341/61)
  • Patent number: 10403334
    Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventors: Byung Kuk Yoon, Honggyeom Kim
  • Patent number: 10326583
    Abstract: A circuit for receiving and processing a bit stream obtained from an electronic communication bus-system comprises a bit stream processor and bit sampling of the bit stream to provide a sampled output signal. The circuit comprises a frame decoder for decoding a data frame encoded in the sampled output signal, and a clock signal generator for generating a first clock signal for the bit stream processor. The circuit comprises a clock signal downsampler for generating a second clock signal having a lower frequency than the first clock signal, in which the second clock signal is based on a co-occurrence of a clock pulse in the first clock signal and the emission of a bit in the sampled output signal. The bit stream processor is adapted for synchronizing the first clock signal to an external protocol timing of the incoming bit stream.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: June 18, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Jörgen Sturm, Thomas Freitag, Martin Bölter, Anton Babushkin
  • Patent number: 10305675
    Abstract: An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 28, 2019
    Assignees: NTT ELECTRONICS CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasuharu Onuma, Masahiro Tachibana, Etsushi Yamazaki, Kazuhito Takei, Yuki Yoshida, Masayuki Ikeda, Yoshiaki Kisaka, Masahito Tomizawa
  • Patent number: 10236917
    Abstract: Providing memory bandwidth compression in chipkill-correct memory architectures is disclosed. In this regard, a compressed memory controller (CMC) introduces a specified error pattern into chipkill-correct error correcting code (ECC) bits to indicate compressed data. To encode data, the CMC applies a compression algorithm to an uncompressed data block to generate a compressed data block. The CMC then generates ECC data for the compressed data block (i.e., an “inner” ECC segment), appends the inner ECC segment to the compressed data block, and generates ECC data for the compressed data block and the inner ECC segment (i.e., an “outer” ECC segment). The CMC then intentionally inverts a specified plurality of bytes of the outer ECC segment (e.g., in portions of the outer ECC segment stored in different physical memory chips by a chipkill-correct ECC mechanism). The outer ECC segment is then appended to the compressed data block and the inner ECC segment.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Natarajan Vaidhyanathan, Luther James Blackwood, Mattheus Cornelis Antonius Adrianus Heddes, Michael Raymond Trombley, Colin Beaton Verrilli
  • Patent number: 10181914
    Abstract: A digital pre distortion (DPD) calibration coefficient control method and apparatus are applied to a microwave communications device that includes an analog device and a digital device, and can ensure a DPD calibration effect, where the method includes determining, by interpolation and according to DPD calibration coefficients corresponding to at least 2N typical working states of the analog device obtained in advance, a specified DPD calibration coefficient corresponding to a specified working state of the analog device, where N is a quantity of parameters representing a working state of the analog device, and controlling a DPD calibration coefficient according to the determined specified DPD calibration coefficient corresponding to the specified working state of the analog device.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 15, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Changliang Li, Yanzhao Pang, Xiaodong Li
  • Patent number: 10069666
    Abstract: Systems and methods relating to a transceiver architecture that maintains legacy timing by inserting and removing a cyclic prefix at a legacy sampling rate are disclosed. In some embodiments, a system for a receiver comprises an upsampling subsystem, a cyclic prefix removal unit, and a downsampling subsystem. The upsampling subsystem is operable to process a first baseband receive signal that is at a first sampling rate to generate an upsampled baseband receive signal at a second sampling rate that is greater than the first sampling rate. The cyclic prefix removal unit is operable to remove a cyclic prefix from the upsampled baseband receive signal to provide a second baseband receive signal at the second sampling rate. The downsampling subsystem is operable to process the second baseband receive signal to generate a downsampled baseband receive signal at the first sampling rate. In this manner, complexity and power consumption are reduced.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: September 4, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Xingqin Lin, Asbjörn Grövlen, Niklas Johansson, Yi-Pin Eric Wang, Christian Hoymann
  • Patent number: 10051591
    Abstract: A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 14, 2018
    Assignee: Hypres, Inc.
    Inventor: Deepnarayan Gupta
  • Patent number: 10009013
    Abstract: A first stage of a digital filter received input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and (2) the first clock pulse of the first clock.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: June 26, 2018
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventor: Andreas Menkhoff
  • Patent number: 10002618
    Abstract: The subject disclosure is directed towards dynamically computing anti-aliasing filter coefficients for sample rate conversion in digital audio. In one aspect, for each input-to-output sampling rate ratio (pitch) obtained, anti-aliasing filter coefficients are interpolated based upon the pitch (e.g., using the fractional part of the ratio) from two filters (coefficient sets) selected based upon the pitch (e.g., using the integer part of the ratio). The interpolation provides for fine-grained cutoff frequencies, and by re-computation for each pitch, smooth anti-aliasing with dynamically changing ratios.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: June 19, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Thomas Craig Savell
  • Patent number: 9985803
    Abstract: Embodiments include methods and devices for processing a digital composite signal generated at a first sampling rate. The signal includes at least first and second carrier-bands arranged to define a first inner gap between the carrier-bands. The first inner gap includes at least a first gap between the highest frequency of the first carrier-band and the lowest frequency of the second carrier-band. The digital composite signal has a predetermined instantaneous bandwidth that is lower than a sampling bandwidth. An outer gap located outside the instantaneous bandwidth and within the sampling bandwidth is determined. The first inner gap is reduced to define a second inner gap, where a width of the second inner gap is related to a width of the outer gap. The resulting folded digital composite signal is decimated to a second sampling rate lower than the first sampling rate thereby creating a decimated folded digital composite signal.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: May 29, 2018
    Assignee: NXP USA, INC.
    Inventors: Vincent Martinez, Frederic Fernez
  • Patent number: 9947362
    Abstract: A system may include an interpolator circuit configured to receive a first signal with a first rate and to generate an interpolated signal with a second rate. The system may include a cancellation circuit configured to determine an interference component signal based on the interpolated signal. The system may further comprise an adder configured to receive a second signal with the second rate and to cancel interference in the second signal using the interference component signal to generate a cleaned signal.
    Type: Grant
    Filed: June 25, 2016
    Date of Patent: April 17, 2018
    Assignee: Seagate Technology LLC
    Inventors: Raman Venkataramani, Belkacem Derras, William Michael Radich
  • Patent number: 9917662
    Abstract: A digital measurement input for an electric automation device has a receiving device configured to receive digital input measurement values generated by sampling an analog measurement signal at a first sampling rate, and a signal converting device configured to generate digital output measurement values from the digital input measurement values and to provide digital output measurement values. The sampling rate and sampling times of each digital output measurement value is adapted to a specified sampling rate and/or specified sampling time. The signal converting device has a digital encoder filter on the input side and a digital decoder filter on the output side, between which an interpolator is provided. The encoder filter, the interpolator, and the decoder filter are matched to one another so as to adapt the sampling rate and/or sampling time of the digital input measurement values.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 13, 2018
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Andreas Jurisch
  • Patent number: 9822765
    Abstract: The invention relates to a wind power plant control system arranged for controlling one or more wind turbine generators in a wind power plant, wherein the wind power plant control system comprises a power plant controller and a modeling unit, the modeling unit being operatively coupled to the power plant controller. The modeling unit is arranged to calculate estimated values of electrical output parameters from the one or more wind turbine generators, and to output said estimated values to the power plant controller. The power plant controller is arranged for determining reference signals for dispatching to the one or more wind turbine generators, wherein the estimated values of said electrical output parameters are used by the power plant controller in the determination of said reference signals. The invention also relates to a corresponding method of controlling a wind power plant.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 21, 2017
    Assignee: VESTAS WIND SYSTEMS A/S
    Inventors: Mehrdad Babazadeh, Kouroush Nayebi
  • Patent number: 9794476
    Abstract: Imager arrays, array camera modules, and array cameras in accordance with embodiments of the invention utilize pixel apertures to control the amount of aliasing present in captured images of a scene. One embodiment includes a plurality of focal planes, control circuitry configured to control the capture of image information by the pixels within the focal planes, and sampling circuitry configured to convert pixel outputs into digital pixel data. In addition, the pixels in the plurality of focal planes include a pixel stack including a microlens and an active area, where light incident on the surface of the microlens is focused onto the active area by the microlens and the active area samples the incident light to capture image information, and the pixel stack defines a pixel area and includes a pixel aperture, where the size of the pixel apertures is smaller than the pixel area.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 17, 2017
    Assignee: FotoNation Cayman Limited
    Inventors: Shree Nayar, Kartik Venkataraman, Bedabrata Pain, Dan Lelescu
  • Patent number: 9787457
    Abstract: A signal interface unit in a radio system includes an external device interface configured to receive a downlink asynchronous radio carrier signal for a radio frequency carrier from an external device; a clock conversion unit communicatively coupled to the external device interface and configured to re-clock the downlink asynchronous radio carrier signal to a master clock of the radio system from the clock of the external device; and an antenna side interface configured to communicate at least one of the re-clocked downlink asynchronous radio carrier signal and a downlink digitized radio frequency signal based on the re-clocked downlink asynchronous radio carrier signal to an antenna unit.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: October 10, 2017
    Assignee: CommScope Technologies LLC
    Inventors: Dean Zavadsky, Philip M. Wala
  • Patent number: 9690425
    Abstract: System and methods are provided for tracking baseline signals for touch detection. The system includes: a comparison network configured to determine whether an input baseline signal is within a tracking range; a filter network configured to generate an output baseline signal for touch detection based at least in part on the input baseline signal according to one or more filter parameters; and a signal processing component configured to update the one or more filter parameters based at least in part on the determination of whether the input baseline signal is within the tracking range.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: June 27, 2017
    Assignee: MARVEL WORLD TRADE LTD.
    Inventors: Kanke Gao, Bike Xie, Songping Wu
  • Patent number: 9692418
    Abstract: An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: June 27, 2017
    Assignee: Altera Corporation
    Inventors: David Lewis, Herman Henry Schmit, Carl Ebeling
  • Patent number: 9661596
    Abstract: A system and method for receiving a radio frequency signal, comprising a device for digitizing, without prior alteration of frequency, an analog radio frequency representation of each of a plurality of radio frequency signals to produce a respective plurality of digital radio frequency signals having a respective associated radio frequency digital clock, the plurality of digital radio frequency signals having a sufficiently high respective associated clock rate to preserve an information content of an information communication present in the analog radio frequency representation; a switch matrix adapted to concurrently switch the plurality of digital radio frequency signals and associated digital radio frequency clock to ones of a plurality of digital signal processors; and a control adapted to selectively automatically control the concurrent switching of a plurality of digital signals and associated digital clock to the respective plurality of digital signal processors; wherein the digital signal processors
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: May 23, 2017
    Assignee: Hypres, Inc.
    Inventor: Deepnarayan Gupta
  • Patent number: 9558251
    Abstract: One or more transformation functions can be used in connection or together with one or more compression/decompression techniques. A transformation function can transform data (e.g., a data object) into a form more suitable for compression and/or decompression. As a result, data can be compressed and/or decompressed more effectively. In addition, multiple data objects can be associated with various transformation functions and/or compression/decompression techniques. As a result, different approaches can be taken with respect to compression and decompression of data objects in an effort to find an optimum approach for compression of data objects that may vary significantly from each other and change over time. It will be appreciated that the objects can be associated with transformation functions in a dynamic manner to accommodate changes to data. Also, an extendible and/or extensible system can allow for growth and adaption of new data in forms not currently present or expected.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 31, 2017
    Assignee: Teradata US, Inc.
    Inventors: David Simmen, Shant Hovsepian, Jeffrey Davis
  • Patent number: 9531280
    Abstract: An isolation device having first and second semiconductor is disclosed. The first semiconductor die may be adapted to transmit a first signal to the second semiconductor die that is electrically isolated. The first semiconductor die may have a transmitter coupled to a modulator that modulates the first signal. The second semiconductor die may have a receiver having a counter and a control circuit. The control circuit may be adapted to determine an indication of the first signal by using the counter. In addition, an isolation system and a DC-DC feedback regulation control system having such control circuit are disclosed. Likewise, a method for conveying a first signal across an isolation barrier is disclosed. The method may comprise counting a received signal based on internal clock and determining an indication of the first signal from the counter's count value.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: December 27, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jia Peng, Fun Kok Chow, Chee Heng Wong, Kwee Chong Chang
  • Patent number: 9521434
    Abstract: In an example aspects of this disclosure generally relate to a method of coding video data that includes determining a first bit depth for outputting video data and a second bit depth for coding the video data, wherein the first bit depth is less than the second bit depth. The method also includes determining whether the video data will be used as reference data when coding other video data. The method also includes storing, based on the determination, the video data at the first bit depth when the video data is not used as reference data, and the video data at the second bit depth when the video data is used as reference data.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Chen, Peisong Chen, Marta Karczewicz
  • Patent number: 9438362
    Abstract: An audio mixing device includes: an adder that adds a plurality of PDM signals each converted from a plurality of digital audio signals; a D/A converter that performs D/A conversion on a digital audio signal outputted from the adder and outputs an analog audio signal; and a synchronization device that is provided prior to the adder, and that synchronizes each of a plurality of digital signals with one another by use of the same predetermined synchronization timing signal and outputs each of them to the adder.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: September 6, 2016
    Assignee: RICOH COMPANY, LTD.
    Inventor: Yukihiro Imai
  • Patent number: 9432032
    Abstract: A method comprises determining a reference ratio based on a first division ratio of a first phase-locked loop (PLL) and a second division ratio of a second PLL, and converting a first discrete sequence to a second discrete sequence based on a sequence of multiples of the reference ratio. The first and second PLLs operate under a locked condition and share a common reference oscillator. An apparatus includes comprises a clock generator including first and second phase-locked loops (PLLs) and configured to generate first and second clock signals, respectively, and a sample-rate converter configured to convert a first discrete sequence to a second discrete sequence based on a sequence of multiples of a reference ratio. The reference ratio is determined based on a first division ratio of the first PPL and a second division ratio of the second PLL.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 30, 2016
    Assignee: MARVELL WORLD TRADE LTD.
    Inventor: Renaldi Winoto
  • Patent number: 9432043
    Abstract: It is known to perform sample rate conversion. A sample rate converter is arranged to receive digital data at an input sample rate Fs and to output data at an output sample rate Fo, where Fo=Fs/N, and N is decimation factor greater than 1. A problem can arise with sample rate converters when a user wishes to change the decimation rate. Generally a sample rate converter needs to discard the samples in its filter when the decimation rate is changed, and the filter output is unusable until the filter has refilled with values taken at the new decimation rate. The sample rate converter provided here does not suffer from this problem. The sample rate converter includes at least Q channels.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: August 30, 2016
    Assignee: Analog Devices Global
    Inventors: Anthony Evan O'Shaughnessy, Colin Lyden, Joseph Peter Canning
  • Patent number: 9398284
    Abstract: In one example, a video coder, such as a video encoder or a video decoder, is configured to code a value for a layer identifier in a slice header for a current slice in a current layer of multi-layer video data, and, when the value for the layer identifier is not equal to zero, code a first set of syntax elements in accordance with a base video coding standard, and code a second set of one or more syntax elements in accordance with an extension to the base video coding standard. The second set of syntax elements may include a syntax element representative of a position for an identifier of an inter-layer reference picture of a reference layer in a reference picture list, and the video coder may construct the reference picture list such that the identifier of the inter-layer reference picture is located in the determined position.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: July 19, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Chen, Li Zhang, Adarsh Krishnan Ramasubramonian
  • Patent number: 9372794
    Abstract: The technique introduced here involves using a block address and a corresponding generation number as a “fingerprint” to uniquely identify a sequence of data within a given storage domain. Each block address has an associated generation number which indicates the number of times that data at that block address has been modified. This technique can be employed, for example, to maintain cache coherency among multiple storage nodes. It can also be employed to avoid sending the data to a network node over a network if it already has the data.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: June 21, 2016
    Assignee: NetApp, Inc.
    Inventor: Michael N. Condict
  • Patent number: 9306818
    Abstract: The disclosure provides a probe and a method for calculating statistic data of traffic flows. The probe comprises at least one link processor (LP) and a correlation processor (CP). Each LP includes two buffers, receives packets from directional traffic flows, generates information of bi-directional traffic flows based on the received packets, stores the generated information in one buffer within a reporting period and, reports the stored information to CP when the reporting period boundary is reached. The information of each bi-directional traffic flow includes the relevant identification information and statistic data. The CP calculates statistic data of a particular group of traffic flows with a predetermined characteristic based on the reported information, and the other buffer stores information of bi-directional traffic flows to be generated within a next reporting period and the stored information is to be reported to the correlation processor when the next reporting period boundary is reached.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: April 5, 2016
    Assignee: CellOS Software LTD
    Inventors: Greg Aumann, David Lynes, Amit Goel
  • Patent number: 9264065
    Abstract: Generally described herein are methods and systems for sample rate conversion of non-integer and integer factors. In one or more embodiments an apparatus can include a sample rate converter that can include an input configured to receive an input signal with a first frequency and an output configured to provide an output signal with a second frequency different from the first frequency. The sample rate converter can include a filter coefficient lookup table and a numerically controlled oscillator configured to provide filter coefficients from the filter coefficient lookup table at a rate that is a function of the first frequency and the second frequency.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Raytheon Company
    Inventor: Gregary B. Prince
  • Patent number: 9258011
    Abstract: Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: February 9, 2016
    Assignee: Visteon Global Technologies, Inc.
    Inventors: J. William Whikehart, David P. Stewart, Dave Lavacek
  • Patent number: 9229506
    Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip. The IC chip includes a power demand determination unit upstream of a command execution circuit. The power demand determination unit is configured to determine, before command execution, an expected power demand of the IC chip for executing a command that is input to the command execution circuit.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: January 5, 2016
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Uri Holzman
  • Patent number: 9231562
    Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: January 5, 2016
    Assignee: SIGMATEL, INC.
    Inventor: Darrell Eugene Tinker
  • Patent number: 9209783
    Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: December 8, 2015
    Assignee: DSP GROUP LTD.
    Inventors: Yosef Bendel, Eyal Rosin, Assaf Ganor
  • Patent number: 9170986
    Abstract: A method for waveform analysis and compression includes determining harmonic components of a waveform, subtracting the harmonic components from the waveform, leaving a residual waveform, and compressing the residual waveform. Information about the harmonic components and the compressed residual transform can be transmitted across a network for analysis or reconstruction of the waveform in another device. The method is used in a low cost power quality meter, which can form part of a smart metering scheme.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: October 27, 2015
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Chung-Fai Tse, Wing-Hong Lau
  • Patent number: 9172391
    Abstract: A method and a system for compensating a delay mismatch between a first measurement channel and a second measurement channel is disclosed. A method for compensating a delay mismatch between a first measurement channel and a second measurement channel includes providing a reference point for starting the first and second measurement channel, and starting the first measurement channel after expiration of a first delay period which begins at the reference point. The method further includes starting the second measurement channel after expiry of a second delay period which begins at the reference point, wherein a difference between a length of the first delay period and a length of the second delay period is substantially equal to the delay mismatch between the first measurement channel and the second measurement channel.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies AG
    Inventor: Jens Barrenscheen
  • Patent number: 9144067
    Abstract: Communication systems in which a fixed size information block is transmitted to one or multiple receivers, such as the long term evolution (LTE) of the 3rd Generation Partnership Projection (3GPP), may benefit from a structure, in which a downlink control information (DCI) format, or more generally the fixed sized information block, can be extended by a small number of bits and still be backwards compatible with older terminals, which do not need the extra bits or may not even be aware of this extension. A method for providing this extension can include preparing a first codeword for transmission. The method can also include preparing a second codeword for transmission. The second codeword can have a code rate that is configured to be less than the code rate of the first codeword. The method can further include initiating simultaneous transmission of the first codeword and the second codeword.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: NOKIA TECHNOLOGIES OY
    Inventors: Lars E. Lindh, Klaus Hugl
  • Patent number: 9143139
    Abstract: A microelectronic system comprises at least one circuit block that performs certain signal processing functions and at least one clock generation circuit that produces at least one Time-Average-Frequency clock signal which comprises clock pulses of at least two different lengths. The said lengths are measured in time. The arithmetic mean of the lengths of all the pulses that exist in a time frame of one second is calculated. The Time-Average-Frequency clock pulse train is made in such way that the arithmetic inversion of the said arithmetic mean equals to a predetermined value that is the clock frequency of the Time-Average-Frequency clock signal. At least one said circuit block in the said microelectronic system is driven by the said Time-Average-Frequency clock signal. The said circuit block is setup-constrained using the minimum pulse length found among the lengths of all the pulses in the Time-Average-Frequency clock signal.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: September 22, 2015
    Inventor: Liming Xiu
  • Patent number: 9112763
    Abstract: The present disclosure discloses a device, system and method for bi-phase modulation decoding. The bi-phase modulation decoding device includes a sliding-window module and a determination module. The sliding-window module is configured to receive a baseband signal corresponding to a bi-phase modulated signal, and generate a filtered data packet by filtering the baseband signal using sliding-window digital filtering, wherein the filtered data packet comprises a series of sliding-window output values. The determination module configured to determine a bitstream corresponding to the bi-phase modulated signal based on the filtered data packet. The determination module determines a bit value of a first bit cycle of the bi-phase modulated signal based on a sign of a sliding-window output value of the first bit cycle and a sign of a sliding-window output value of a next bit cycle.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 18, 2015
    Assignee: O2MICRO INC.
    Inventors: Xiaogang Tan, Ke Gao, Fan Dou, Xinsheng Peng, James Wang
  • Patent number: 9100030
    Abstract: An arbitrary waveform generator (AWG) comprises a real-time digital signal processor (DSP) configured to process a stream of waveform data based on current values of processing parameters, a DSP memory configured to store information related to the processing parameters, and an update component configured to update in real-time the current values of the processing parameters based on the information stored in the DSP memory.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 4, 2015
    Assignee: Keysight Technologies, Inc.
    Inventor: Hansjoerg Haisch
  • Patent number: 9100036
    Abstract: There is provided a receiving device includes: a plurality of interpolation unit circuits, each interpolation unit circuit configured to perform interpolation processing of a sampling value obtained by asynchronously sampling input data, based on an interpolation ratio, so that sampling data synchronous with the input data and continuous in time is generated, wherein one of the interpolation unit circuits is provided in parallel with another of the interpolation unit circuits for a channel previous to a channel in which switching of the interpolation ratio is performed.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: August 4, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Sanroku Tsukamoto
  • Patent number: 9075108
    Abstract: A method for marking a signal edge, which has been removed from at least one decimated binary signal after the decimation of an associated binary signal, within the decimated binary signal, establishes successive signal portions of the respective binary signal, in each case with a number of sampled values corresponding to a decimation factor of the decimation. It detects a signal edge removed through decimation from each signal portion if the number of signal edges determined in each signal portion of the respective binary signal is greater than one. Then, the sampled values of the respective decimated binary signal are determined through decimation of the sampled values of the associated binary signal with the decimation factor, and the removed signal edge at the sampling time of the decimated binary signal which corresponds to the signal portion of the associated binary signal with the signal edge removed through decimation is marked.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: July 7, 2015
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventors: Wolfgang Herbordt, Thomas Kuhwald, Bernhard Nitsch, Friedrich Reich
  • Patent number: 9063968
    Abstract: A method begins by processing module in response to a read command, issuing at least a read threshold number of read requests regarding a set of encoded data slices and receiving at least the read threshold number of encoded data slices. The method continues where the processing module selects a unique combination of encoded data slices and decodes the unique combination to produce a recovered data segment. The method continues where the processing module verifies an integrity value for the recovered data segment and indicates whether the unique combination is valid. The method continues where the processing module selects other combinations producing more recovered data segments for further validity verification. The method continues where the processing module utilizes a verified recovered data segment as a response to the read command and identifies a compromised encoded data slice.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: June 23, 2015
    Assignee: Cleversafe, Inc.
    Inventor: Jason K. Resch
  • Patent number: 9035808
    Abstract: A communication system including a configurable sample rate converter and a controller is provided. The configurable sample rate converter, configured to convert a digital signal with a first sample rate to a converted signal with a second sample rate, being operable in one of a first configuration and a second configuration. The controller, configured to dynamically control the sample rate converter to operate in one of the first configuration and the second configuration according to at least one condition.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 19, 2015
    Assignee: MStar Semiconductor, Inc.
    Inventors: Ming-Yu Hsieh, Shih-Chieh Yen, Khurram Muhammad
  • Patent number: 9030337
    Abstract: A method of filtering an input sample stream having a downsampling rate is disclosed to generate an output sample stream having an upsampling rate that is less than the downsampling rate. The input sample stream is input to a rate change filter having multiple filter branches. The input sample stream is filtered at each of the multiple filter branches to output filtered sample substreams. Each of the multiple filter branches have filter coefficients corresponding to a different phase of the filter response. The filtered sample substreams are stored in a memory and the stored filtered sample substreams are combined to generate the output sample stream.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: May 12, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Joleen Hind, Pierre-André Laporte
  • Patent number: 9026692
    Abstract: A Data Throttling method duplicates the full-speed transmission of data so that it appears to be transmitting at a 10 Mhz rate. Additional storage elements and multiplexers are added along the data path but this completely eliminates undesirable complexity in the clock tree. In a two-bit application, data is received and transmitted two bits at a time, and yet the output 10 Mhz data rate is maintained. For an even ratio between the system clock rate and the 10 Mhz clock signal rate, bit0 is transmitted for half the time and bit1 is transmitted for the other half of the time. But if the full-speed clock rate is an odd multiple of 10 Mhz, then there will be a “split cycle” including one bit0 and one bit1.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: May 5, 2015
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: J. Steve Griffith, John Pfeil, Sam Stratton
  • Patent number: 9014307
    Abstract: A multichannel radio receiver may include a radio frequency (RF) subsystem and a digital subsystem. The RF subsystem may be configured to provide analog information associated with a radio band to an analog to digital converter (ADC). The ADC samples the analog input and sends digital output to the digital subsystem. The digital subsystem may be configured with one or more channelizers and one or more decoders. A channelizer within the digital subsystem may filter and re-sample the digital output to result in a channel plan having a desired bandwidth and a desired sample rate. The sample rate may be selected for compatibility with a decoder. The decoder may have design specifications based in part on a modulation scheme to be decoded. The design specifications may indicate the desired sample rate to be provided by the channelizer.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 21, 2015
    Assignee: Itron, Inc.
    Inventor: Danny Ray Seely
  • Publication number: 20150097708
    Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.
    Type: Application
    Filed: March 12, 2014
    Publication date: April 9, 2015
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Mi Jeong PARK, Ik Soo EO, Sang-Kyun KIM
  • Patent number: 9001939
    Abstract: Provided is a transmitter for transmitting signals by means of the STBC method or the DSTBC method, wherein communication is carried out effectively. The transmitter for transmitting signals by means of the STBC method or the DSTBC method has the following configuration. A frame in which synchronization words are arranged at specified positions is used. An encoding means in the transmitter encodes the entire frame to be transmitted including the synchronization words, by means of the STBC method or the DSTBC method. It is also possible to implement a communication system and a communication method for communicating signals by means of the STBC method or the DSTBC method.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 7, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hiroyuki Akutagawa, Takehiko Kobayashi
  • Patent number: 9000958
    Abstract: A data rate conversion device generates a first parameter representing a memory address position to sample and a second parameter representing a phase value of an estimation time point, records input data at a memory based on an input clock, outputs sampled continued data from the memory using the first parameter based on an output clock, and generates and outputs final data using the continued data, a plurality of filter coefficients, and the second parameter.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 7, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi Jeong Park, Ik Soo Eo, Sang-Kyun Kim
  • Publication number: 20150091743
    Abstract: Methods and systems consistent with the present invention provide an improved sample-rate converter that overcomes the limitations of conventional sample-rate converters. The improved system comprises a simple asynchronous sample-rate converter and synchronous sample-rate converter. The output of the simple asynchronous sample-rate converter is connected to the input of the synchronous sample-rate converter. In an alternative embodiment, the output of the synchronous sample-rate converter is connected to the input of the simple asynchronous sample-rate converter.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: VISTEON GLOBAL TECHNOLOGIES, INC.
    Inventors: J. Willliam Whikehart, David P. Stewart, Dave Lavacek
  • Patent number: 8965942
    Abstract: Systems and methods for sample rate tracking are provided. An example method includes computing an actual latency associated with an output sample from an output sample stream. The actual latency is calculated using a phase and a phase increment (conversion rate ratio). A measured latency is determined using an internal clock using a presentation time of the output sample, or an input sample from an input sample stream, or both. The measured latency is compared to the actual latency to generate a latency error. A successive phase increment can be determined based on the latency error by using a low-pass or adaptive filter to adjust the latency error.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 24, 2015
    Assignee: Audience, Inc.
    Inventors: David P. Rossum, Sneha Date, Xiaojun Chen