Abstract: Provided are systems and methods for dynamic detection of changes in signal bandwidth associated with audio samples received by a communication device during handovers, where the communication device is moved through geographical areas served by different wireless network technologies. Based on the detection, operation parameters of an audio processor of the communication device may be adjusted or switched to achieve optimal performance of audio enhancing procedures (e.g., noise suppression) performed by the audio processor and to preserve minimal power consumption.

Abstract: There is disclosed a stream data reception/reproduction device capable of suppressing deterioration of quality of stream data reproduced even when the stream data is received via an IP network or the like in which the packet arrival timing and the order are not guaranteed. In this device, a reproduction speed control unit (107) sets various conditions in accordance with the value of the synchronization difference reported from a synchronization difference calculation unit (102). Only when the set conditions are satisfied, the speed of reproduction of a frame decompressed and inputted from a decoding unit (105) is adjusted. The reproduction speed control unit (107) interpolates a predetermined amount of sample data into the frame or decimates it from the frame when adjusting the reproduction speed.

Abstract: A method and system for monitoring and analyzing at least one signal are disclosed. An abstract of at least one reference signal is generated and stored in a reference database. An abstract of a query signal to be analyzed is then generated so that the abstract of the query signal can be compared to the abstracts stored in the reference database for a match. The method and system may optionally be used to record information about the query signals, the number of matches recorded, and other useful information about the query signals. Moreover, the method by which abstracts are generated can be programmable based upon selectable criteria. The system can also be programmed with error control software so as to avoid the re-occurrence of a query signal that matches more than one signal stored in the reference database.

Abstract: A fractional rate converting filter in a wireless transceiver comprising a delay line, multiplier circuit, adder circuit, and selector. The delay line receives a digital input signal at a first sample rate and has delay blocks each providing an output and receiving samples gated at a plurality of clock cycles of an integer sub-multiple frequency of a clock. The outputs are multiplied by corresponding filter tap coefficients. Each filter tap coefficient is spaced by a first integer Y. The adder circuit receives and sums the tap outputs to provide an output signal. The selector iteratively shifts the coefficients by a second integer Z. The output of each delay block is multiplied by corresponding shifted filter tap coefficients. The delay blocks are inhibited from receiving another input sample during the plurality of clock cycles. The output signal has a second sample rate at the integer sub-multiple frequency of the clock.

Abstract: One embodiment relates to an apparatus for sample rate conversion. A sample rate converter is arranged to receive an input signal at an input sampling frequency and use an interpolation interval to convert the input signal to an output signal at an output sampling frequency. A rate controller is arranged to alternate between different frequency control words for use in generating the interpolation interval signal. Another embodiment relates to a method of sample rate conversion. Another embodiment relates to a rate controller circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.

Abstract: A system and method for performing sample rate conversion and creating fractional delays to a signal is disclosed. The system comprises a filter, a look up table for storing coefficients for sample rate conversion and fractional delays, and control circuitry configured to use an indexing scheme to select one or more coefficients from the look up table for rate conversion and fractional delays. The coefficients stored in the look up table comprise the coefficients required to generate delays in desired increments of a sample rate. In the disclosed method, the one or more coefficients necessary for a desired sample rate and fractional delay are selected from a single look up table and provided to a filter to delay the signal based upon the input sample rate.

Abstract: Disclosed are methods and apparatus for sampling rate conversion in a wireless transceiver. The methods and apparatus achieve agile setting of sampling rates or resampling by adaptively setting a sampling rate of a signal based on at least one performance requirement of the transceiver. In particular, the methods and apparatus perform sampling of an input signal at a first sampling rate to gain one or more input signal samples. The input signal samples are then filtered using parallel or polyphase filtering operating at a second sampling rate lower than the first sampling rate. The filtered samples are then interpolated at the second sampling rate to achieve resampling of the input signal. Polyphase filtering affords an effectively high input sampling rate for good spectrum image rejection, while allowing the second sampling rate to be effectively much lower than the first rate, thereby reducing the complexity of multiplier operations for interpolation.

Abstract: Digital methods and systems for signal processing and filtering are provided. The methods and corresponding systems provide asynchronous conversion of sampling rate frequencies and utilize advanced multistage phasor filters for converting an input signal having a first sampling rate into an output signal sampled in an arbitrary sequence of sampling times. The conversion process provides a sequence of sets of complex numbers representing a filtered version of the input signal. More specifically, the conversion process includes the calculation of values of the output signal by multiplying (e.g., scaling) the sets of complex numbers by a corresponding set of complex phasors, the complex phasors corresponding to the timing of the arbitrary time sequence to obtain a corresponding set of real results with the value of the output signal being the sum of the real results.

Abstract: As a digitized representation of an intermediate frequency television signal moves through a demodulator it undergoes a number of processes, including conversion from an analog signal to a digitized data, digital signal processing of the digitized data, and the like. The rate at which the digitized data moves through the digital signal processor of the demodulator for processing is referred to as the data rate of the DSP. The demodulator can vary the data rate based on a selected television channel, thereby reducing the level of interference at the demodulator resulting from noise.

Abstract: Unpacking a variable number of data bits is provided. A structure includes an input port operable to receive one or more input data units including a plurality of packed bits of data, each of the one or more input data units including a header and a payload, the header including a predetermined number of bits and identifying a format of the payload and a length of the payload, and the payload including a variable number of bits. The structure further includes a circuit operable to identify and unpack the one or more input data units based on the header and the payload of each of the one or more input data units. The structure further includes an output port operable to transmit one or more output data units including the unpacked one or more input data units, once per clock cycle.

Abstract: A digital signal processing circuit, such as a digital-to-analog converter (DAC) having multiple cascaded processing stages, some of which are selectably placed in a low-power non-operating state according to a lower-power operating mode of the digital signal processing circuit and are placed in an operating state according to another higher-performance operating mode of the circuit. The output sample rates of the stages differ, so that the sample rate through the cascade changes. A signal characteristic determination block generates an indication of one or both of an amplitude and/or frequency of the input signal, so that the operating mode of the digital signal processing circuit is selected in conformity with the indication of amplitude and/or frequency of the input signal.

Abstract: A system and method transmits graphic data received at varying frequencies at a fixed data rate. The frequency dependent data and associated data clock signal are received and the frequency dependent data is converted to frequency independent data. A ratio of a number of data clock cycles to a number of reference clock cycles is determined and transmitted. The frequency independent data and header data are transmitted, at a fixed rate, to a receiver, the fixed rate being a frequency greater than the frequency of the associated data clock signal. The received the frequency independent data is converted to frequency dependent data based upon the received determined ratio. The communication channel may include an optical fiber and a tension member wherein control data is transmitted along the tension member and graphic data is transmitted along the optical fiber.

Abstract: A method of operating an electronic video device such as a DVD player, wherein video clock signals and audio clock signals are derived from a system clock signal using two phase-lock loops, and these video and audio clock signals are used to process encoded video data and encoded audio data, but digital-to-analog conversion of the audio data stream is controlled by the system clock signal rather than the audio clock signals. By using the system clock signal to control the audio digital-to-analog converter (DAC), the DAC avoids the poor performance issues that can arise from jitter introduced into the audio clock signals by the PLL. The system clock signal may be divided by an integer to generate the sampling clock for the audio DAC. In the illustrative embodiment, the system clock signal has a rate which is not an integer multiple of the sample rate of the audio data stream.

Abstract: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Abstract: There are provided a digital signal converter and a method of converting a digital signal. The digital signal converter includes: a signal reception unit analyzing a digital input signal received according to a first form; a signal output unit transmitting a digital output signal according to a second form, different from the first form; and a controller converting the digital input signal received according to the first form into a digital output signal to be transmitted according to the second form, wherein the controller controls a power level of the digital output signal according to power supply methods of the first and second forms. Signal transmission and reception methods according to various interfaces may be provided in a limited form factor by adjusting the standard and coding of a digital signal transmitted and received through different interfaces and as to whether to supply power.

Abstract: A circuit includes an enhanced frequency range linear pulse code modulation conversion circuit. The enhanced frequency range linear pulse code modulation conversion circuit is driven by a clock signal within a frequency range. The enhanced frequency range linear pulse code modulation conversion circuit provides enhanced frequency range linear pulse code modulated information. More specifically, the enhanced frequency range linear pulse code modulation conversion circuit is provided by selectively decimating and interpolating non-enhanced frequency range linear pulse code modulated information based on a desired output sampling frequency and the frequency range.

Abstract: Method and apparatus for generating a target frequency having an over-sampled data rate using a system clock having a different frequency are disclosed. In one aspect of the present disclosure, the circuit includes, a digital phase locked loop coupled to the system clock. The digital phase locked loop including an oscillator output and an oscillator input. The circuit further comprises an extra pulse eliminator coupled to the oscillator output. The extra pulse eliminator includes an extra pulse eliminator output. One or more frequency dividers may be coupled to an extra pulse eliminator output.

Abstract: Disclosed herein is a digital filter circuit for producing a noise reduction signal for reducing noise based on a noise signal outputted from a microphone which collects the noise, including: an analog/digital conversion section; a first digital filter section; an arithmetic operation processing section; a second digital filter section; and a digital/analog conversion section. The first digital filter section and/or the second digital filter section are configured such that a predetermined attenuation amount is obtained within a predetermined range in the proximity of a sampling frequency around the sampling frequency.

Abstract: A method and system for fractionally converting sample rates. Fractional rate conversion for a transmit path of a transceiver is achieved by upsampling an input signal having a first sample rate by a first integer factor, removing aliasing resulting from the upconversion process, and then downsampling the intermediate signal by a second integer factor to provide a final signal having a second sample rate. The first factor and the second factor are selected to obtain a desired output sample rate that is a fraction of the sample rate of the input signal.

Abstract: The present invention provides a digital data acquisition module, such as a digital oscilloscope, that includes a synchronous random access memory (RAM), a digital signal processing unit, and a master control unit. The digital signal processing unit is coupled to the synchronous RAM and includes at least one analog-to-digital (A/D) converter that digitizes an analog signal, and a digital signal processor that includes a dual-port RAM, a plurality of processing blocks and a communications interface. The plurality of processing blocks process the digitized analog signal data, store the processed signal data in the synchronous RAM, create display data from the stored signal data, store the display data in the dual-port RAM.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: Systems and methods for asynchronous sample rate conversion are provided that allow time-varying arbitrary sample ratios. An uncorrected ratio between two arbitrary sample rates is corrected and subsequently used to perform an efficient sample rate conversion on the samples in a data stream. Coefficients of a (polyphase) finite impulse response filter are interpolated based on a current time register value. Additional computational efficiency (and a smaller finite impulse response filter) may be used due to oversampling the input signal to the finite impulse response filter.

Abstract: A method of operating an electronic video device such as a DVD player, wherein video clock signals and audio clock signals are derived from a system clock signal using two phase-lock loops, and these video and audio clock signals are used to process encoded video data and encoded audio data, but digital-to-analog conversion of the audio data stream is controlled by the system clock signal rather than the audio clock signals. By using the system clock signal to control the audio digital-to-analog converter (DAC), the DAC avoids the poor performance issues that can arise from jitter introduced into the audio clock signals by the PLL. The system clock signal may be divided by an integer to generate the sampling clock for the audio DAC. In the illustrative embodiment, the system clock signal has a rate which is not an integer multiple of the sample rate of the audio data stream.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: Some embodiments relate to a method for use in a sigma-delta analog to digital converter, sigma-delta analog to digital converters and systems comprising sigma-delta analog to digital converters. In accordance with an aspect of the invention, there is provided a method for use in a sigma-delta analog to digital converter (SD-ADC) comprising a modulator, a decimation filter, a decimation counter, and a decimator data output, wherein the method comprises receiving an external trigger signal and capturing a value of the decimation counter and a value of the decimator data output upon receiving the external trigger signal.

Abstract: A sampling rate converter that converts an incoming stream of data, clocked at a first frequency, to an output stream of data that can be clocked at a second frequency is described. The sampling rate converter up-samples an incoming data stream, filters the up-sampled incoming data stream, interpolates the filtered up-sampled data stream, and then stores the interpolated filtered up-sampled incoming data stream in a FIFO at the first frequency. The interpolated filtered up-sampled data can then be read from the FIFO at the second frequency. A control block that includes a numerically controlled oscillator (NCO) that generated the first frequency is provided. Control of the NCO's production of the first frequency is based on the status of the FIFO, how the data stream is modulated, and the sampling rate ratio of the incoming data stream with respect to the output or read rate of data stream.

Abstract: Disclosed herein is a coding method including the step of: coding an information sequence in such a manner that upon performing error correction coding after carrying out RLL coding of the information sequence, the maximum number of consecutive 1-bits or 0-bits is ??? or less in an RLL code word over a range from bit p?? to bit p+??1 of the RLL code word and that a ?-bit error correcting code parity sequence is inserted between bit p?1 and bit p of the RLL code word, where ? is a number larger than 1 representing the maximum number of consecutive 0-bits or 1-bits in an n-bit RLL code word and where p is a natural number.

Abstract: Video processing systems and methods for preservation of small details in video undergoing quantization is discussed. Small details are preserved by identifying an area of interest within a video frame, determining whether small details are present within the selected portion of the video frame, and further determining whether those small details may be lost during quantization. In the event that small details are present in the selected portion of the video frame and may be lost during quantization, a color-shifting operation may be performed on one or more color components of the selected portion of the video frame, such as luminance, prior to quantization to preserve the small detail. During the color-shifting operation, the values of at least one color component of pixels representing the video frame are shifted such that the pixels extend between at least two quantization levels when quantized.

Abstract: A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Abstract: A system, method and computer program product provide finer rate control in data compression by processing a data stream through a plurality of parallel subbands, wherein a first subband processes the data differently than a second subband. Separate shift quantization parameters for each separate run-of-zeros compressed storage area or pile can be provided, instead of a single common shift parameter for every coefficient as in the prior art. The parameter value for each such area or pile can be recorded in the compressed output file. The separate shift quantization parameters can also be adjusted dynamically as data is being compressed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for encoding and decoding information. In one aspect, methods of encoding information in an encoder include the actions of receiving a signal representing information using a collection of discrete digits, converting, by an encoder, the received signal into a time-based code, and outputting the time-based code. The time-based code is divided into time intervals. Each of the time intervals of the time-based code corresponds to a digit in the received signal. Each digit of a first state of the received signal is expressed as a event occurring at a first time within the corresponding time interval of the time-based code. Each digit of a second state of the received signal is expressed as a event occurring at a second time within the corresponding time intervals of the time-based code, the first time is distinguishable from the second time.

Abstract: Poly-phase filters are used to offer an efficient and low complexity solution to rate conversion. However, they suffer from inflexibility and are not easily reconfigured. A novel design for rate converters employ poly-phase filters but utilize interpolation between filter coefficients to add flexibility to rate conversion. This interpolation can be implemented as an interpolation of the poly-phase filter results. Additional approximations can be made to further reduce the amount of calculations required to implement a flexible rate converter.

Abstract: A system and method for performing sample rate conversion and creating fractional delays to a signal is disclosed. The system comprises a filter, a look up table for storing coefficients for sample rate conversion and fractional delays, and control circuitry configured to use an indexing scheme to select one or more coefficients from the look up table for rate conversion and fractional delays. The coefficients stored in the look up table comprise the coefficients required to generate delays in desired increments of a sample rate. In the disclosed method, the one or more coefficients necessary for a desired sample rate and fractional delay are selected from a single look up table and provided to a filter to delay the signal based upon the input sample rate.

Abstract: Techniques of this disclosure provide for adjustment of a conversion rate of a sampling rate converter (SRC) in real-time. The SRC determines relative timing of generated output samples based on non-approximated integer components that are recursively updated. The SRC may further base relative timing of output samples on a value of one or more step size components associated with the integer components. Also according to techniques of this disclosure, a conversion rate of an SRC may be adjusted in real-time based on a detected mismatch between a source clock of a digital input signal and a local clock.

Abstract: A method and system for monitoring and analyzing at least one signal are disclosed. An abstract of at least one reference signal is generated and stored in a reference database. An abstract of a query signal to be analyzed is then generated so that the abstract of the query signal can be compared to the abstracts stored in the reference database for a match. The method and system may optionally be used to record information about the query signals, the number of matches recorded, and other useful information about the query signals. Moreover, the method by which abstracts are generated can be programmable based upon selectable criteria. The system can also be programmed with error control software so as to avoid the re-occurrence of a query signal that matches more than one signal stored in the reference database.

Abstract: A direct digital radio having a high speed RF front end in communication with an antenna, and a radio subsystem that can be configured to form a multi-channel, full duplex transceiver system. The high speed RF front end provides a digital signal to the radio subsystem. Each transceiver includes a waveform processing subsystem that makes use of a linear, phase-B cubic spline interpolating finite impulse response (IFIR) filter for filtering the received RF signal substantially entirely in the digital domain. The linear phase-B, cubic spline IFIR filter requires significantly fewer hardware components than traditional FIR filters and is ideally suited for implementation using Very Large Scale Integration (VLSI) technology.

Abstract: Various methods and systems permit digital data, such as video data, audio/video data, audio/video/subpicture data and the like, to be processed in a manner that permits playback at different speeds in both forward and reverse directions. Various embodiments are also directed to handling playback rate changes in a manner that can enhance the user's experience.

Abstract: A digital recording apparatus for recording 1-bit digital audio data of a first sampling frequency on a recording medium in accordance with the recording format of multi-bit PCM data of a second sampling frequency includes a storage section to which input 1-bit digital audio data of the first sampling frequency is written; an encoder configured to read, from the storage section, the 1-bit digital audio data at a clock synchronized with the second sampling frequency and configured to convert the 1-bit digital audio data in such a manner that bits of the 1-bit digital audio data are arrayed in a 1-bit data area provided in the multi-bit PCM data that is in accord with the recording format; and a recorder configured to record data output from the encoder on the recording medium in accordance with the recording format.

Abstract: A projection system comprising an information processing apparatus capable of processing image data and a projector capable of performing a display process on the image data processed by the information processing apparatus, when the bit number representing the number of gradations of pixel data transmitted from the information processing apparatus to the projector is n-bit and the bit number representing the number of gradations which can be expressed by the projector is m-bit (m>n). The image processing apparatus outputs image data where m-bit pixel data is divided into k-pieces of pixel data of at most n-bits, and the projector synthesizes the k-pieces of pixel data based on a set synthesis rule to generate the m-bit pixel data in the pixel.

Abstract: An automatic power control system, an automatic power control method, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.

Abstract: A digital audio processing system includes an input to receive a phase component of a signal. The digital audio processing system includes symbol recognition logic to adjust a sample of the phase component using an offset value. The symbol recognition logic maps the adjusted sample to a nearest predetermined phase value of a plurality of predetermined phase values. The symbol recognition logic determines a symbol using a difference between the nearest predetermined phase value and a prior nearest predetermined phase value. The prior nearest predetermined phase value corresponds to a prior sample of the phase component of the signal. The offset value is based on a detected error of the prior sample of the phase component of the signal. The digital audio processing system also includes an output to provide a second signal that indicates the symbol.

Abstract: A system including a pulse generating module and a processing module is disclosed. The pulse generating module generates a target signal. The processing module outputs a processing signal according to the target signal. Throughput of the target signal exceeds throughput of the processing signal.

Abstract: Disclosed herein is a signal processing apparatus including: a first decimation processing section for generating, based on a digital signal in a first form, a digital signal in a second form; a second decimation processing section for generating, based on the digital signal in the second form, a digital signal in a third form; a first signal processing section for processing the digital signal in the third form; an interpolation processing section for converting a digital signal in the third form outputted from the first signal processing section into a digital signal in the second form; a second signal processing section for processing the digital signal in the second form outputted from the first decimation processing section; and a combining section for combining the digital signals in the second form outputted from the interpolation processing section and the second signal processing section.

Abstract: A method and apparatus are disclosed for performing sampling rate conversion of an audio signal from a first sampling rate to any of a plurality of higher sampling rates using a single set of low-pass filter coefficients. Sampling rate conversion is accomplished by effectively up-sampling, low-pass filtering, and down-sampling the audio signal to generate interpolated output samples of a second digital audio signal at any of a plurality of sampling rates. The sampling rate conversion process includes storing a fixed set of filter coefficients as a plurality of phased subsets of filter coefficients, applying samples of the audio signal to the phased subsets in a rotational manner to generate filtered samples of the audio signal, and selecting and linear interpolating between certain filtered samples to generate samples of the second digital audio signal.

Abstract: According to the present invention, in a liquid crystal display device which intermittently drives (burst driving) a light source device having a discharge tube which is arranged to face a main surface of a liquid crystal display panel in an opposed manner and is turned on in response to an alternating electric field, the resistance between first and second active elements which constitute a resonance circuit at a primary side of a driving circuit of the light source device and the reference potential in the driving circuit is set higher when burst driving of the discharge tube assumes the turn-OFF state than when the burst driving of the discharge tube assumes the turn-ON state.

Abstract: Some of the embodiments of the present disclosure provide a method of transferring data from a fast clock domain associated with a fast clock signal to a slow clock domain associated with a slow clock signal, the method comprising receiving first fast data from the fast clock domain during a first fast clock cycle, wherein the first fast clock cycle is a first full fast clock cycle in a first slow clock cycle; and propagating, during the first full fast clock cycle in the first slow clock cycle, the received first fast data to the slow clock domain. Other embodiments are also described and claimed.

Abstract: Tri-level scrambling in a digital to analog converter system is achieved by, in response to a tri-level binary code input, disabling a negative data directed scrambler circuit when the input code is in the positive cycle portion, disabling a positive data directed scrambler circuit when the input code is in the negative cycle portion and disabling both scrambler circuits upon a zero input code for reducing low level distortion due to a reversal of current during crossover between those cycles.

Abstract: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.