Abstract: A technique for encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors include the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any disparity dependent encoded representations. Techniques for encoding 7B source vectors to 8B encoded vectors, and decoding techniques, are also provided.

Abstract: A method and a device for interpolating or decimating a signal is provided, the signal being processed by a plurality of signal processing means connected in series, which at least comprise means for increasing or reducing a clock rate of the signal and filtering means. To achieve adaptation to different operating modes or transmission standards, individual portions of the signal processing means connected in series can be bridged by bypasses. In addition, filtering parameters of the filtering means can be varied and factors, by which a clock rate of the signal is increased or reduced, can be changed.

Abstract: Disclosed is an apparatus and a method for down-converting frequencies of an input signal by separating the signal to which at least two frequencies are allocated according to each frequency, and then outputting at least two digital IF signals in a communication system. The digital down-converting apparatus includes a band-pass filter, an analog-to-digital converter, down-converters, up-converters, and Serializer/Deserializeres, etc. First, the signal to which at least two frequencies are allocated is down-converted into baseband signals respectively. Then, the baseband signals are up-converted into signals of a predetermined frequency respectively.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: A NICAM encoding method comprises performing NICAM processing and coupling a front-end to the NICAM processing. The front-end processing operates with a system clock that is integer divisible such that the system clock can be used by both the NICAM processing and the front-end processing. The front-end processing includes a front-end input processing and a front-end output processing. The front-end input processing is coupled to an input of the NICAM processing and the front-end output processing is coupled to an output of the NICAM processing.

Abstract: A method of resampling a digital signal involves serially receiving a plurality of samples of said digital signal and applying a plurality of filter coefficients to a first subset of the plurality of samples to generate a first plurality of intermediate results and to a second subset of the samples to generate a second plurality of intermediate results. The first plurality of intermediate results is accumulated to generate a first resampled value, and the second plurality of intermediate results is accumulated to generate a second resampled value. Upon receipt, each signal sample may be used to update each of a plurality of running accumulation values and then discarded before receipt of a next signal sample. Furthermore, multiple signals may be resampled concurrently using a single filter path by multiplexing circuit components, such as memory blocks.

Abstract: In a frequency analysis system, such as a signal detection system or a spectrum analyzer, the frequency domain resolution is enhanced by compression and decompression of the signal samples. The limited capacity of the data storage and/or data transfer resources limit the number of samples that can be stored or transferred. A compressor forms a compressed signal prior to data transfer or storage. A decompressor decompresses the compressed signal prior to transformation to the frequency domain, by a fast Fourier transform or other frequency domain transform. The frequency domain resolution is enhanced because more decompressed samples are available for the frequency domain transform. The compressor and decompressor apply computationally efficient algorithms that can be implemented to operate in real time.

Abstract: A sampling rate conversion system reduces the signal processing burdens carried by cellular phones, headsets, and other electronic devices. Because the system consumes fewer resources to convert between signal sampling rates, the system may significantly reduce processing time and resource requirements in the device. As a result, the device may instead devote resources to performing other useful tasks, such as interacting with the user through a graphical user interface and performing selected processing tasks.

Abstract: Control of signal compression is coordinated by selectively modifying control parameters affecting the bit rate, sample rate, dynamic range and compression operations. Selected control parameters are modified according to a control function. The control function can include a ratio parameter that indicates the relative or proportional amounts of change to the control parameters. Alternatively, the control function can be represented in a lookup table with values for the selected control parameters related by the control function. Downsampling the input signal samples according to a sample rate control parameter is followed by upsampling to the original sample rate. Errors are calculated between the upsampled and original signal samples. Encoding of the downsampled signal samples and the error samples is performed in accordance with a compression control parameter. The sample rate control parameter and compression control parameter are determined based on the control function.

Abstract: Semiconductor devices, a system including said semiconductor devices and methods thereof are provided. An example semiconductor device may receive data scheduled for transmission, scramble an order of bits within the received data, the scrambled order arranged in accordance with a given pseudo-random sequence. The received data may be balanced such that a difference between a first number of the bits within the received data equal to a first logic level and a second number of bits within the received data equal to a second logic level is below a threshold. The balanced and scrambled received data may then be transmitted. The example semiconductor device may perform the scrambling and balancing operations in any order. Likewise, on a receiving end, another semiconductor device may decode the original data by unscrambling and unbalancing the transmitted data. The unscrambling and unbalancing operations may be performed in an order based upon the order in which the transmitted data is scrambled and balanced.

Abstract: The invention allows the interpolation factor, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as CLOCK1=2*CLOCK2). This relationship leads to degenerate cases where, in fact, there are only one or two clocks to consider rather than three. Furthermore, the invention allows for input data rates that are higher than the DSP clock rate. The invention also provides for an arbitrary time delay to be applied to the output signal.

Abstract: A data processing device and adjusting method for adjusting the timing of a higher-rate stream of second data samples derived from a lower-rate stream of first data samples are described. A predetermined one of the first data samples is stored and first predetermined ones of the second data samples derived from the stored predetermined one of the first data samples are skipped to obtain an acceleration of the time base. Then, second predetermined ones of the second data samples following the skipped first predetermined ones of the second data samples are replaced by new second data samples derived from the stored predetermined one of the first data samples.

Abstract: A serial interface controller provides for transferring data between a data source having a least one channel and a processor. The serial interface controller has a plurality of control registers; the control registers in turn include a data structure for configuring the serial interface controller for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller; a field for storing the address of the active data channel; and, a field for storing the system clock rate.

Abstract: Techniques are described for sampling rate conversion in the digital domain by up-sampling and down-sampling a digital signal according to a selected intermediate sampling frequency. A prototype anti-aliasing filter that has a bandwidth with multiple factors is stored in memory. The techniques include selecting an intermediate sampling frequency to be an integer multiple of a desired output sampling frequency of a digital signal based on the factors of the prototype filter, and selecting a down-sampling factor to be the same integer associated with the selected intermediate sampling frequency. A filter generator generates an anti-aliasing filter for the selected down-sampling factor based on the prototype filter.

Abstract: Control of signal compression is coordinated by selectively modifying control parameters affecting the bit rate, sample rate, dynamic range and compression operations. Selected control parameters are modified according to a control function. The control function can include a ratio parameter that indicates the relative or proportional amounts of change to the control parameters. Alternatively, the control function can be represented in a lookup table with values for the selected control parameters related by the control function. The input signal samples can be resampled according to a sample rate control parameter. The dynamic range of signal samples can be selectively adjusted according to a dynamic range control parameter to form modified signal samples. The resampling and dynamic range adjustment can be applied in any order. The modified signal samples are encoded according to a compression control parameter to form compressed samples. The encoder can apply lossless or lossy encoding.

Abstract: Embodiments of an apparatus for sample rate conversion are described. Various embodiments include an interpolator configured to interpolate a digital input data stream by using values of an interpolation phase shift control quantity to generate a digital output data stream, a computing stage configured to compute values of the interpolation phase shift control quantity, and an enabling/disabling stage configured to selectively disable the interpolator while keeping the computing stage enabled.

Abstract: The sample rate of a digital signal is converted by a digital simulation of an analog filter. The simulation can update the states of complex poles in the analog filter at arbitrary times using different techniques. One technique updates the states at variable rates. Other techniques update the states at a fixed rate in response to values of input or output samples that are modified to account for offsets between the times of the samples and the times the states are updated. The states may be updated by using interpolations of complex exponential functions. Values of the complex exponential functions may be obtained from a product of values obtained from multiple lookup tables.

Abstract: The sample rate converter includes a synthesizing unit which synthesizes an input signal sampled with frequency fs with a feedback signal of the frequency fs, in a frequency band from 0 to fs/N (where N indicates a natural number), with a gain greater than at least 1, to generate a synthesized signal, a downsampler which downsamples the synthesized signal to obtain an output signal of sample rate fs/N, and an upsampler which upsamples the output signal to generate the feedback signal.

Abstract: A cascaded integrator comb filter includes a first integrator that receives an input signal x[n] and provides an integrated signal, and a fractional integrator that also receives the input signal x[n] and provides a fractional integrated signal. A summer sums the integrated signal and the fractional integrated signal and provides a summed signal indicative thereof to a second integrator, which receives and integrates the summed signal to provide a second integrator output signal. A decimator unit receives the second integrator output signal and provides a decimated signal to a differentiator that receives the decimated signal and provides a differentiated signal.

Abstract: In general, this disclosure describes techniques for changing a sampling frequency of a digital signal. In particular, the techniques provide a more accurate way to determining a relative timing between a desired output sample and a corresponding input sample using a non-approximated integer representation of the relative timing. The relative timing between the desired output sample and corresponding input sample may be represented using a first component that identifies a latest input sample of the digital signal used to generate intermediate samples, a second component that identifies an intermediate sample, and a third component that identifies a timing difference between the desired output sample and the intermediate sample. Each of the components may be recursively updated using non-approximated integer values.

Abstract: Control of signal compression is coordinated by selectively modifying control parameters affecting the bit rate, sample rate, dynamic range and compression operations. Selected control parameters are modified according to a control function. The control function can include a ratio parameter that indicates the relative or proportional amounts of change to the control parameters. Alternatively, the control function can be represented in a lookup table with values for the selected control parameters related by the control function. The input signal samples can be resampled according to a sample rate control parameter. The dynamic range of signal samples can be selectively adjusted according to a dynamic range control parameter to form modified signal samples. The resampling and dynamic range adjustment can be applied in any order. The modified signal samples are encoded according to a compression control parameter to form compressed samples. The encoder can apply lossless or lossy encoding.

Abstract: A data encoder. The novel encoder includes a first circuit for generating a fundamental sequence coded data stream from an incoming input data stream, a second circuit for generating a k-split data stream from the incoming data stream, and a third circuit for combining the fundamental sequence coded data stream and k-split data stream to form a final encoded output. The first circuit includes a circuit for converting the incoming input data stream into a novel intermediate format comprising a set bit word and a zero word count, and a zero-word expander for converting the intermediate format to the fundamental sequence coded data stream. The first circuit may also include a register adapted to store the intermediate format to provide rate buffering.

Abstract: The present invention is related to a circuit for converting the sample rate of a digital signal, comprising an input for applying the digital signal, a conversion filter having either a symmetrical or anti-symmetrical impulse response and implemented as a plurality of subfilters in parallel, each subfilter having a symmetrical or anti-symmetrical response derived from components of a polyphase decomposition of said impulse response, combining means for deriving from said applied digital signal input signals of said plurality of subfilters or for combining output signals of said plurality of subfilters into a digital signal with converted sample rate, an output for outputting said digital signal with converted sample rate.

Abstract: A method and apparatus are described for asynchronous sample rate conversion, in particular those which use an interpolating filter, especially a polyphase interpolating filter (FB4). The input and output signals have jitter but the polyphase branch signals have no or reduced jitter due to the operation of a jitter removing means such as a phase locked loop. The jitter is reduced only in the polyphase branch signals. Various methods are described for reducing the jitter.

Abstract: A fractional up-sampling filter is configured to convert a lower data rate to a higher data rate by using methods of interpolation to generate output digital data that corresponds to the higher data rate. For example, if the higher data rate output is 4/3 of the lower data rate input, then for every three (3) digital data values originally sampled by the fractional up-sampling filter, four (4) output digital data values are generated and output from the filter. These output digital data values are obtained by methods of interpolation. Interpolation is performed using different filter coefficients depending on the relative timing of the output digital data rate versus the original sampling rate. The fractional up-sampling filter utilizes a high frequency master clock to derive the fractional relationship between the original sampling rate to the new fractional sampling rate.

Abstract: Embodiments of an apparatus for sample rate conversion are described. Various embodiments include an interpolator configured to interpolate a digital input data stream by using values of an interpolation phase shift control quantity to generate a digital output data stream, a computing stage configured to compute values of the interpolation phase shift control quantity, and an enabling/disabling stage configured to selectively disable the interpolator while keeping the computing stage enabled.

Abstract: Methods and apparatus are provided for interfacing a plurality of encoded serial data streams, such as Serial Gigabit Media Independent Interface streams, to a serializer/deserializer circuit. A plurality of encoded serial data streams are transmitted by receiving the plurality of encoded serial data streams that have been encoded using an encoding scheme that provides a substantially uniform distribution of a first code and a second code; marking at least one of the encoded serial data streams (such as changing a first code to a predefined code); and combining at least two of the plurality of encoded serial data streams into a single data stream.

Abstract: An interpolation filter without a FIFO memory is configured as a cascade arrangement of simpler interpolation sub-filters that are operated in reverse order. The interpolation sub-filter that produces the highest sampling frequency is operated first, followed by interpolation sub-filters that operate at successively lower sampling frequencies. Computational independence of the cascaded sub-filters is guaranteed by adding delays to sampled and filtered signals. Delays are implemented by operating each of the cascaded sub-filters using prior filtering results that are computed during a previous sampling interval. A small increment to random-access memory is required for storing the successively delayed signals. The digital signal processor performing the filtering process is stalled for one clock cycle at the time a filtered signal sample is outputted so that the outputted signal sample can be produced without a timing conflict.

Abstract: Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

Abstract: Methods and systems for sample rate conversion convert a sampled signal to a higher data rate signal. Conversion pulses are received, having a conversion rate that is higher than the sample rate of the sampled signal. Sample points are then reconstructed from the sampled signal, in real time, on either side of a conversion pulse. An interpolation is performed between the reconstructed sample points, at the time of the conversion pulse. The interpolation results are outputted in real time. The process is repeated for additional conversion pulses. The outputted interpolated amplitudes form the higher data rate signal having a data rate equal to the conversion rate. Sample rate conversion is thus performed in real time according to the higher data rate clock, rather than with fixed ratios. As a result, when the higher data rate clock is affected by, for example, jitter or other frequency variations, the higher data rate samples immediately track the lower data rate samples.

Abstract: Embodiments of a sample rate converter and method for sample rate conversion are generally described herein. In some embodiments, an interpolation module calculates new digital samples for insertion into a digital sample ring, a cache module provides input digital samples of a digital sample stream to the interpolation module, and a control module maintains and provides state information to the interpolation module and the cache module. Based on pitch parameters, the control module provides the interpolation module a fractional portion of an address for use in calculating the new digital samples and provides the cache module with an integer portion of the address and an address increment.

Abstract: Aspects of a method and system for extending dynamic range of an RF signal are provided. In this regard, a signal representative of an amplitude of a pair of baseband signals may be generated. The amplitude of the generated signal may be expanded, and the amplitude of the baseband signals may be compressed. In this regard, the compression and the expansion may be inverse functions of each other. Additionally, the compressed baseband signals may be combined to generate an intermediate signal which may be amplitude modulated by the expanded signal. The amplitude modulation may result from controlling a gain, a voltage source, and/or a current source of a power amplifier. The intermediate signal may be generated by up-converting the baseband signals and subsequently combining the up-converted signals.

Abstract: A method, a component, a system, and a computer program for changing an encoding mode of an encoded data stream from a first encoding mode to a second encoding mode are disclosed. The encoded data stream at the first encoding mode is represented by first encoding parameters. For the encoding mode change the steps of selecting (20) a first set of the first encoding parameters to be used unchanged at the second encoding mode, selecting (30) a second set of the first encoding parameters, changing (40) the second set according to an algorithm being adapted to change the second set to match to the second encoding mode when combined with the first set, and combining (50) the first set and the changed second set for representing the encoded data stream by second encoding parameters at the second encoding mode are performed.

Abstract: A signal resampler carries out a time domain interpolation of an input signal for compensating for frequency offset, such as found in an ADSL system. A sample selector interpolator carries out part of the interpolation and a second, e.g. polynomial interpolator carries out the rest of the interpolation. The time interval between samples being interpolated, can be effectively divided between a sample selector interpolator and a small second, e.g. polynomial interpolator. The complexity of the second, e.g. polynomial interpolator can be reduced or its accuracy increased if it is effectively interpolating over a much smaller time interval. The sample selector interpolator can be an oversampling arrangement, and enable the order of the second, e.g. polynomial interpolator to be reduced. Selected ones of the oversampled samples are fed to the second, e.g. polynomial interpolator to keep the operating frequency lower. A chain of upsamplers can be used to generate the oversampled samples.

Abstract: A low-power data conversion system for converting a serial digital data input signal (DIN) to an analog output signal (Vout) by generating the serial digital data input signal (DIN) at a first sample rate (fsin) in a burst mode, wherein the sampling frequency of the serial digital data input signal (DIN) has a predetermined ratio to the frequency of an external reference clock signal (SLEEPCLK or WCLK). The serial digital data input signal (DIN) is converted into parallel format. A FIFO system temporarily stores a predetermined number of samples (Din) of the parallel format digital data input signal. The samples (Din) have a first sample rate (fsin). The samples (Din) are converted to an analog output signal (Vout).

Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce a

Abstract: A transcoder calculates a reference conversion factor on the basis of a ratio between a total target bit rate of a whole second stream and an total input bit rate of a whole first stream and calculates a coefficient of variation from the total target bit rate of the whole second stream and an average output bit rate of a converted second stream in the N period. Next, a quantization step conversion factor in the next (N+1) period is calculated by adding the coefficient of variation to the reference conversion factor. Then, a quantization step value of a second stream in the (N+1) period is calculated by multiplying a quantization step value of a first stream in the (N+1) period by the quantization step conversion factor.

Abstract: An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.

Abstract: In a sampling frequency conversion apparatus, an input sample register stores a predetermined number of input samples as an original sequence of input samples for an interpolative operation. A coefficient generating part prepares a first sequence of interpolative coefficients corresponding to an oversampled sequence of input samples which are obtained by inserting nominal input samples of zero values to the input samples stored in the input sample register, and generates a second sequence of interpolative coefficients which are extracted from the first sequence of the interpolative coefficients and which correspond to the original sequence of the input samples. A convolutional operation part convolutes the second sequence of the interpolative coefficients with the original sequence of the input samples so as to output an interpolated sample.

Abstract: Data rates of simultaneous radio transmissions of data are matched for services over a connection between a base station and a subscriber station by determining a service-specific rate matching factor for one of the services based on a steady-state rate matching factor and a dynamic rate matching factor. The dynamic connection-oriented rate matching factor is based on the steady-state matching factor. The dynamic-connection oriented rate matching factor matches a sum of a volume of data for the services over the connection to a volume of data available in a next frame of data. In addition, the data is compressed or expanded for the one of the services based on the corresponding service-specific rate matching factor.

Abstract: A sampling rate converter, a method of performing digital sampling rate conversion and a wireless transmitter incorporating the filter or the method. In one embodiment, the sampling rate converter includes: (1) an input configured to receive digital data from a first clock domain sampled at a first sampling rate, (2) an output configured to provide digital data to a second clock domain sampled at a second sampling rate that differs from the first sampling rate and (3) a filter with a second-order, polynomial-based impulse response coupled to the input and the output and configured to apply coefficients having only one nonunitary divisor to the digital data from the first clock domain.

Abstract: Methods for processing waveforms may include decimating an over-sampled waveform by identifying samples for which the sample's position within a data period indicates that is closest to a selected time within a data period. In some example applications, the selected time may be determined as a preferred time to sample the waveform within a data period. In an illustrative example, a sequence of samples representing an over-sampled waveform may be reduced by identifying a sample in each data period that is closest in time to the selected time. In another illustrative example, a sample within each data period may be identified if it falls within a range that is a function of the selected time within the data period and an integral ratio of a sample period to the data period. The identified samples may be used to reconstruct the original waveform with fewer samples than the over-sampled waveform.

Abstract: An audio codec in a wireless device may be utilized for up sampling two or more audio signals to a same data sampling rate. Each audio signal, such as digital audio, voice, and polyringer, for example, may be received at one of a plurality of data sampling rates. Audio signals may be equalized and/or compensated with an FIR filter before up sampling or with an IIR filter to reduce overall processing latency. Multiple half-band interpolation operations may perform the up sampling. The first half-band filter may be replaced by an IIR filter to reduce overall processing latency. A gain of the up-sampled data may be adjusted to reduce noise effects. The channels of the up-sampled audio signals may be mixed and later further up sampled for subsequent communication to an output device. The up-sampled mixed audio signals may be down sampled for communication to a Bluetooth radio.

Abstract: A double data rate (DDR) transmitter and a clock converter circuit are provided. The clock converter circuit includes a first logic circuit and a second logic circuit. The first logic circuit receives a clock signal as a trigger signal, performs a sequential logic operation based on the clock signal, and outputs a result of the sequential logic operation. The second logic circuit is coupled to the first logic circuit. The second logic circuit performs a combinational logic operation based on the output of the first logic circuit and outputs a result of the combinational logic operation as a converted signal. The converted signal has the same waveform and frequency as those of the clock signal, and the phases of the clock signal and the converted signal are the same or only slightly different.

Abstract: An iterative method provides an output value at each iteration, indicating a time position of an output sample to be generated in a subsequent processing step, relative to the time position of a known input sample. The method also provides an indication as to whether a new input sample needs to be used to generate the output sample.

Abstract: A sample rate converter for converting a digital input signal having a first sample rate into a digital output signal having a second sample rate, wherein the second sample rate is different from the first sample rate. The sample rate converter includes a digital interpolation filter receiving the input signal and comprising a digital zero-phase filter, and a digital polynom interpolator connected to the interpolation filter and providing the output signal.

Abstract: A digital radio system comprises a mixer and an analog-to-digital converter communicative coupled to the mixer. The mixer generates an intermediate frequency signal based at least in part upon a radio frequency signal and a local oscillator signal, wherein the intermediate frequency signal comprises a signal of interest having a particular bandwidth. The analog-to-digital converter generates a digital signal by quantizing the intermediate frequency signal using a sampling frequency that is greater than twice the bandwidth of the signal of interest and less than the frequency of the intermediate frequency signal.

Abstract: Described herein is a method and system for sampling rate conversion. A clamped cubic spline interpolator (CCSI) may be utilized to interpolate or decimate a source signal to provide samples at times based on a sink rate. The source clock and sink clock may be driven by independent oscillators, and may therefore drift independently. A rate tracking algorithm may monitor the relative drift and adjust the conversion of the source signal to track the sink rate.

Abstract: A sampling rate converter able to obtain an amplitude characteristic that passes any frequency and able to achieve a high precision conversion without depending upon a cutoff frequency, having an up sampler 103 for inserting (U-1) zero points between signals and raising a sampling frequency Fsi U-fold, a convolution processing unit 104 including an FIR filter and interpolating a value by convolution with respect to output signals of the up sampler, and a linear interpolation block 105 for selecting two points of samples from the output signal of the convolution processing unit 104 having a sampling frequency UFsi and finding the value at a required position from the linear interpolation, wherein the FIR filter has an impulse response becoming a filter coefficient, having a transmission function H(z) associated with a transmission function Z(z) of a pre-filter, and having a filter coefficient set by performing weighted approximation with respect to a desired characteristic associated with the frequency respons

Abstract: A method for accelerating a pseudo-random input bit flow (PRBS(T1)), generated at a first relatively low dock frequency (f1), into an identical output bit flow (PRBS(T0)) at a second relatively high dock frequency (f0), comprising: collecting the output bit flow, delaying the collected flow by a predetermined value (?); and combining the delayed flow with the input bit flow.