Abstract: A talker prediction method obtains a voice from a plurality of talkers, records a conversation history of the plurality of talkers, identifies a talker of the obtained voice, and predicts a next talker among the plurality of talkers based on the identified talker and the conversation history.

Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.

Abstract: A signal processing method of a semiconductor device, the method including: receiving a first digital code of a first digital signal; generating a constraint vector; masking the first digital code with a transmitting mask based on the constraint vector; and outputting the masked first digital code and a Data Bus Inversion (DBI) bit of the mask.

Abstract: A video encoder may be configured to apply a multi-stage quantization process, where residuals are first quantized using an effective quantization parameter derived from the statistics of the samples of the block. The residual is then further quantized using a base quantization parameter that is uniform across a picture. A video decoder may be configured to decode the video data using the base quantization parameter. The video decoder may further be configured to estimate the effective quantization parameter from the statistics of the decoded samples of the block. The video decoder may then use the estimated effective quantization parameter for use in determining parameters for other coding tools, including filters.

Abstract: A system comprises a forward error correction decoder comprising syndrome computation circuitry, key-equation solver circuitry, and search and evaluator circuitry. The syndrome computation circuitry may comprise a plurality of syndrome compute units connected in parallel. The syndrome computation circuitry may be dynamically configurable to vary a quantity of the syndrome compute units used for processing of a codeword based on conditions of a channel over which the codeword was received. The syndrome computation circuitry may be operable to use a first quantity of the syndrome compute units for processing of a first codeword received over the channel when the channel is characterized by a first bit error rate and a second quantity of the syndrome compute units for processing of a second codeword received over the channel when the channel is characterized by a second bit error rate.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: Performing a constant time cyclic redundancy check (CRC) over an entire packet to obtain a constant time CRC value. A first CRC is performed on an original header of the packet and a second CRC is performed on a modified header of the packet. The size of the payload of the packet is obtained. An XOR operation is performed on the results of the first and second CRC to calculate a third result. An intermediate CRC value is obtained by performing a CRC on a number of zero values corresponding to the size of the payload using the third result as an initial value. The intermediate CRC value may be employed with other packets having a same size and same header as the packet. The constant time CRC value is obtained by performing an XOR operation on the intermediate CRC value and the original CRC value contained in the packet.

Abstract: Various aspects include methods and devices for implementing the methods for error checking a memory system. Aspects may include receiving, from a row buffer of a memory, access data corresponding to a column address of a memory access, in which the row buffer has data of an activation unit of the memory corresponding to a row address of the memory access, determining multiple error correction codes (ECCs) for the access data using the column address, and checking the access data for an error utilizing at least one of the multiple ECCs. In some aspects, the multiple ECCs may include a first ECC having data from an access unit of the memory corresponding with the column address, and at least one second ECC having data from the access unit and data from the activation unit other than from the access unit.

Abstract: A transmitter (200) generates (602) an encoded vector (404) by encoding (406) a data vector (402), the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits (604) a signal representing the encoded vector over a communication channel. A receiver (300) determines (702) a vector estimate (502) from the signal and recovers (716) the data vector from the vector estimate by sequentially decoding (706, 710, 714) the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: A method for diagnosing memory, performed by a storage system, is provided. The method includes writing and reading through a communication channel to and from flash memory of each of a plurality of flash memory devices and a static random-access memory (SRAM) register of each of the plurality of flash memory devices. The method includes analyzing errors in read data from the reading through the communication channel, identifying types of errors among flash memory errors, SRAM register errors, and communication channel errors, based on the analyzing, and indicating at least one error and type of error from the read data.

Abstract: A mobile device, such as a cellular telephone or a personal digital assistant (PDA), stores first personal data, such as any one or more of image, video, and audio data. The mobile device transmits the first personal data over a first wide area network (WAN) to a personal server.

Abstract: A polar-code based encoder is used to perform a transfer of useful data to a polar-code based decoder via a Binary Discrete-input Memory-less Channel. The Divide and Conquer structure consists of a multiplexer having useful data bits and a set of frozen bits as inputs followed by a polarization block of size N=2L, wherein the polarization block of size N comprises a set of front kernels followed by a shuffler and two complementary polarization sub-blocks of size N/2 with a similar structure as the polarization block of size N but with half its size. A dynamically configurable interleaver is present between the shuffler and one and/or the other of the complementary polarization sub-blocks at each recursion of the Divide and Conquer structure. The configuration of the dynamically configurable interleavers is dynamically modified according to changes detected in the Binary Discrete-input Memory-less Channel.

Abstract: Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded to produce a first decoded output, which is subsequently encoded, and error characteristics of the encoded first decoded output are assessed. The input signal is again decoded (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.

Abstract: A method for decoding a digital signal encoded using predictive coding and transform coding, comprising the following steps: predictive decoding of a preceding frame of the digital signal, encoded by a set of predictive coding parameters; detecting the loss of a current frame of the encoded digital signal; generating by prediction, from at least one predictive coding parameter encoding the preceding frame, a frame for replacing the current frame; generating by prediction, from at least one predictive coding parameter encoding the preceding frame, an additional segment of digital signal; temporarily storing said additional segment of digital signal.

Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.

Abstract: An integrated digital-analog archiving system can automatically initiate a migration process to move electronic documents to a media library. For each electronic document, the system may retrieve the electronic document from a digital data storage medium, extract metadata from the electronic document, determine size, orientation, and format of the electronic document, generate indicators for indicating the start and end of the electronic document to be stored on an analog data storage medium, generate an analog document identifier for identifying the electronic document on the analog data storage medium, generate a scaled image of the electronic document based on the size, orientation, and format of the electronic document, generate a text string based at least in part on the extracted metadata, and render the indicators, the analog document identifier, the scaled image of the electronic document, and the text string on the analog data storage medium.

Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.

Abstract: According to various embodiments, there may be provided a method of encoding data, the method including providing a set of replica nodes, wherein each replica node of the set of replica nodes stores replica data identical to original data stored in a corresponding original node of a set of original nodes; receiving original data at each replica node of the set of replica nodes, wherein the received original data is transmitted from the corresponding original node of a different replica node; generating a first result at each replica node, based on the replica data stored therein and the received original data; and generating a second result at each replica node, based on the replica data stored therein and the first result from a different replica node; and replacing the replica data in each replica node with the second result from the respective replica node.

Abstract: A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.

Abstract: A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.

Abstract: Disclosed is an optical transceiver. The optical transceiver includes a decoder for decoding an 8B10B line-coded signal, a data mapper for separating the decoded signal into block units and securing extra memory capacity by mapping a data code and a block information code onto each of the separated blocks, and an FEC encoding unit for creating Forward Error Correction (FEC) data and mapping the FEC data onto the extra memory capacity.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.

Abstract: A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, an apparatus includes a processor configured to encode user data into a set of data fragments and to transmit each data fragment of the set of data fragments in a plurality of discovery messages. In another aspect, the apparatus includes a processor configured to receive one or more discovery messages, determine whether each of the received one or more discovery messages includes an encoded data fragment of a set of encoded data fragments associated with user data, determine whether a minimum number of encoded data fragments have been received from the received one or more discovery messages to enable reconstruction of the user data, and reconstruct the user data based on the determination of whether the minimum number of encoded data fragments is received.

Abstract: Provided are a frame error concealment method and apparatus and an error concealment scheme construction method and apparatus. The frame error concealment method includes generating a new signal by synthesizing a plurality of previous signals that are similar to a signal of an error frame and reconstructing the signal of the error frame using the generated signal.

Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.

Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.

Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.

Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.

Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.

Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks (S11) sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates (S12) the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs (S13) an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.

Abstract: Disclosed is an optical transceiver. The optical transceiver includes a decoder for decoding an 8B10B line-coded signal; a data mapper for separating the decoded signal into block units and securing extra memory capacity by mapping a data code and a block information code onto each of the separated blocks; and an FEC encoding unit for creating a Forward Error Correction (FEC) data and mapping the FEC data onto the extra memory capacity.

Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks (S11) sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates (S12) the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs (S13) an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.

Abstract: A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.

Abstract: A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder.

Abstract: Techniques that address content interruptions are described. In an implementation, an interruption is detected at the client device in receipt of a stream of content from a distribution system that is to be recorded locally in memory at the client device. A stream of content is generated at the client device and the generated stream of content is recorded to fill the interruption in the stream of content from the distribution system in the memory of the client device.

Abstract: Data flow control in a television receiver controls the output of the frequency deinterleaver (FDI) and the time deinterleaver (TDI) to prioritize processing control information having transmission parameters needed for processing data, thereby facilitating use of one FEC decoder.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: A turbo encoder apparatus includes: a first element encoder for receiving an input of a bitstream of the data, encoding the input of the bitstream of the data, and generating a first output bitstream in an unit of plural bits; an internal interleaver for generating an interleaved input bitstream from the bitstream of the data; a second element encoder for receiving an input of the interleaved input bitstream in the unit of plural bits, encoding the input of the interleaved input bitstream, and generating a second output bitstream in an unit of plural bits; a trellis-termination-encoder for generating bits for trellis terminations of the first element encoder and the second element encoder; and a bitstream assembler for receiving the first output bitstream, the second output bitstream, and the bits for the trellis terminations and generating an input bitstream for a rate matching.

Abstract: A method is provided for hierarchical coding of a digital audio signal comprising, for a current frame of the input signal: a core coding, delivering a scalar quantization index for each sample of the current frame and at least one enhancement coding delivering indices of scalar quantization for each coded sample of an enhancement signal. The enhancement coding comprises a step of obtaining a filter for shaping the coding noise used to determine a target signal and in that the indices of scalar quantization of said enhancement signal are determined by minimizing the error between a set of possible values of scalar quantization and said target signal. The coding method can also comprise a shaping of the coding noise for the core bitrate coding. A coder implementing the coding method is also provided.

Abstract: Methods and circuits are described for creating low-weight codes, encoding of data as low-weight codes for communication or storage, and efficient decoding of low-weight codes to recover the original data. Low-weight code words are larger than the data values they encode, and contain a significant preponderance of a single value, such as zero bits. The resulting encoded data may be transmitted with significantly lower power and/or interference.

Abstract: A data predicted value generating unit generates a predicted value (data predicted value) for original data intended to be encoded, based on a history of original data which is floating-point data. A data predicted value modifying unit adjusts a mantissa value of the data predicted value by aligning an exponent value of the data predicted value with an exponent value of the original data. A first residual generating unit generates a residual (first residual) between new original data and the data predicted value after being adjusted. A first residual predicted value generating unit generates a predicted value for the first residual (first residual predicted value), based on a history of first residuals. A second residual generating unit generates a residual (second residual) between the first residual and the first residual predicted value. A residual encoding unit generates encoded data by encoding the second residual.

Abstract: In an embodiment, a data encoding method may be provided. The data encoding method may include: inputting data to be encoded; determining a polynomial so that an evaluation of the polynomial at a sum of a first supporting point of the polynomial and a second supporting point of the polynomial corresponds to the sum of an evaluation of the polynomial at the first supporting point and an evaluation of the polynomial at the second supporting point, wherein coefficients of the polynomial are determined based on the data to be encoded; and generating a plurality of encoded data items by evaluating the polynomial at a plurality of supporting points.

Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.

Abstract: Disclosed is a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology. There are effects of reducing a time spent for performing an encoding by performing the encoding in the unit of plural bits every clock cycle and performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus.

Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.

Abstract: In an audio network system constructed from a main node and a plurality of satellite nodes each having a plurality of ports, the main node generates and transmits a main packet including audio signals of a plurality of channels. Each satellite node selects one of the plurality of ports in turn, and confirms whether the main packet arrives at the selected port every predetermined period or not. When the main packet arrives at the selected port every predetermined period, the main packet is received via the port by continuing selection of the port. In the case where reception of the main packet is lost, one is selected from the plurality of ports in turn, the operation to confirm arrival of the main packet is restarted, and another port at which the main packet arrives at the present stage is automatically found.