With Error Detection Or Correction Patents (Class 341/94)
  • Patent number: 10324787
    Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 18, 2019
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yu-Hsiang Lin, Shao-Wei Yen, Yu-Siang Yang, Kuo-Hsin Lai
  • Patent number: 10187084
    Abstract: According to various embodiments, there may be provided a method of encoding data, the method including providing a set of replica nodes, wherein each replica node of the set of replica nodes stores replica data identical to original data stored in a corresponding original node of a set of original nodes; receiving original data at each replica node of the set of replica nodes, wherein the received original data is transmitted from the corresponding original node of a different replica node; generating a first result at each replica node, based on the replica data stored therein and the received original data; and generating a second result at each replica node, based on the replica data stored therein and the first result from a different replica node; and replacing the replica data in each replica node with the second result from the respective replica node.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: January 22, 2019
    Assignee: NANYANG TECHNOLOGICAL UNIVERSITY
    Inventor: Anwitaman Datta
  • Patent number: 10110251
    Abstract: A method and a system for data transmission are provided. The method includes: determining a size of a first block and a first degree distribution for a first data transmission according to a parameter which is related to a hardware specification of a receiving node; determining a channel loss rate of a channel between a sending note and the receiving node when completing the first data transmission; determining a size of a second block and a second degree distribution for a second data transmission according to the channel loss rate; and performing, by the sending node and the receiving node, the second data transmission according to the size of the second block and the second degree distribution.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 23, 2018
    Assignee: National Chiao Tung University
    Inventors: Hsie-Chia Chang, Kuo-Kuang Yen, Yen-Chin Liao
  • Patent number: 10097208
    Abstract: A decoder includes an error locator polynomial generator circuit configured to determine, during a first cycle of a clock signal, a first value of a parameter. The first value of the parameter is associated with a first iteration of a decode operation and is based on a value of an error locator polynomial associated with a prior iteration of the decode operation. The error locator polynomial generator circuit is further configured to determine, during a second cycle of the clock signal that sequentially follows the first cycle or during a third cycle of the clock signal that sequentially follows the second cycle, an adjusted value of the error locator polynomial. The adjusted value of the error locator polynomial is associated with a second iteration of the decode operation and is based on the first value of the parameter.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ishai Ilani, Idan Alrod
  • Patent number: 10044468
    Abstract: Disclosed is an optical transceiver. The optical transceiver includes a decoder for decoding an 8B10B line-coded signal, a data mapper for separating the decoded signal into block units and securing extra memory capacity by mapping a data code and a block information code onto each of the separated blocks, and an FEC encoding unit for creating Forward Error Correction (FEC) data and mapping the FEC data onto the extra memory capacity.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 7, 2018
    Assignee: OE SOLUTIONS AMERICA, INC.
    Inventors: Wanseok Seo, Jong Ho Kim, Moon Soo Park, Joon Sang Yu
  • Patent number: 10037243
    Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 31, 2018
    Assignee: InterDigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Patent number: 10013989
    Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: July 3, 2018
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Sebastian Näslund, Volodya Grancharov, Jonas Svedberg
  • Patent number: 9949168
    Abstract: A method, an apparatus, and a computer-readable medium for wireless communication are provided. In one aspect, an apparatus includes a processor configured to encode user data into a set of data fragments and to transmit each data fragment of the set of data fragments in a plurality of discovery messages. In another aspect, the apparatus includes a processor configured to receive one or more discovery messages, determine whether each of the received one or more discovery messages includes an encoded data fragment of a set of encoded data fragments associated with user data, determine whether a minimum number of encoded data fragments have been received from the received one or more discovery messages to enable reconstruction of the user data, and reconstruct the user data based on the determination of whether the minimum number of encoded data fragments is received.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Todd Mizenko, James Kelleman
  • Patent number: 9858933
    Abstract: Provided are a frame error concealment method and apparatus and an error concealment scheme construction method and apparatus. The frame error concealment method includes generating a new signal by synthesizing a plurality of previous signals that are similar to a signal of an error frame and reconstructing the signal of the error frame using the generated signal.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-sang Sung, Ki-hyun Choo, Jung-hoe Kim, Eun-mi Oh, Chang-yong Son, Kang-eun Lee
  • Patent number: 9538203
    Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: January 3, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Park, Yong-je Kim, Yung-lyul Lee
  • Patent number: 9538201
    Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: January 3, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Park, Yong-je Kim, Yung-lyul Lee
  • Patent number: 9532078
    Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Park, Yong-je Kim, Yung-lyul Lee
  • Patent number: 9532077
    Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: December 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Park, Yong-je Kim, Yung-Iyul Lee
  • Patent number: 9532079
    Abstract: Provided are a filtering method and apparatus for removing blocking artifacts and ringing noise. The filtering method includes transforming video data on a block-by-block basis, and detecting the presence of an edge region in the video data by checking the distribution of values obtained by the transformation. Accordingly, it is possible to completely remove blocking artifacts and/or ringing noise by more effectively detecting the presence of an edge region in video data.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: December 27, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Park, Yong-je Kim, Yung-Iyul Lee
  • Patent number: 9514756
    Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks (S11) sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates (S12) the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs (S13) an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 6, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Sebastian Näslund, Volodya Grancharov, Jonas Svedberg
  • Patent number: 9485056
    Abstract: Disclosed is an optical transceiver. The optical transceiver includes a decoder for decoding an 8B10B line-coded signal; a data mapper for separating the decoded signal into block units and securing extra memory capacity by mapping a data code and a block information code onto each of the separated blocks; and an FEC encoding unit for creating a Forward Error Correction (FEC) data and mapping the FEC data onto the extra memory capacity.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: November 1, 2016
    Assignee: OPTO ELECTRONICS SOLUTIONS CO., LTD.
    Inventors: Wanseok Seo, Jong Ho Kim, Moon Soo Park, Joon Sang Yu
  • Patent number: 9478222
    Abstract: A frame error concealment method based on frames including transform coefficient vectors including the following steps: It tracks (S11) sign changes between corresponding transform coefficients of predetermined sub-vectors of consecutive good stationary frames. It accumulates (S12) the number of sign changes in corresponding sub-vectors of a predetermined number of consecutive good stationary frames. It reconstructs (S13) an erroneous frame with the latest good stationary frame, but with reversed signs of transform coefficients in sub-vectors having an accumulated number of sign changes that exceeds a predetermined threshold.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 25, 2016
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Sebastian Näslund, Volodya Grancharov, Jonas Svedberg
  • Patent number: 9459836
    Abstract: A simplified inversionless Berlekamp-Massey algorithm for binary BCH codes and circuit implementing the method are disclosed. The circuit includes a first register group, a second register group, a control element, an input element and a processing element. By breaking the completeness of math structure of the existing simplified inversionless Berlekamp-Massey algorithm, the amount of registers used can be reduced by two compared with conventional algorithm. Hardware complexity and operation time can be reduced.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: October 4, 2016
    Assignee: Storart Technology Co., Ltd.
    Inventors: Jui Hui Hung, Chih Nan Yen
  • Patent number: 9374586
    Abstract: A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: June 21, 2016
    Assignee: NORTH STAR INNOVATIONS INC.
    Inventor: Zhongli He
  • Patent number: 9223643
    Abstract: Techniques that address content interruptions are described. In an implementation, an interruption is detected at the client device in receipt of a stream of content from a distribution system that is to be recorded locally in memory at the client device. A stream of content is generated at the client device and the generated stream of content is recorded to fill the interruption in the stream of content from the distribution system in the memory of the client device.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: December 29, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Paul R. Cooper, Matt Henry Van der Staay, Chad Michael Williams
  • Patent number: 9106265
    Abstract: Data flow control in a television receiver controls the output of the frequency deinterleaver (FDI) and the time deinterleaver (TDI) to prioritize processing control information having transmission parameters needed for processing data, thereby facilitating use of one FEC decoder.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 11, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Frederic Nicolas, Olivier Souloumiac, David Rault
  • Patent number: 9007240
    Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventor: Wayne M. Barrett
  • Patent number: 9000959
    Abstract: A turbo encoder apparatus includes: a first element encoder for receiving an input of a bitstream of the data, encoding the input of the bitstream of the data, and generating a first output bitstream in an unit of plural bits; an internal interleaver for generating an interleaved input bitstream from the bitstream of the data; a second element encoder for receiving an input of the interleaved input bitstream in the unit of plural bits, encoding the input of the interleaved input bitstream, and generating a second output bitstream in an unit of plural bits; a trellis-termination-encoder for generating bits for trellis terminations of the first element encoder and the second element encoder; and a bitstream assembler for receiving the first output bitstream, the second output bitstream, and the bits for the trellis terminations and generating an input bitstream for a rate matching.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 7, 2015
    Assignee: InnoWireless Co., Ltd.
    Inventors: Jinsoup Joung, Joohyeong Lee, Jongho Lim, Seungkeun Yook, Ji Hye Shin
  • Patent number: 8965773
    Abstract: A method is provided for hierarchical coding of a digital audio signal comprising, for a current frame of the input signal: a core coding, delivering a scalar quantization index for each sample of the current frame and at least one enhancement coding delivering indices of scalar quantization for each coded sample of an enhancement signal. The enhancement coding comprises a step of obtaining a filter for shaping the coding noise used to determine a target signal and in that the indices of scalar quantization of said enhancement signal are determined by minimizing the error between a set of possible values of scalar quantization and said target signal. The coding method can also comprise a shaping of the coding noise for the core bitrate coding. A coder implementing the coding method is also provided.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: February 24, 2015
    Assignee: Orange
    Inventors: Balazs Kovesi, Stéphane Ragot, Alain Le Guyader
  • Patent number: 8952834
    Abstract: Methods and circuits are described for creating low-weight codes, encoding of data as low-weight codes for communication or storage, and efficient decoding of low-weight codes to recover the original data. Low-weight code words are larger than the data values they encode, and contain a significant preponderance of a single value, such as zero bits. The resulting encoded data may be transmitted with significantly lower power and/or interference.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 10, 2015
    Assignee: Kandou Labs, S.A.
    Inventor: Harm Cronie
  • Patent number: 8947274
    Abstract: A data predicted value generating unit generates a predicted value (data predicted value) for original data intended to be encoded, based on a history of original data which is floating-point data. A data predicted value modifying unit adjusts a mantissa value of the data predicted value by aligning an exponent value of the data predicted value with an exponent value of the original data. A first residual generating unit generates a residual (first residual) between new original data and the data predicted value after being adjusted. A first residual predicted value generating unit generates a predicted value for the first residual (first residual predicted value), based on a history of first residuals. A second residual generating unit generates a residual (second residual) between the first residual and the first residual predicted value. A residual encoding unit generates encoded data by encoding the second residual.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hideya Shibata
  • Patent number: 8930798
    Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Thomas Mittelholzer
  • Patent number: 8928503
    Abstract: In an embodiment, a data encoding method may be provided. The data encoding method may include: inputting data to be encoded; determining a polynomial so that an evaluation of the polynomial at a sum of a first supporting point of the polynomial and a second supporting point of the polynomial corresponds to the sum of an evaluation of the polynomial at the first supporting point and an evaluation of the polynomial at the second supporting point, wherein coefficients of the polynomial are determined based on the data to be encoded; and generating a plurality of encoded data items by evaluating the polynomial at a plurality of supporting points.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: January 6, 2015
    Assignee: Nanyang Technological University
    Inventors: Frederique Oggier, Anwitaman Datta
  • Publication number: 20140375485
    Abstract: Disclosed is a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology. There are effects of reducing a time spent for performing an encoding by performing the encoding in the unit of plural bits every clock cycle and performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus.
    Type: Application
    Filed: February 24, 2012
    Publication date: December 25, 2014
    Applicant: INNOWIRELESS CO., LTD.
    Inventors: Jinsoup Joung, Joohyeong Lee, Jongho Lim, Seungkeun Yook, Ji Hye Shin
  • Patent number: 8890722
    Abstract: A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Atul A. Salvekar, Young Geun Cho, Jia Tang, Shantanu Khare, Ming-Chieh Kuo, Iwen Yao
  • Patent number: 8862972
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Bradley D. Seago, Scott M. Dziak, Jingfeng Liu
  • Patent number: 8823558
    Abstract: System, computer program product, and computer-implemented method to improve a running disparity of an encoded bit stream in a distributed network switch, the distributed network switch comprising a plurality of switch modules including a first switch module, by receiving, at the first switch module, a raw data stream comprising a plurality of bits, receiving a bit sequence, encoding at least a first bit of the raw data stream using a corresponding at least a first bit of the bit sequence, transmitting the encoded first bit, inverting the first bit of the bit sequence, and encoding a second bit of the raw data stream using the inverted first bit.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventor: Wayne M. Barrett
  • Patent number: 8761208
    Abstract: In an audio network system constructed from a main node and a plurality of satellite nodes each having a plurality of ports, the main node generates and transmits a main packet including audio signals of a plurality of channels. Each satellite node selects one of the plurality of ports in turn, and confirms whether the main packet arrives at the selected port every predetermined period or not. When the main packet arrives at the selected port every predetermined period, the main packet is received via the port by continuing selection of the port. In the case where reception of the main packet is lost, one is selected from the plurality of ports in turn, the operation to confirm arrival of the main packet is restarted, and another port at which the main packet arrives at the present stage is automatically found.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 24, 2014
    Assignee: Yamaha Corporation
    Inventor: Peter Charles Eastty
  • Publication number: 20140152476
    Abstract: In an embodiment, a data encoding method may be provided. The data encoding method may include: inputting data to be encoded; determining a polynomial so that an evaluation of the polynomial at a sum of a first supporting point of the polynomial and a second supporting point of the polynomial corresponds to the sum of an evaluation of the polynomial at the first supporting point and an evaluation of the polynomial at the second supporting point, wherein coefficients of the polynomial are determined based on the data to be encoded; and generating a plurality of encoded data items by evaluating the polynomial at a plurality of supporting points.
    Type: Application
    Filed: December 8, 2010
    Publication date: June 5, 2014
    Applicant: Nanyang Technological University
    Inventors: Frederique Oggier, Anwitaman Datta
  • Patent number: 8707129
    Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: April 22, 2014
    Assignee: Interdigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Patent number: 8692697
    Abstract: A method and apparatus for encoding based on a linear block code, and a method and apparatus for generating a linear block code are provided. The method for encoding based on a linear block code includes: generating a linear block code; and encoding an information sequence with an encoding matrix of the linear block code to obtain a bit stream sequence. The linear block codes have a good minimum distance characteristic, so that the error correction performance is improved.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: April 8, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Ying Xu, Shaofang Wang
  • Patent number: 8633840
    Abstract: A determining method and apparatus thereof for a transition point of a sequence which can be applied to a decoder. The determining method determines the transition point of the sequence having N numbers, wherein the sequence is composed of a first value and a second value and N is a positive integer. The determining method includes determining the position the first value appearing consecutively in the sequence to determine a first interval; determining the position the second value appearing consecutively in the sequence to determine a second interval; and determining the longer interval between the first interval and the second interval, when the first interval is longer, determining an adjacency of the first interval and the second value as the transition point according to the first interval, and when the second interval is longer, determining an adjacency of the second interval and the first value as the transition point.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: January 21, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Po Lin Yeh, Chien-Hsing Lin, Jui-Hua Yeh, Shao Ping Hung, Chih-Tien Chang
  • Patent number: 8618963
    Abstract: An embodiment of a bit converter includes a substitution module and an output module. The substitution module substitutes a decision result representing one of “0” and “1” for input bit information based on a substitution rule for bit information for converting a bit string of a predetermined pattern into a predetermined code word. The output module outputs the decision result of the bit information substituted by the substitution module, to a decoder configured to decode the decision result into the predetermined code word.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Yoshida
  • Publication number: 20130321183
    Abstract: Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventor: Kenneth W. Fernald
  • Patent number: 8582668
    Abstract: An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. Another embodiment is a method and apparatus to decode a signal using averaging. A channel estimator provides a channel estimate. A multiplier multiplies a quantized output of a demodulator with the channel estimate to produce N symbols of a signal corresponding to a carrier. A de-interleaver de-interleaves the N symbols. An averager averages the N de-interleaved symbols to generate a channel response at a carrier.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: November 12, 2013
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kaveh Razazian, Maher Umari, Amir Hosein Kamalizad
  • Patent number: 8572461
    Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: October 29, 2013
    Assignee: Interdigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Publication number: 20130259146
    Abstract: A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
    Type: Application
    Filed: April 1, 2013
    Publication date: October 3, 2013
    Applicant: STMicroelectronics S.r.l.
    Inventors: Daniele Mangano, Salvatore Pisasale, Carmelo Pistritto
  • Patent number: 8525707
    Abstract: The present invention is related to systems and methods for applying two or more data decode algorithms to a processing data set.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventors: Fan Zhang, Chung-Li Wang, Shaohua Yang, Haitao Xia
  • Patent number: 8522119
    Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 27, 2013
    Assignee: XILINX, Inc.
    Inventors: Christopher H. Dick, Raghavendar M. Rao
  • Patent number: 8508391
    Abstract: Systems, methods, and other embodiments associated with an encoder. In one embodiment, a system includes an encoder having a code word generator and an appending logic. The code word generator is configured to generate code words based on input data and identify one or more short code words. A short code word has a length less than a length of a full code word. The appending logic is configured to append at least one dummy value to at least one of the short code words to convert the at least one short code word to a full code word. The encoder may further be configured to encode the converted full code word and store the converted full code word without the at least one dummy value in a storage medium.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: August 13, 2013
    Assignee: Marvell International Ltd
    Inventors: Shu Li, Panu Chaichanavong, Jun Gao
  • Patent number: 8502711
    Abstract: This invention relates to a coding circuit for generating a swap tolerant code. The coding circuit comprises a first and second input (540, 541), an odd parity pair detector (535), a memory (533), and an output circuit (536, 537, 551; 736, 737, 751). Each of the first and second inputs (540, 541) receive a stream of serial data. The odd parity pair detector (535) outputs an odd parity pair signal if the bits received at said first and second inputs (540, 541) have different logical values and therefore constitute an odd parity pair. The memory (533) stores information on a previous odd parity pair. The output circuit outputs the previous odd parity pair, if said first input (540) provides a logical 1 and said second input (541) provides a logical 0. The output circuit outputs the inverted previous odd parity pair, if said first input (540) provides a logical 0 and said second input (541) provides a logical 1. The invention further provides a corresponding decoding circuit, and coding and decoding methods.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: August 6, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Thomas Bellingrath
  • Patent number: 8504847
    Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.
    Type: Grant
    Filed: April 18, 2010
    Date of Patent: August 6, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Wesley Leggette
  • Patent number: 8497787
    Abstract: Systems and methods for decoding data using a hybrid decoder are provided. A data signal that includes a codeword is received. A signal quality indicator for the data signal is computed. One of a plurality of decoders is selected based on the computed signal quality indicator. Each of the plurality of decoders is configured to decode information based on a different decoding technique. The codeword included in the data signal is decoded using the selected one of the plurality of decoders.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: July 30, 2013
    Assignee: Marvell World Trade Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8472479
    Abstract: A data transmission apparatus for sequentially transmitting data in units of packets each containing transmission data to the receiving end. The apparatus including a reception unit receiving the transmission data as an input signal, a packet formation unit receiving the transmission data, and forming an uncompressed packet in which predetermined transmission data is stored as uncompressed data, and a compressed packet in which at least a portion of transmission data that follows the predetermined transmission data is compressed and stored as compressed data. The apparatus also including a reference information management unit holding and managing as reference information related to the uncompressed packet, and a transmission unit transmitting the packets formed by the packet formation unit. The packet formation unit forming compressed data to be stored in a compressed packet, based on the transmission data of the uncompressed packet and the reference information.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: June 25, 2013
    Assignee: Panasonic Corporation
    Inventors: Akihiro Miyazaki, Hideaki Fukushima, Carsten Burmeister, Rolf Hakenberg
  • Publication number: 20130147645
    Abstract: A data encoding circuit and a corresponding method is provided. The data encoding circuit includes a first data formatter in communication with an encoder section. The first data formatter is configured to receive blocks of source data in serial and output parallel two dimensional source data. The encoder receives the parallel two dimensional source data and that computes a plurality of serial row parity bits and a plurality of parallel column parity bits of an error correcting code from the parallel two dimensional source data. A second data formatter communicates with the encoder section and receives the parallel column parity bits and outputs serial column parity bits. A multiplexer section multiplexes the blocks of source data, the serial row parity bits, and the serial column parity bits into an output stream including the blocks of source data encoded by the error correcting code.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: BROADCOM CORPORATION
    Inventor: Zhongfeng Wang