Abstract: A system and method for providing a method for reducing artifacts in a video sequence of image frames is disclosed. The method and system include classifying scenes in the sequence of image frames, analyzing the content of the image frames and performing temporal filtering on the image frames. The method and system further include applying a set of rules to results of the classification and the content analysis to adapt characteristics of the temporal filtering for the scene.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: An EFM data decoding method and apparatus thereof for optical disk system is provided. According to the method, a 14-bit data complying with the EFM modulation criteria but failing to correspond to a 8-bit data based on an EFM decoding table is transformed successfully by looking up an expanded EFM decoding table. The expanded EFM decoding table includes probable 8-bit data corresponding to the erroneous data complying with the EFM modulation criteria. Reliability of data reading is thus enhanced in the present invention.

Abstract: Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold.

Abstract: Described are a system and method for transmitting digital messages through wire channels and telecommunication channels using electromagnetic waves. The use of the channels is simplified by excluding multiplication and division operators from the coding and a decoding process. The system and method allows to transmit any messages from elements of Abelian group including code words whose elements are matrixes, polynomials, numbers of mixed-base notation and nonpositional notation. An encoder of the system may include a driver clock, a function g<2> calculator, a pulse generator having recurrent frequency of f(k+1)/k, a pulse recurrent frequency doubler, a ring counter up to k, an adder-accumulator of elements of Abelian group, a key, a ring counter up to (2k+1), an AND component, a main memory unit, a key, a trigger, a main memory unit and a ring counter up to (k+1).

Abstract: A system and method to improve signal quality by including a weighted signal average in computations that calculate a regenerated signal's sampling values is presented. Secondary signal lobe values are removed from an original signal during signal re-sampling computations in order to minimize signal re-sampling memory requirements. A weighed signal average is included in signal re-sampling computations in order improve signal quality that was degraded due to the removal of the secondary signal lobe values. Weighted signal averages are calculated using error function values that are included in an error function. Each error function value corresponds to the distance between sample points of an original signal and the regenerated signal. The error function value is combined with the original signal's average signal value to produce a weighed signal average.

Abstract: The invention concerns a method and apparatus for performing packet loss or Frame Erasure Concealment (FEC) for a speech coder that does not have a built-in or standard FEC process. A receiver with a decoder receives encoded frames of compressed speech information transmitted from an encoder. A lost frame detector at the receiver determines if an encoded frame has been lost or corrupted in transmission, or erased. If the encoded frame is not erased, the encoded frame is decoded by a decoder and a temporary memory is updated with the decoder's output. A predetermined delay period is applied and the audio frame is then output. If the lost frame detector determines that the encoded frame is erased, a FEC module applies a frame concealment process to the signal. The FEC processing produces natural sounding synthetic speech for the erased frames.

Abstract: Adjacent blocks are identified in an image. Coding parameters for the adjacent blocks are identified. Deblock filtering between the identified adjacent blocks is skipped if the coding parameters for the identified adjacent blocks are similar and not skipped if the coding parameters for the identified adjacent blocks are substantially different.

Abstract: Disclosed is a turbo channel encoding and decoding device for a CDMA communication system. When the input data frames are very short, the device assembles input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding and decoding, the frames are reassembled into the original input frames.

Abstract: A first stage inner code decoder performs a first error correction process for a plurality of inner code words. A first stage outer code decoder performs a second error correction process for a plurality of outer code words. A second stage inner code decoder performs a third error correction process for one or more inner code words whose number of errors has been decreased by the second error correction process and skips the third error correction process for one or more inner code words whose number of errors has not been decreased by the second error correcting process.

Abstract: A turbo channel encoding/decoding device for a CDMA communication system. The device segments an input frame into multiple sub frames of an appropriate length when the input data frame is very long, and then encodes and decodes the sub frames. Otherwise, when the input data frames are very short, the device composes input frames into one super frame of an appropriate length and then encodes and decodes the super frame. After frame encoding/decoding, the frames are recomposed into the original input frames.

Abstract: An encoder for enabling selection of output bits that reduce run-length includes classification circuitry, a disparity control circuit, encoding circuitry, and a run-length control circuit. The classification circuitry is configured to receive data in a first bitwidth. An output of the classification circuitry is in communication with the disparity control circuit. The encoding circuitry is configured to encode the data received in the first bitwidth into a second bitwidth. The run-length control circuit is included in the encoding circuit and is selectively triggered in one coding scheme when a contiguous portion of the data of the first bitwidth is of a particular sequence, e.g., all logic ones, to generate a control signal. The run-length control circuit receives as additional inputs outputs of a portion of the encoding circuitry and a disparity signal from the current encoding cycle. The control signal, when generated, reduces run-length of the second bitwidth.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: Broadly speaking, a method and corresponding apparatus is provided for controlling a data output rate of an electronic device. More specifically, the method and corresponding apparatus enables an equivalent data output rate to be obtained from each of an ASIC and an FPGA prototype of the ASIC while maintaining equivalent logic between the ASIC and the FPGA prototype. A validity bit is attached to each output data signal in accordance with each cycle of a clock signal. The validity bit provides an indication as to whether the associated data signal should be processed (i.e., transmitted as output) normally. Only valid output data signals as identified by their validity bit value are transmitted. Thus, the validity bit values associated with successive data signals can be defined to generate a particular data output rate.

Abstract: A picture-encoding apparatus provided by the present invention includes a wavelet transformation unit for carrying out wavelet transformation on an input picture to generate wavelet-transformation coefficients, a bit-plane encoding-pass-generating unit for spreading the wavelet-transformation coefficients over bit-planes, an arithmetic encoding unit for carrying out an arithmetic encoding process in an encoding pass, a rate control unit for controlling an encoded-data quantity of the generated arithmetic code so as to achieve a target encoded-data quantity, a header-generating unit for generating a header, a packet-generating unit for generating a packet by addition of the header to the arithmetic code experiencing control of the encoded-data quantity executed by the rate control unit, and an encoded-code-stream-truncating means for truncating an encoded-code stream completing processing through all the encoding passes by discarding a rear portion of the stream so as to make an encoded-data quantity of the st

Abstract: A limited value range is defined for obtaining approximated integer cosine transform coefficients. The transform coefficients of the base vectors for the submatrices are selected by taking into account the orthogonality condition so that the sum of their squares yields the square of the constant component coefficient. The coefficients of the variable components are derived from these coefficients. These measures yield the advantage that in quantization and normalization, a uniform normalization and quantization factor may be used for all coefficients.

Abstract: A method for processing a chain reaction codes includes first selecting a source symbol which is associated an output symbol of degree two or higher (i.e., an output symbol which is itself associated with two or more input symbols), and subsequently deactivating the selected source symbol in an attempt to produce an output symbol of degree one. The inactivation process can be repeated either successively until an output symbol of degree one is identified, and/or whenever the decoding process is unable to locate an output symbol of degree one.

Abstract: Techniques for reliable transmission of higher priority data within a frame are disclosed. In one aspect, an inner code is applied to one or more partial segments of a transmitted data frame in addition to any outer code applied to the entire frame. In another aspect, inner coded segments of a received frame are decoded when decoding of the outer code indicates one or more errors within the frame. The inner coded segment is retained when the inner decoding decodes without error. Various other aspects are also disclosed. These aspects have the benefits of reducing the number of retransmissions of higher priority data, as well as reducing delay for time-sensitive segments of the frame. The result is more efficient use of bandwidth, more responsiveness to higher priority segments, such as signaling traffic, and capacity, power, and other efficiencies associated therewith.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: An architecture for a turbo decoder performs a faster max* computation. In this architecture, one or more lookup tables begin processing a digital signal prior to the most significant bit of the digital signal stabilizes. This technique allows processing in the lookup table to be accomplished during a period of time in which processing could not be accomplished previously. As a result, the architecture performs the max* computations at a faster rate than previous architectures.

Abstract: A method and apparatus of converting a series of data words into modulated signals generates for each data word, a number of intermediate sequences by combining mutually different digital words with that data word, scrambles the intermediate sequences to form alternative sequences, translates each alternative sequence into a (d,k) constrained sequence, measures for each (d,k) constrained sequence, not only an inclusion rate of undesired sub-sequence but also a running DSV (Digital Sum Value), and selects one (d,k) constrained sequence having small inclusion rate for recording on an optical or magneto-optical recording medium among the (d,k) constrained sequences having maximum value of running DSV. smaller than a preset limit. Accordingly, efficient DSV control can be achieved for even relatively-long sequences.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: An A/D converter includes a calibration apparatus handling occurrences of thermometer code bubbles in an A/D sub-converter in at least one A/D converter stage. The calibration apparatus includes means (30) for detecting two A/D sub-converter comparators causing a bubble, means (32, 34, 36) for increasing the threshold of the bubble causing comparator having the lowest threshold by a first predetermined voltage and means (32, 34, 36) for decreasing the threshold of the bubble causing comparator having the highest threshold by a second predetermined voltage.

Abstract: A method for correcting an analog signal to target levels is provided. Firstly, the analog signal is periodically sampled to obtain a plurality of sampled points. Then, levels of the sampled points are compared with a threshold value to find a set of sequentially sampled points including a head and a tail ones, each having a first comparing result with the threshold value, and the other intermediate ones, each having a second comparing result with the threshold value. Then, one of the set of sequentially sampled points, which has the second comparing result with the threshold value, is adjusted to one of the target levels. A device for correcting an analog signal to target levels is also provided.

Abstract: A communication system comprises a transmitting apparatus and receiving apparatus for transmitting/receiving a N-ary signal, based on a prime number exceeding 2, inclusive of an efficient error correction system. The transmitting apparatus includes a binary to N-ary converting unit for converting a binary transmit signal into an N-ary signal, as an information sequence, where the N of the N-ary number is a prime number exceeding 2, an encoding unit for generating a transmit sequence, comprised of BCH code on a Galois field with the number of elements being a prime number exceeding 2, and a multi-level modulating unit for multi-level modulating the transmit sequence and for transmitting the multi-level modulated transmit sequence to a receiving apparatus.

Abstract: Encoded data is decoded by a receiver for an analogue input signal that is converted into a digital signal. A detector produces a sequence of data representative of the analogue signal, a decoder for the sequence of data outputs data indicating that a sequence includes an error. An event detector detects an event which substantially alters or destroys the analogue input signal. The decoder outputs data corresponding to the or each sequence resulting from the altered or destroyed analogue input signal indicating that the sequence is incorrect.

Abstract: A speech decoder 10 comprises a decoding processing portion 11 and an amplification process control portion 12. Here, the decoding processing potion 11 is a device for decoding a received coded speech signal (bitstream) BS and outputting a decoded speech signal SP. Additionally, the amplification process control portion 12 monitors the state of occurrence of frame errors in the coded speech signal BS, and when the number of successive frame errors exceeds a predetermined reference frame error number, outputs amplification instructions for a predetermined number of frames after the successive frame errors disappear. As a result, instead of codebook data DCB obtained by a decoding process of the decoding processing portion 11, amplified codebook data DACB are supplied to a synthesis filter portion 17, and is written into the codebook decoder 18 of the decoding processing portion 11 as new original codebook data DCBO.

Abstract: A communications system, having a combination Reed-Solomon encoder and a Turbo-Code encoder Data frame configuration which may be changed to accommodate embedded submarkers of known value are embedded in with the data order to aid synchronization in the receiver system, by providing strings of known symbols. The string of known symbols may be the same as the symbols within a training header that appears at the beginning of a data frame. Frame parameters may be tailored to individual users and may be controlled by information pertaining to receivers, such as bit error rate, of the receiver. Additional headers may be interspersed within the data in order to assist in receiver synchronization. Frames of data may be acquired quickly by a receiver by having a string of symbols representing the phase offset between successive header symbols in the header training sequence in order to determine the carrier offset.

Abstract: A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n−1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n−1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

Abstract: A dummy bit elimination device in a coding apparatus for use in a submarine cable system. The dummy bit elimination device has a converter for eliminating only dummy bits from FEC (Forward Error Correction) code. The coding apparatus has an optical-to-electrical signal transducer, a demultiplexer, a coder for generating an FEC code, a multiplexer for multiplexing inputs, and an electrical-to-optical signal transducer. The dummy bit elimination device is inserted between the coder and the multiplexer so that the outputs of the coder are fed to the converter and an outputs of the converter are fed to the multiplexer.

Abstract: An optical transmission system and optical transmission devices in the optical transmission system that can achieve a high quality transmission using considerably simple arrangements are disclosed. At a transmitting-end optical transmission device, encoding means having n outputs, forms k data by aligning phases of data on k channels with each other and for generating (n−k) error correction bits for said k data and adding said (n−k) error correction bits to said k data, and wavelength-multiplexing means connected to the encoding means, converts both said k data and said (n−k) error correction bits ton optical signals having different wavelengths and for wavelength-multiplexing said n optical signals so as to be delivered to the optical transmission line.

Abstract: A circuit and method for protecting the minimum run length in RLL code is disclosed. The circuit comprises three state processors, each having a plurality of registers, including a decision bit, an invalid bit, metric bits and path bit array, and changing state at the zero crossing point (Turning) of an RF signal, before the zero crossing point (Before) and after the zero crossing point (After). A metric computing unit is used to calculate the metrics at the points of turning, before and after corresponding to the EFM (Eight-Fourteen Modulation) signal. A timing unit is used to generate control signals to the state processors and metric computing unit according to the EFM signal. Then the protecting circuit comprises a computing unit to control the decision bit, the invalid bit, the metric bits and path bit array and generates correct output signals according to the control signals and the metrics.

Abstract: A variable length coding (VLC) method and a variable length coding apparatus for producing variable length coding having a reduced number of arithmetic cycles. The method includes carrying out (a) performing a VLC process and assigning a code to a combination of (Last, Run, Level), (b) subtracting LMAX as the maximum Level corresponding to (Last, Run) from Level to calculate amended Level and thereafter assigning a code to a combination of (Last, Run, amended Level), (c) subtracting a value that is obtained by adding 1 and RMAX as the maximum Run corresponding to (Last, Level) from Run to calculate amended Run and thereafter assigning a code to a combination of (Last, amended Run, Level), and (d) of performing faxed length coding (FLC) assignment in parallel with each other, and includes (e) selecting the code according to predetermined priorities.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: A method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.

Abstract: Encoding/decoding systems and methods for use with data signals representing speech, audio, video, and/or other types of information, including, but not limited, to EKG, surround sound, seismic signals, and others. These systems and methods encode signal parameters into a plurality of frames, each frame having a predetermined number of bits. The encoder encodes signals into frames that are of longer duration than a transmission (or storage) interval, except in cases where signals may be characterized by an axis other than time, such as image or video-coded signals, wherein the encoder codes signals into frames that are larger than the coded segment. When no bits are lost during data transmission (or storage), the decoder uses the received (or retrieved) bits to reconstruct segments having a length equal to the transmission (or storage) interval.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and-block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: In a puncturing section 102, input memory 201 temporarily stores data inputted to the puncturing section 102, a controller 202 distinguishes data to be added, a switch 203 selects data to be added in accordance with control of the controller 202, an adder 204 adds data (namely, data subjected to repetition by a transmitter side) selected by the switch 203, and output memory 205 temporarily stores data outputted from the puncturing section 102.

Abstract: Digital code words are transmitted via a digital communication network, e.g. from a digital modem (1) to an analog modem (5). Whenever an RBS technique is used for an RBS channel, a given bit, as a rule the LSB, of a corresponding code word is changed. In order to recognize and correct such RBS channels, training code words transmitted during a training phase are evaluated. If an RBS channel is detected, the given bit of the corresponding code word is set to a fixed value.

Abstract: The invention relates to method of encoding address words (a) comprising address symbols (a0, a1, . . . , ak−1) into codewords (c) of a code (C) for providing an enhanced error correction capability if at least one information symbol (m1) of information words (m) is known a priori to a decoder decoding received, possibly mutilated codewords (r). The invention relates further to a method of decoding possibly mutilated codewords (r).

Abstract: In a method for compressing data, in which, in a data stream composed of characters, character strings are checked for correlation with other character strings that are present at a given distance in the data stream, and in which, in each case, the number of correlating characters and the position of the correlating characters within the respective other character string constitute the compressed data, at least one character is allowed to differ in the correlation check and data for correcting the at least one differing character is inserted into the compressed data.

Abstract: A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

Abstract: A memory tester including an algorithmic pattern generator (ALPG) for generating a test pattern as a digital signal based on vector data is provided with a digital-to-analog converter built in the memory tester or provided outside the memory tester. Thus, the function of a device under test (DUT) having the analog-to-digital converting function can be verified. In other words, an address signal included in the test pattern generated in the ALPG is used for generating an analog signal to be input to the DUT having the analog-to-digital converting function, not for address designation. A control unit compares an output digital signal generated in the DUT with the address signal generated in the ALPG as a test digital signal to detect the degree of agreement between these signals, thereby verifying the analog-to-digital converting function of the DUT.

Abstract: The present invention is to provide an average bubble correction circuit which will expand the range of bubble error correction and will detect the proper position of the 1/0 state-conversion points of the thermometer codes to low down the error rate that caused by the ROM decoding. The average bubble correction circuit is used in the analog to digital converter and will convert the thermometer code obtained from the comparator of the analog to digital converter into the 1/0 state-conversion point.

Abstract: A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than l and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits.

Abstract: A first codec-based warning message generator 151 generates a warning message by a first. A first codec-based silent fixed pattern generator 152 generates a first codec-based silent fixed pattern. A second codec encode block 154 encodes an input signal by a second codec. A code string generator 155 generates a synthetic code string by synthesizing outputs from the above components in an encoding frame having a predetermined length being a unit of encoding.

Abstract: Encoding/decoding systems and methods for use with data signals representing speech, audio, video, and/or other types of information, including, but not limited, to EKG, surround sound, seismic signals, and others. These systems and methods encode signal parameters into a plurality of frames, each frame having a predetermined number of bits. The encoder encodes signals into frames that are of longer duration than a transmission (or storage) interval, except in cases where signals may be characterized by an axis other than time, such as image or video-coded signals, wherein the encoder codes signals into frames that are larger than the coded segment. When no bits are lost during data transmission (or storage), the decoder uses the received (or retrieved) bits to reconstruct segments having a length equal to the transmission (or storage) interval.

Abstract: A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

Abstract: In carrying out PWM-recording on optical disks, RESYNC BYTES including a bit compensation part, RESYNC detection part, and bit synchronization part are periodically inserted in the recorded data code stream. After encoding and at the time of decoding, RESYNC BYTES are detected by detection of the RESYNC detection part. The decoder is initialized by detecting the position of the bit synchronization part and decoding is performed satisfactorily free from error. With this configuration, even for synchronization bytes having a comparatively long portion of consecutive code values, bit resynchronization is enabled free from mis-detection caused by peak shift. Even with the recording and reproducing characteristics with an un-symmetrical unerased area of the mark and space parts, the RESYNC detection part is fixed to either mark or space and RESYNC BYTES with little influence on an unerased area can be realized.