Abstract: A MIMO communication method for performing MIMO communication between a base station including a plurality of antennas, and a plurality of terminals accommodated in the base station. The method includes, in the base station, dividing the plurality of terminals into a first and a second group, and assigning orthogonal codes with each other to the respective groups, spreading transmission data to the plurality of terminals with the assigned codes, multiplying data obtained by the spreading by a predetermined pre-coding matrix, obtaining a channel matrix representing channels between the plurality of antennas and the plurality of terminals, multiplying data obtained by the multiplying by the pre-coding matrix by a complex conjugate matrix of the channel matrix, and transmitting data obtained by the multiplying by the complex conjugate matrix from the plurality of antennas.

Abstract: The device provides a resistive memory device for storing elements of hyper-dimensional vectors, in particular digital hyper-dimensional, as conductive statuses in components in particular in 2D-memristors, of the resistive memory device, wherein the resistive memory device provides a first crossbar array of the components, wherein the components are memristive 2D components addressable by word-lines and bit-lines, and a peripheral circuit connected to the word-lines and bit-lines and adapted for encoding operations by activating the word-lines and bit-lines sequentially in a predefined manner.

Abstract: A MIMO communication method for performing MIMO communication between a base station including a plurality of antennas, and a plurality of terminals accommodated in the base station. The method includes, in the base station, dividing the plurality of terminals into a first and a second group, and assigning orthogonal codes with each other to the respective groups, spreading transmission data to the plurality of terminals with the assigned codes, multiplying data obtained by the spreading by a predetermined pre-coding matrix, obtaining a channel matrix representing channels between the plurality of antennas and the plurality of terminals, multiplying data obtained by the multiplying by the pre-coding matrix by a complex conjugate matrix of the channel matrix, and transmitting data obtained by the multiplying by the complex conjugate matrix from the plurality of antennas.

Abstract: A MIMO communication method for performing MIMO communication between a base station including a plurality of antennas, and a plurality of terminals accommodated in the base station. The method includes, in the base station, dividing the plurality of terminals into a first and a second group, and assigning orthogonal codes with each other to the respective groups, spreading transmission data to the plurality of terminals with the assigned codes, multiplying data obtained by the spreading by a predetermined pre-coding matrix, obtaining a channel matrix representing channels between the plurality of antennas and the plurality of terminals, multiplying data obtained by the multiplying by the pre-coding matrix by a complex conjugate matrix of the channel matrix, and transmitting data obtained by the multiplying by the complex conjugate matrix from the plurality of antennas.

Abstract: Method and system for partially cloning a data container with compression is provided. A storage operating system determines if a portion of a source data container that is to be cloned includes a plurality of compressed blocks that are compressed using a non-variable compression group size. The operating system clones the plurality compressed blocks with the non-variable compression group size and de-compresses a plurality of blocks of the data container that are not within the non-variable compression group size. The plurality of compressed blocks and the plurality of blocks that are not within the non-variable compression group size are then stored as a partially cloned copy of the source data container.

Abstract: The present invention relates to data manipulation and in particular incrementing, decrementing and comparing binary coded numbers, notably the manipulation of thermometer codes and the performance of arithmetic operations thereon. A method of processing data is provides which comprises receiving a series of data samples, each sample being represented as an N-bit thermometer code, wherein the most significant bit thereof represents the sign of the data sample value Y(n) and the remaining N?1 bits represent the magnitude of the data sample and executing a predetermined sequence of arithmetic operations directly on the series of N-bit thermometer code data samples to determine one of two values for each data sample, without any recoding of the thermometer code data samples.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: An apparatus and a method for enhancing digital processing implementation using non-power-of-two even count Gray coding are disclosed. The even count encoding device includes a first circuit, a second circuit, and a coding circuit. The first circuit, in one embodiment, is configured to identify a first portion of entries in a table in response to an input number. The second circuit is capable of determining a second portion of entries in the table in response to the input number, wherein the number of the first portion of entries and the number of the second portion of the entries are substantially the same. The coding circuit is operable to concatenate the second portion of the entries to the first portion of the entries to form an output table, which includes a sequence of even count integers wherein the difference between two adjacent integers is one bit position.

Abstract: High speed, low power all CMOS thermometer-to-binary demultiplexer. A received signal undergoes digital sampling (e.g., as within an ADC) to generate a signal that subsequently undergoes encoding (e.g., transformation from thermometer encoded data to binary encoded data) and de-multiplexing. Two separate de-multiplexing stages are employed when performing combined encoding and de-multiplexing. In addition, the individual DEMUXs of the two stages are clocked using a distributed clock generation architecture, such that, reset and time-interleaving is controlled on the ADC clock generator. The thermometer-to-binary encoders are placed very close to the input stage which facilitates very fast data rates while consuming relatively lower power.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract: High speed, low power all CMOS thermometer-to-binary demultiplexer. A received signal undergoes digital sampling (e.g., as within an ADC) to generate a signal that subsequently undergoes encoding (e.g., transformation from thermometer encoded data to binary encoded data) and de-multiplexing. Two separate de-multiplexing stages are employed when performing combined encoding and de-multiplexing. In addition, the individual DEMUXs of the two stages are clocked using a distributed clock generation architecture, such that, reset and time-interleaving is controlled on the ADC clock generator. The thermometer-to-binary encoders are placed very close to the input stage which facilitates very fast data rates while consuming relatively lower power.

Abstract: High speed, low power all CMOS thermometer-to-binary demultiplexer. A received signal undergoes digital sampling (e.g., as within an ADC) to generate a signal that subsequently undergoes encoding (e.g., transformation from thermometer encoded data to binary encoded data) and de-multiplexing. Two separate de-multiplexing stages are employed when performing combined encoding and de-multiplexing. In addition, the individual DEMUXs of the two stages are clocked using a distributed clock generation architecture, such that, reset and time-interleaving is controlled on the ADC clock generator. The thermometer-to-binary encoders are placed very close to the input stage which facilitates very fast data rates while consuming relatively lower power.

Abstract: Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2?L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2?L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.

Abstract: Various embodiments of the present invention include methods for determining nanowire addressing schemes and include microscale/nanoscale electronic devices that incorporate the nanowire addressing schemes for reliably addressing nanowire-junctions within nanowire crossbars. The addressing schemes allow for change in the resistance state, or other physical or electronic state, of a selected nanowire-crossbar junction without changing the resistance state, or other physical or electronic state, of the remaining nanowire-crossbar junctions, and without destruction of either the selected nanowire-crossbar junction or the remaining, non-selected nanowire-crossbar junctions. Additional embodiments of the present invention include nanoscale memory arrays and other nanoscale electronic devices that incorporate the nanowire-addressing-scheme embodiments of the present invention.

Abstract: Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address.

Abstract: A radio transmitter system designed using an FSK modulator with IQ up-mixers and sinewave coded digital-to-analog converters (DACs). The radio transmitter system may include a frequency shift keying (FSK) coding logic circuit coupled to the inputs of an IQ modulation and image reject up-mixer through a respective DAC and a respective low pass filter (LPF) for each the I and the Q channels. The FSK modulation scheme may employ sine and cosine signals for the I and Q channels, respectively, where the sine and cosine waves are directly coded into the DACs. The coded levels required by the DACs may be generated using current sources and may be Gray-coded. The output of the IQ modulation and image reject up-mixer may be connected to a power amplifier, which may be used to transmit the modulated RF signal via a loop antenna.

Abstract: A Gray code decoder for decoding input numbers includes a first select circuit that selects an M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J. A second select circuit selects an N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N. A concatenate circuit concatenates the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number.

Abstract: The invention relates to an arrangement for converting a binary input signal corresponding to an n-bit thermometer code into a binary output code different therefrom, having a first number of OR gate circuits, into the inputs of which bits of the thermometer code can be coupled, having a first adder, which is connected downstream of the OR gate circuits and into the inputs of which the output signals of the OR gate circuits can be coupled and which provides at least one binary output signal for the output code at its outputs, having a second number of multiplexer circuits, into the inputs of which bits of the thermometer code can be coupled and into the multiplexer selection terminals of which the output signals of the first adder can be coupled, having a second adder, which is connected downstream of the multiplexer circuits and into the inputs of which the output signals of the multiplexer circuits can be coupled and which provides at least one further binary output signal for the output code at its outp

Abstract: In general, in one aspect, the invention features a Gray code decoder for decoding input numbers according to a K-bit Gray code and a Gray code encoder for encoding input numbers according to the K-bit Gray code. The K-bit Gray code is constructed from a M-bit Gray code having a one-bit separation I and a two-bit separation J and a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N.

Abstract: A method and computer program for generating a K-bit Gray code comprises (a) selecting a M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J; (b) selecting a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N; (c) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number; (d) generating the next 2N?1 sequential K-bit Gray code numbers, comprising (e) selecting a next M-bit Gray code number from the M-bit Gray code, (f) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a next K-bit Gray code number, and (g) repeating steps (e) and (f); (h) selecting a next N-bit Gray code number from the N-bit Gray code; and (i) repeating steps (c) through (h).

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A code word generator for OVSF codes, comprising an intermediate memory device (16) which is used to input a calculation index as a binary calculation index data word, a calculation device (17) which permutes the significant data bits of the calculation index data word bit-by-bit so that a calculation basis (B) can be generated, a counter (21) for producing a counting variable (Z) and provided with a logic circuit comprising several AND gates for bit-by-bit linkage of the counting variables (Z) generated with the calculation basis (B) in order to form a linking data word and several XOR gates for logical reduction of the linking data word to form code word data bits of the OVSF code word.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.

Abstract: In this invention, a new tree-structured generation method for obtaining orthogonal variable spreading factor (OVSF) codes that preserve orthogonality between different rates and spreading factors (SF) based on Gray code labels in a CDMA system is presented. Each OVSF code is uniquely associated with a Gray code label. An efficient method for deciding if the code is a mother code or children code of the other code without searching an entire code tree is proposed. Furthermore, by taking advantage of the Gray code labeling, each OVSF code can be generated directly from a generating matrix instead of being generated recursively using a tree structure. An OVSF code reassignment method with Gray code labeling is also given.

Abstract: A method and a device for high-speed scale conversion wherein a value N within a range of N1 and N2 is converted into a small value M within a range of M1 and M2. The method includes the step of obtaining an approximate value of M by loading the value (N−N1+2p−1) into a multi-bit shift register and right-shifting p bits. A binary search process is then used to determine the error value between the actual value of M and the approximate value of M. By avoiding actual multiplication processes, the conversion can be carried out using low-cost electronic hardware such as a microprocessor or a PROM to carry out the binary search process, a shift-register to obtain the approximate value of M, a multiplexer to receive an analog input data N and an A/D converter to convert the analog input data N into a digital data N.

Abstract: Methods and apparatus for spreading and concentrating information are taught. The present invention relates to constant-weight encoding of data words on a parallel data line bus while allowing communication of information across sub-word paths.

Abstract: A thermometer code converter for converting weightless binary tuples of 2 or higher dimensional arrays into a thermometer or aggregate code comprises a series of layers (16, 18) each made up of bit manipulation cells (10) which collectively cause set bits to be shifted towards a required bit position. The bit manipulation cells are made up of logic elements (12, 14) and the entire converter may be asynchronous. Also disclosed is a sum and threshold device which employs a thermometer code converter and a bit selector device.

Abstract: An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

Abstract: Four parallel lines are provided for the guided transmission of a data flow with a high rate (sub-GHz range). Two data bits per transmission clock are transmitted via these lines. The other two remaining lines are used for signaling certain changes in both data bits. Data transmission and signaling are accomplished on the basis of the Grey code. In other words, only one of the four lines changes state per clock. The interface according to the invention has reduced sensitivity to signal skew and permits simple clock recovery in terms of circuit engineering.

Abstract: A decoding compensation circuit, which compensates for missing pulses when decoding the gray code written in a magnetic disk of a hard disk drive (HDD) includes: a central processing unit (CPU) for controlling the hard disk drive, a positive pulse detection window generator for generating a positive pulse detection window signal, a digital servo data generator for generating a digital servo data, a gray code detection window generator for generating a gray code detection window signal, a first logic gate circuit for logically processing the positive pulse detection window signal, digital servo data and gray code detection window signal so as to produce positive and negative pulse gray codes, a gray sync/data separation circuit for separating gray data and gray sync from the positive and negative pulse gray codes, a second logic gate circuit for logically processing the positive and negative gray data and sync to compensate for missing gray data and sync, a gray sync decision circuit for detecting the gray syn

Abstract: A coding scheme for coding information having a nonuniform probability distribution function. According to exemplary embodiments, a code word is assigned to the information corresponding to the peak level of the probability density function, and is referred to as the kernel. New code words having a Hamming distance of 1 to the kernel are then assigned to information adjacent to the peak level of the probability density function. The new code words are arranged around the kernel in as compact a manner as possible. If there are forbidden code words, the kernel is selected appropriately and the forbidden words are omitted from the resulting code table.

Abstract: The address of each track in a disk drive system is expressed in Gray code, and an appended bit of information is added to the Gray code, associated with the least significant bits thereof, the value of which is determined by the values of the most significant bits of the Gray code. The value of this appended bit is the same from Gray code to successive Gray code, as long as there are no changes in any significant bit between successive Gray codes, but the appended bit changes value when there is a change in a most significant bit between successive Gray codes.

Abstract: A bar graph decoder includes input terminals to which 5-bit digital data is input, a logic circuit for outputting a thermometer code changing continuously at a constant ratio in response to the input data, and output terminals connected to the logic circuit for outputting switch select signals according to the digital input. The logic circuit is configured only of 2-input OR circuits and 2-input AND circuits. As a result, a bar graph decoder having a simple configuration and a reduced number of elements can be provided.

Abstract: Apparatus for generating an output signal in response to the change in state of any one of a plurality of input signals. The apparatus includes decoding means for each possible combination of input signals, and by an appropriate arrangement of these decoding means, ensures that any change in input signal status causes an output signal to be generated by the arrangement of decoding means. The decoding means includes first and second arrays 10,12, each comprising a matrix of MOS FET's; the FET's 30.sub.ij of the first array 10 are p-channel devices and the FET's 32.sub.ij of the second array 12 are n-channel devices. The matrix of each array is a paralleled configuration of series-connected branches of FET's functioning as decoders. The branches of each array decode input signal combinations of minimum distance two from one another. Arrays 10 and 12 are interconnected in such a manner that they draw no dc current (other than device leakage current).

Abstract: A digital counting circuit, including a binary counter supplying output sals to an adjacent code encoder that processes the received signals and transmits its output to a binary decoder. The encoder has a plurality of D-type flip-flop devices to which selected outputs of the binary counter are connected. The circuit operates so that only one input change to the binary decoder is permitted for each change of count from the binary counter. This prevents any erroneous counts from momentarily appearing on the output lines of the binary decoder.

Abstract: A binary encoding method notably but not exclusively for the encoding of data elements designed to be represented sequentially, according to a preestablished order, for example in counters, inducing a uniform or substantially uniform mean changing rate for each of the binary elements, the data elements being encoded on two distinct fields of binary elements, a reference field and a permutation field, and the sequence of binary elements assigned to the permutation field undergoing a permutation as a function of the value contained in the reference field.

Abstract: A high speed, synchronous counter which counts using a Gray code, Because Gray code counting has the unique property that only a single bit of the counter changes with each new count, the output of the counter may be latched at any time and the latched value will never be more than one count away from the actual count value in the counter. The present invention provides a look-ahead qualification bit that provides for an eight count look-ahead. With this eight count look-ahead capability, the qualification inputs to the high order bits can be created through a series of AND gates, each having only two inputs, thus saving significatnt power and space. Because most digital circuits require the output of a counter to be in binary code, the invention provides a conversion means for converting the Gray code input to a binary output.

Abstract: A method and apparatus for correcting errors in a thermometer code data array (32). A parallel A/D converter (22) comprises an array (26) of comparators and an encoder (30). The correction of errors in the data array (32) produced by the comparators (26) is accomplished by an array (24) of majority error correction gates which is placed between the array (26) of comparators and the encoder (30) in the A/D converter (22).

Abstract: A method and circuit arrangement is disclosed for converting Gray code signals into counting pulses, forming a counter status, detecting interference signals infringing the Gray code and for forming an error signal with a network defining a finite automaton according to Moore or Mealy, wherein the network forms no error signal when a Gray code infringement is followed by a second Gray code infringement. The disclosed network arrangement in one embodiment comprises a quadruple interpolator (quadrature decoder) for precision dimension measuring machines with optoelectronic scale scanning. Interruptions of the measuring procedure and errors are reduced by not generating an error signal when a Gray code infringement is followed by a second Gray code infringement.

Abstract: A modified quasi-Gray encoding technique for use in parallel analog-to-digital converters that significantly reduces errors resulting from multiple simultaneous inputs. The encoding technique converts a one-in-(2.sup.n -1) digital code into an n-bit binary word that is the same as quasi-Gray code in all but its least significant bit position, which alternates in the same manner as standard binary code. For many multiple simultaneous inputs, the modified quasi-Gray code substantially reduces errors when compared with quasi-Gray code. For example, the modified quasi-Gray code reduces the maximum error from 3 to 2 for two simultaneous inputs separated by two bit positions (n=8). In a typical parallel analog-to-digital converter employing the modified quasi-Gray code, the one-in-(2.sup.n -1) digital code is converted into modified quasi-Gray code using a read-only memory.

Abstract: A parallel type A/D converter includes circuitry for generating plural reference voltages, comparators for comparing the plural reference voltages with an input voltage, logic circuits for logically processing the outputs of comparators, and an encoder circuit for encoding the outputs from the logic circuits. A pair of logic outputs are obtained by a first logic circuit chain for receiving as inputs the outputs of a comparator of number i and of a comparator i+2. Conversion errors are reduced by properly processing this pair of logic outputs in a second logic circuit, or by composing an encoder circuit for receiving the pair of logic outputs as inputs.

Abstract: A single-step digital-to-analog converter includes a multiplicity of individual interconnected sources disposed in a matrix having matrix rows and matrix columns; a decoder apparatus connected to the matrix for addressing the individual sources, the decoder apparatus including a column decoder for addressing at least the more significant part of an n-bit-wide digital word to be converted and a row decoder in the form of a thermometer decoder.Logic apparatus is connected between the decoder apparatus and the matrix for determining the matrix column of one of the individual sources being addressed and for suppressing switching over of the individual sources of others of the columns. The logic apparatus includes first and second logic devices, the first logic device being connected between the column decoder and the matrix for deriving further column information (E.sub.i) and additional information (S.sub.i) from column information (X.sub.i) in accordance with the logical equations: E.sub.i =S.sub.i and S.sub.

Abstract: Employed is a thermometer-code-to-one-of-n converter having a number of similar portions each of which includes gates each configured to detect a zero-zero-one pattern and to develop a one-of-n signal, gates each configured to detect a one-zero-zero pattern (an invalid pattern) and to develop an error signal, gates configured to combine the error signals, and gates configured to gate the error signals with the one-of-n pattern signals to block (inhibit) one-of-n signals.

Abstract: An integrated individual listening device and decoder for receiving an audio signal including a decoder for decoding the audio signal by separating the audio signal into a voice signal and a background signal, a first end-user adjustable amplifier coupled to the voice signal and amplifying the voice signal; a second end-user adjustable amplifier coupled to the background signal and amplifying the background signal; a summing amplifier coupled to outputs of said first and second end-user adjustable amplifiers and outputting a total audio signal, said total signal being coupled to an individual listening device.