Abstract: Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Abstract: Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, an asynchronous FIFO. Data is received at a write side receiving circuitry residing in a write-side clock domain of the FIFO and stored at a memory location in a data storage buffer having a plurality of locations. Each memory location in the data storage buffer has a binary pointer value corresponding to the respective location. The binary pointer value is converted to a corresponding Gray code symbol and transferred to the read side of the FIFO. At the read side the Gray code symbol is converted back to the corresponding binary pointer value. Read-side control circuitry, using the binary pointer value, transfers the data from the data storage buffer to a data output register residing in a read-side clock domain of the FIFO.

Abstract: The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

Abstract: Systems, methods, and apparatuses relating to conditional operations in a configurable spatial accelerator are described.

Abstract: The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

Abstract: The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit. The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.

Abstract: A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.

Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.

Abstract: The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuit 101 to which data of (2n+1) bits are inputted (where “n” is an integer more than 1) and which encodes 2 bits of an input signal of (2n+1) bits to a Gray code as a signal for allowing four quadrants to be identified, an encoding circuit 102 that encodes 3 bits of the input signal of (2n+1) bits as a signal indicating any one of eight subgroups provided in each of the four quadrants so that an average Hamming distance between adjacent subgroups within its quadrant becomes a minimum, and a mapping circuit 104 that maps binary data encoded by the Gray coding circuit 101 and the encoding circuit 102 on the four quadrants.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: For high resolution resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row of the resistor string are fed into a multiplexer, wherein the multiplexer produces an output voltage. A method and apparatus are disclosed for implementing the reflective nature of Gray code to design a DAC such that all the switches in a column of the resistor string may be controlled with only one control signal, thereby reducing extra routing costs, surface area, and dynamic power consumed by the circuit.

Abstract: A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.

Abstract: A method an apparatus is provided to generate a gray code sequence from a sequence of binary values having a length “L”. Accordingly, one aspect of the present invention provides a circuit comprising a cycle flag toggle circuit configured to toggle a cycle flag between a first value and a second value, an intermediate value generator coupled to an output of the cycle flag toggle circuit configured to receive the binary value, and configured to generate an intermediate value from the cycle flag and the binary value, and a binary to gray converter coupled to an output of the intermediate value generator, configured to convert the intermediate value to a gray code.

Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Abstract: Methods for generating Gray count for an odd length sequence using a virtual space. More than one set of Gray codes can be generated for a given odd multiple virtual domains that assists in achieving more robust systems which are fault tolerant. Broadly contemplated herein is the use of a simple and elegant algorithm which is less complex and uses only an N-bit sequence.

Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: Generating Gray sequences for non-standard sequence lengths to be used in cyclical sequences having L members. For binary members of the cyclical sequence having values less than L/2 an amount (C/2?L) the most significant bit is forced to a logical “1” to create intermediate binary members. For members greater than or equal to an amount (C/2?L) is added to the binary to create intermediate binaries. The intermediate binaries are then transformed to a Gray code sequence having a non-standard sequence length of L.

Abstract: With the aim of reducing noise due to a digital signal in an A-D conversion unit, the following is implemented: an input unit is provided with four A-D converters and a gray code conversion unit. An analog NMR signal corresponding to each channel is inputted to each A-D converter, and the gray code conversion unit converts a digital signal represented in binary code, outputted from the A-D converters, into a digital signal represented in gray code. A gray code-converted digital signal is transferred to an output unit through a digital signal bus. The gray code digital signal is returned to a binary digital signal by a gray code inverse conversion unit, and then the output unit transmits a binary signal, outputted from the gray code inverse conversion unit, to a signal processing unit.

Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

Abstract: A method and apparatus for detecting the position of a movable device are provided, in which an acceleration signal of the movable device is obtained and the acceleration signal is converted to a digital signal using an acceleration sensor; a high level time of the digital signal is counted, based on a predetermined frequency; the absolute displacement of the movable device is calculated by integrating the counted high level time of the digital signal twice; and the absolute displacement is converted to a binary gray code and the binary gray code is output.

Abstract: A gray scale voltage generating circuit includes a first resistor ladder circuit, connected between a high voltage power supply terminal and a low voltage power supply terminal and having nodes for outputting respective reference voltages, a second resistor ladder circuit, connected between the high voltage power supply terminal and the low voltage power supply terminal, and plural voltage follower circuits, connected between the respective nodes of the second resistor ladder circuit and the respective nodes of the first resistor ladder circuit with first resistor provided between the n/2'th node voltage and the high voltage power supply terminal and a second resistor provided between the n/2+1'th node voltage and the low voltage power supply terminal.

Abstract: Methods, systems and data structures select prioritized robust data values from a plurality of available data values formed by a plurality of data bits, each capable of exhibiting a bit value. Available data values are arranged into a gray code format, and alternate values of gray code format are selected to form a value map. An optional complementary value map may also be formed from the remaining data values. The value map is then prioritized according to bit adjacencies, wherein bit adjacencies are defined by contiguous bits within one of the data values that exhibit a common bit value. Priority may be given to data values having shortest and/or fewest bit adjacencies.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Abstract: A position of a moveable object may be encoded and indicated by a skew-tolerant Gray code on the object. Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: A generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).

Abstract: A Gray code decoder for decoding input numbers includes a first select circuit that selects an M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J. A second select circuit selects an N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N. A concatenate circuit concatenates the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number.

Abstract: Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: A cyclic reduced Gray code in n-many bits having 2k-many entries, for any natural number k, where 2(n?1)<2k<2n and n is a positive integer, is found by first constructing a 2n-many entry code in n-many bits with a reflected binary technique, and then selecting the last k-many ordered entries in the first half of the full reflected binary code, followed by the first k-many ordered entries in the second half of the full reflected binary code. These ordered 2k-many entries are a shortened cyclic reduced Gray code in n-many bits. Alternatively, the first k-many ordered entries in the first half of the full reflected binary code can be selected, followed by the last k-many ordered entries in the second half of the full reflected binary code.

Abstract: Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time. To overcome these problems, a Gray code counter according to the present invention has a consecutively counting Gray code counter that counts in increments or decrements of one, and an output value converter circuit that converts the Gray code data output from the consecutively counting Gray code counter into a Gray code corresponding to decimal counts as obtained by counting with (2 raised to a particular power minus 1) counts skipped at a time.

Abstract: In general, in one aspect, the invention features a Gray code decoder for decoding input numbers according to a K-bit Gray code and a Gray code encoder for encoding input numbers according to the K-bit Gray code. The K-bit Gray code is constructed from a M-bit Gray code having a one-bit separation I and a two-bit separation J and a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N.

Abstract: A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: A method and computer program for generating a K-bit Gray code comprises (a) selecting a M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J; (b) selecting a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N; (c) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number; (d) generating the next 2N?1 sequential K-bit Gray code numbers, comprising (e) selecting a next M-bit Gray code number from the M-bit Gray code, (f) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a next K-bit Gray code number, and (g) repeating steps (e) and (f); (h) selecting a next N-bit Gray code number from the N-bit Gray code; and (i) repeating steps (c) through (h).

Abstract: First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

Abstract: A counter arrangement comprises a plurality of counter registers and at least the same number of checksum registers being controlled by control means. The counter control means change the content of only one of the counter registers for each change in the counting sequence and comprise means to update the checksum registers, whereby the content of each checksum registers is defined by an associated function which allows recovery of the content of each counter register and a function performed on the content of all checksum registers results in a constant value to validate the checksum.