Abstract: A cyclic analog to digital converter for digitizing an output from a photoplethysmography sensor has a buffer amplifier for setting a voltage of the feedback capacitance. Additionally, digital averaging circuit is preferably provided for averaging the digital output from the cyclic analog to digital converter for the several conversions. Finally, voting logic is additionally provided for declaring the digital bits based on successive comparisons by the one or more comparators.

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

Abstract: A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern.

Abstract: An integrated circuit counter includes a segmented thermometer coding counter architecture that reaches the thermodynamic energy minimum for a forward/reverse counting operation, requiring only one write or one erase operation per count so that energy consumption can be minimized, and circuit endurance maximized.

Abstract: The present document relates to a digital counter providing counting information comprising at least a first and a second counting module, said counting modules being serially coupled forming a counting module chain; each counting module comprising at least a first and a second digital storage cell, each counting module providing module counting information comprising a width of at least two bits; the counting modules being adapted to change only one bit of said module counting information between two successive counting states; wherein the counting modules are coupled such that the start of counting of the second counting module is triggered by the first counting module if said first counting module once has passed through its possible counting states.

Abstract: Methods and apparatuses are described for performing adaptive analog-to-digital conversion and time-to-delay conversion by using signal prediction to adjust reference voltages of adjustable comparators.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.

Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: Provided are a ring buffer circuit in which a data full state and a data empty state may be correctly detected without depending on whether read and write operations are synchronous or asynchronous with each other, and a control circuit for the ring buffer circuit. The ring buffer circuit includes: a read and write memory having addresses specified by N bits; a write address counter pointer and a read address counter pointer which are provided for the read and write memory to count (N+1)-bit gray codes; and write and read address converter circuits provided to convert the (N+1)-bit gray codes output from the write and read address counter pointers into N-bit addresses which may be directly designated as write and read addresses of the read and write memory.

Abstract: A functional compression scheme involves determining a minimal entropy coloring of a characteristic graph of a random variable. Various scenarios are disclosed where the determination of the minimal entropy coloring of a characteristic graph is easy and tractable.

Abstract: An A/D conversion apparatus according to the present invention for comparing a reference signal with an analog signal, and when the reference signal matches with the analog signal, outputting a corresponding digital value, is provided, and the A/D conversion apparatus includes a gray code counter for generating the digital value from a reference clock or a reverse clock of the reference clock, and uses a gray code, in which a most significant bit to a second least significant bit of the digital value is a count value of the gray code counter and a least significant bit of the digital value is generated from the reference clock or the reverse clock thereof and defined as a least significant bit of the gray code counter.

Abstract: The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuit 101 to which data of (2n+1) bits are inputted (where “n” is an integer more than 1) and which encodes 2 bits of an input signal of (2n+1) bits to a Gray code as a signal for allowing four quadrants to be identified, an encoding circuit 102 that encodes 3 bits of the input signal of (2n+1) bits as a signal indicating any one of eight subgroups provided in each of the four quadrants so that an average Hamming distance between adjacent subgroups within its quadrant becomes a minimum, and a mapping circuit 104 that maps binary data encoded by the Gray coding circuit 101 and the encoding circuit 102 on the four quadrants.

Abstract: A projection system comprising an information processing apparatus capable of processing image data and a projector capable of performing a display process on the image data processed by the information processing apparatus, when the bit number representing the number of gradations of pixel data transmitted from the information processing apparatus to the projector is n-bit and the bit number representing the number of gradations which can be expressed by the projector is m-bit (m>n). The image processing apparatus outputs image data where m-bit pixel data is divided into k-pieces of pixel data of at most n-bits, and the projector synthesizes the k-pieces of pixel data based on a set synthesis rule to generate the m-bit pixel data in the pixel.

Abstract: Apparatuses and a method for transmitting a counter signal in an imaging system are provided. Counter states of the counter signal are Gray coded to Gray coded counter states before transmission. Every second Gray coded counter state is inverted to an inverted counter state. The Gray coded counter states inverted in every second counter state are transmitted and are decoded on receipt.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: An apparatus for processing a signal and method thereof are disclosed. Data coding and entropy coding are performed with interconnection, and grouping is used to enhance coding efficiency. The present invention includes the steps of obtaining index information and data and entropy-decoding the index information and identifying an entropy table corresponding to the entropy-decoded index information and entropy-decoding the data using the identified entropy table.

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract: A system and method for efficiently performing a pattern matching procedure includes an enrollment manager that performs an image conversion procedure for converting an initial reference image into a reference template. The image conversion procedure may include at least one of a binarization procedure and a symmetrical reduction procedure to more efficiently utilize system resources such as processing requirements and memory requirements. A verification manager may then convert an initial test image into a transformed test image for combining with the foregoing reference template to produce a correlation image. The verification manager then analyzes matching characteristics of the correlation image to determine whether the initial test image matches the initial reference image.

Abstract: Systems, methods and data structures are provided for representing robust data transmitted within a control system. The data structure includes at least two data fields identifying sub-modules and sub-modes of the control system, and optionally includes a third field for designating a primary operating mode of the control system and/or a fourth field representing a handshaking bit or value. The operating modes, sub-modes and sub-module designators are represented by values of the bits selected such that no single bit transition results in the selection of another valid operating state of the control system. As a result, single bit errors will not produce erroneous operating results. Similar concepts can be optionally applied to ensure that errors in contiguous sets of four, eight or any other number of bits do not produce valid states represented by the data structure.

Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

Abstract: The present invention relates to Gray Codes and their conversion to sign and magnitude representation. Gray codes are used in flash ADCs (analogue to digital converters), which convert an analogue waveform into a sampled binary value. This can be done via a thermometer code, and the present invention addresses the issue of the propagation of error due to an indeterminant thermometer code value. In particular the invention provides a Gray code to sign and magnitude converter arranged to produce for the bits of its output other than the sign bit the same code for the Gray codes that are the same distance from the boundary where the sign bit changes value when the Gray codes are arranged in order of their value.

Abstract: ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increase accuracy without significant increasing power consumption and size.

Abstract: An encoder circuit and A/D converter that can minimize the error of an encoder output with respect to all the possible combinations of thermometer codes are desired to be provided. To this end, an encoder circuit has a logic thereof configured to take a thermometer code as an input and to output as an encoded value a center value of a range in which one or more encoded values are distributed, the one or more encoded values corresponding to positions of one or more boundaries between “0” and “1” appearing in the thermometer code.

Abstract: A gray scale voltage generating circuit includes a first resistor ladder circuit, connected between a high voltage power supply terminal and a low voltage power supply terminal and having nodes for outputting respective reference voltages, a second resistor ladder circuit, connected between the high voltage power supply terminal and the low voltage power supply terminal, and plural voltage follower circuits, connected between the respective nodes of the second resistor ladder circuit and the respective nodes of the first resistor ladder circuit with first resistor provided between the n/2'th node voltage and the high voltage power supply terminal and a second resistor provided between the n/2+1'th node voltage and the low voltage power supply terminal.

Abstract: Methods, systems and data structures select prioritized robust data values from a plurality of available data values formed by a plurality of data bits, each capable of exhibiting a bit value. Available data values are arranged into a gray code format, and alternate values of gray code format are selected to form a value map. An optional complementary value map may also be formed from the remaining data values. The value map is then prioritized according to bit adjacencies, wherein bit adjacencies are defined by contiguous bits within one of the data values that exhibit a common bit value. Priority may be given to data values having shortest and/or fewest bit adjacencies.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Abstract: A key bit position of a first Gray code is determined based on the bit values of the first Gray code. The first Gray code and a second Gray code that differs from the first Gray code only in the key bit position correspond to two associated numbers that differ by one.

Abstract: A generalized Gray code converter includes a decimal-binary to intermediate-binary converter and an intermediate-binary to Gray code converter. The decimal-binary to intermediate-binary converter is operable to convert a sequence of sets of electrical signals encoded in decimal-binary format (decimal-binary sequence) to a sequence of sets of electrical signals encoded in intermediate-binary format (intermediate sequence). The intermediate-binary to Gray code converter, connected to the decimal-binary to intermediate-binary converter, is operable to convert the intermediate sequence to a sequence of sets of electrical signals encoded in Gray code-binary format (Gray code sequence).

Abstract: A Gray code decoder for decoding input numbers includes a first select circuit that selects an M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J. A second select circuit selects an N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N. A concatenate circuit concatenates the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number.

Abstract: Skew-tolerant Gray codes have the property that consecutive code words differ in only one co-ordinate position, and the additional property that, in each consecutive group of three consecutive code words, the first and third code words differ in only two adjacent coordinate positions.

Abstract: The invention relates to an arrangement for converting a binary input signal corresponding to an n-bit thermometer code into a binary output code different therefrom, having a first number of OR gate circuits, into the inputs of which bits of the thermometer code can be coupled, having a first adder, which is connected downstream of the OR gate circuits and into the inputs of which the output signals of the OR gate circuits can be coupled and which provides at least one binary output signal for the output code at its outputs, having a second number of multiplexer circuits, into the inputs of which bits of the thermometer code can be coupled and into the multiplexer selection terminals of which the output signals of the first adder can be coupled, having a second adder, which is connected downstream of the multiplexer circuits and into the inputs of which the output signals of the multiplexer circuits can be coupled and which provides at least one further binary output signal for the output code at its outp

Abstract: Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time. To overcome these problems, a Gray code counter according to the present invention has a consecutively counting Gray code counter that counts in increments or decrements of one, and an output value converter circuit that converts the Gray code data output from the consecutively counting Gray code counter into a Gray code corresponding to decimal counts as obtained by counting with (2 raised to a particular power minus 1) counts skipped at a time.

Abstract: A coding apparatus, a program and a data processing method capable of attaining a high speed and a reduction of a computation amount in coding processing is provided, wherein coding portions for performing a left shift operation on a range and a lower limit value until the range exceeds a predetermined value and performing coding in accordance with the lower limit value before performing the left shift operation comprise a bit position specifying portion for specifying a bit position indicating a first logic value being closest to the MSB in a range; a shift amount specifying portion for specifying a shift amount immediately before the range exceeds a predetermined value by a left shift operation based on the bit position; a judging portion for judging whether there is a free space exceeding the shift amount in a predetermined bit length of extended region data added to the MSB side of the lower limit value, wherein bit data is carried from the lower limit value by the left shift operation; and an extended da

Abstract: In general, in one aspect, the invention features a Gray code decoder for decoding input numbers according to a K-bit Gray code and a Gray code encoder for encoding input numbers according to the K-bit Gray code. The K-bit Gray code is constructed from a M-bit Gray code having a one-bit separation I and a two-bit separation J and a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N.

Abstract: A system for gray-code counting in an integrated circuit such as a programmable logic device uses a binary adder coupled to a binary counter output and to a selected binary offset value. The binary adder provides a binary sum that is converted to a gray code value by a binary-to-gray converter. The gray code value represents the binary sum output.

Abstract: A method and computer program for generating a K-bit Gray code comprises (a) selecting a M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J; (b) selecting a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N; (c) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number; (d) generating the next 2N?1 sequential K-bit Gray code numbers, comprising (e) selecting a next M-bit Gray code number from the M-bit Gray code, (f) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a next K-bit Gray code number, and (g) repeating steps (e) and (f); (h) selecting a next N-bit Gray code number from the N-bit Gray code; and (i) repeating steps (c) through (h).

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: An image sensor includes a sensor array, a data memory for storing pixel data and a pixel normalization circuit. The sensor array has a two-dimensional array of pixel elements and outputs digital signals as pixel data representing an image of a scene. The pixel data outputted by the sensor array are arranged in a sensor-bit arrangement and the pixel normalization circuit rearranges the pixel data into a pixel-bit order. In another embodiment, an image sensor includes a sensor array, a data memory, and a pixel normalization circuit, all fabricated on a single integrated circuit. The pixel normalization circuit includes one or more of a pixel rearrangement circuit, a Gray code to binary conversion circuit, a reset subtract circuit, and a multiple sampling normalization circuit. Finally, a Gray code to binary conversion circuit is provided for high speed conversion.

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Abstract: A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.