Abstract: An encoding circuit for use with a comparator, includes a plurality of logic elements for receiving an input from a comparator, and a Gray code encoder for receiving an output from the plurality of logic elements. Both first and second type comparator errors (e.g., meta-stability errors and bubble-errors) are substantially eliminated simultaneously by the logic elements.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: A method for coding information in which the information consisting of signal sequences is mapped to binary code words having in each case a plurality of bit positions in such a manner that the redundant information contained in the symbol sequences represents information on the binary values of one or, respectively, some of these binary positions. The result is that the error rate of the decoded bits can be reduced without additional expenditure, and thus information can be transmitted with less interference.

Abstract: A high speed A/D converter includes a series of encoder sections for converting a thermometer code to a gray code and an error signal production section for detecting a babble error in the gray code and generating an error signal indicating such a babble error. An error correction section corrects babble errors in the gray code in response to the error signal. The corrected gray code is then converted to a binary code with a gray code to binary code converter. When the high speed A/D converter is incorporated in a semiconductor device, the A/D converter may be tested using a sampling clock having a phase which varies successively with respect to the input analog signal to sample the analog signal, and then evaluating the corresponding generated digital signal.

Abstract: An analog comparator compares an analog signal to be converted with an analog ramp signal. The output of the comparator enables a digital latch having a binary Gray code counter input. When the analog ramp equals the analog signal, the digital latch captures the state of the Gray code counter. Metastability in the digital latch is resolved by a latch train. The Gray coded output is then decoded by a Gray decoder to a standard binary output. An array of converters are constructed on a monolithic integrated circuit where each converter shares a single analog ramp generator, binary Gray code counter and Gray decoder. A multiplexer selects a particular converter and switches the standard binary output from the selected converter to line drivers to be used off-chip. The two least significant bits of the Gray code are generated with phase shifting circuits.

Abstract: Memory control circuitry is provided which includes circuitry for generating a sequence of gray code values. Counter circuitry is coupled to the gray code circuitry and controls the duration of assertion of each of the generated gray code values. Bus circuitry is also coupled to the gray code circuitry for transmitting the gray code values generated by circuitry. Programmable logic array circuitry is also coupled to the bus circuitry for transmitting, receiving and decoding each of the gray code values and providing at least one memory control signal in response.

Abstract: A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray ?n:0! which the first translator translates into a binary number, I.sub.bin ?n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin ?n:0! to produce an incremented/decremented binary number, Z.sub.bin ?n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin ?n:0! into an incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray ?n:0!, to the input of the first translator logic.

Abstract: A rate 5/7, d=0 channel code encodes a Gray code servo track address into channel data recorded on a magnetic disk; a PR4 sliding threshold Viterbi sequence detector detects the recorded servo track address upon read back; a cost effective d=0 decoder decodes the recorded servo track address into its Gray code representation; and a 1/1+D filter decodes the Gray code track address into its binary representation. Detecting the servo data with a PR4 Viterbi sequence detector, which is already provided in a read channel for detecting user data, increases the data density of the storage system. The cost and complexity of the decoder is reduced by encoding/decoding the Gray code track address in sections of five bits.

Abstract: A Half-Gray digital encoding technique is disclosed for use in a parallel analog-to-digital converter (ADC) that reduces the ADC's output errors. A thermometer code, proportional to the ADC's analog input, is provided to a decoder which produces 2.sup.n output lines with one active line for each binary 0-to-1 transition in the thermometer code. A 1-of-(2.sup.n)-to-Half-Gray encoder converts the decoder output to a Half-gray code which has error reducing properties. The Half-Gray code is then provided to an n-bit Half-Gray-to-binary decoder for converting the Half-Gray code to a standard Binary code ADC output.

Abstract: A first subset of components of a first set of pairs of complementary differential electrical signals representative of a numerical value expressed in a multi-bit thermometer code, is processed in accordance with a first set of Boolean functions to produce a first set of output electrical signal components , and a second subset of components of the first set of pairs of complementary differential electrical signals is processed in accordance with a second set of Boolean functions to produce a second set of output electrical signal components. The first and second subsets and the first and second sets of Boolean functions are such that the first and second sets of output electrical signal components when combined form a second set of pairs of complementary differential electrical signals representative of the same numerical value expressed in a second multi-bit code with fewer bits than the multi-bit thermometer code.

Abstract: This invention describes the use of a counter and digital logic to provide a timing pulse needed to decode Gray code position information on the tracks of a rotating disk storage media when the timing pulse is missing because the head of the disk drive is straddling two tracks as the Gray code passes beneath the head. The logic synchronizes the timer to provide a pulse at precisely the right time if and only if a pulse originated by the Gray code is missing.

Abstract: A digital counting circuit, including a binary counter supplying output sals to an adjacent code encoder that processes the received signals and transmits its output to a binary decoder. The encoder has a plurality of D-type flip-flop devices to which selected outputs of the binary counter are connected. The circuit operates so that only one input change to the binary decoder is permitted for each change of count from the binary counter. This prevents any erroneous counts from momentarily appearing on the output lines of the binary decoder.

Abstract: A high speed, synchronous counter which counts using a Gray code, Because Gray code counting has the unique property that only a single bit of the counter changes with each new count, the output of the counter may be latched at any time and the latched value will never be more than one count away from the actual count value in the counter. The present invention provides a look-ahead qualification bit that provides for an eight count look-ahead. With this eight count look-ahead capability, the qualification inputs to the high order bits can be created through a series of AND gates, each having only two inputs, thus saving significatnt power and space. Because most digital circuits require the output of a counter to be in binary code, the invention provides a conversion means for converting the Gray code input to a binary output.

Abstract: A very high speed optical converter for converting digital signals from Gray code to binary code and vice versa. The converter implements an exclusive-OR function. The converter may be constructed with fiber optic technology, AlGaAs ridge waveguide technology, LiNbO technology and other technologies.

Abstract: A modified quasi-Gray encoding technique for use in parallel analog-to-digital converters that significantly reduces errors resulting from multiple simultaneous inputs. The encoding technique converts a one-in-(2.sup.n -1) digital code into an n-bit binary word that is the same as quasi-Gray code in all but its least significant bit position, which alternates in the same manner as standard binary code. For many multiple simultaneous inputs, the modified quasi-Gray code substantially reduces errors when compared with quasi-Gray code. For example, the modified quasi-Gray code reduces the maximum error from 3 to 2 for two simultaneous inputs separated by two bit positions (n=8). In a typical parallel analog-to-digital converter employing the modified quasi-Gray code, the one-in-(2.sup.n -1) digital code is converted into modified quasi-Gray code using a read-only memory.