Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A technique for encoding index values of asynchronous pointers for a non-power-of-two sized buffer that supports the unit distance property. The technique includes converting N+1 pointer index values corresponding to index locations 0 through N of the buffer from the natural binary-coded decimal format to a unit distance code format such as the gray code, adding a 0 bit in the MSB position of each of the N+1 converted pointer index values, adding a first pointer index value at index location N+1 equal to the pointer index value at index location N except that a 1 bit replaces the 0 bit in the MSB position, and adding a plurality of pointer index values at index locations greater than N+1 but less than or equal to N+n+1 that are equal to the first added pointer index value, where “n” equals the number of bits in each pointer index value prior to conversion.

Abstract: A method for coding information in which the information consisting of signal sequences is mapped to binary code words having in each case a plurality of bit positions in such a manner that the redundant information contained in the symbol sequences represents information on the binary values of one or, respectively, some of these binary positions. The result is that the error rate of the decoded bits can be reduced without additional expenditure, and thus information can be transmitted with less interference.

Abstract: An electronic apparatus (24, 25, 27) having a plurality of externally selectable operating states is controlled to assume sequentially those states. The control is accomplished (41, 43, 45) using a sequence of state codes which define a reflected code.

Abstract: A Gray Code counter includes first translator logic, binary incrementing/decrementing logic, second translator logic, and a clocked storage device. The first translator logic receives at an input a Gray Code number, I.sub.gray ?n:0! which the first translator translates into a binary number, I.sub.bin ?n:0!. The binary incrementing/decrementing logic either increments or decrements the binary number I.sub.bin ?n:0! to produce an incremented/decremented binary number, Z.sub.bin ?n:0!. The second translator logic translates the incremented/decremented binary number Z.sub.bin ?n:0! into an incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device stores the incremented/decremented Gray Code number, Z.sub.gray ?n:0!. The clocked storage device also feeds the incremented/decremented Gray Code number, Z.sub.gray ?n:0!, to the input of the first translator logic.

Abstract: A digital counting circuit, including a binary counter supplying output sals to an adjacent code encoder that processes the received signals and transmits its output to a binary decoder. The encoder has a plurality of D-type flip-flop devices to which selected outputs of the binary counter are connected. The circuit operates so that only one input change to the binary decoder is permitted for each change of count from the binary counter. This prevents any erroneous counts from momentarily appearing on the output lines of the binary decoder.

Abstract: As an orthogonally transformed signal carries a value adjacent to zero, the output of an orthogonal transformer is coupled in series to a fixed length code encoder for converting the orthogonally transformed signal into a fixed length code signal which exhibits less bit inversion between positive and negative signals near zero. The orthogonal transformer and the fixed length code encoder constitute in combination an orthogonal transformer device.

Abstract: A FIFO 12 has a status flag generator 14. The status flag generator 14 includes a register programmable to "N". It also includes two sets of gray-code counters and a register (22,23,21;26,25,24) that are driven by separate READ and WRITE CLKS. The registers and counters are connected to comparators (31-36) for generating a plurality of signals that are input to output latches (41-43). The status flag generator is capable of generating status signals of FULL, HALF-FULL, EMPTY, FULL-N and EMPTY+N. N is a user-defined number that is programmed into a register 20 that is selectively connected to one or more of the programmable gray-code counters (23,24).

Abstract: A modified quasi-Gray encoding technique for use in parallel analog-to-digital converters that significantly reduces errors resulting from multiple simultaneous inputs. The encoding technique converts a one-in-(2.sup.n -1) digital code into an n-bit binary word that is the same as quasi-Gray code in all but its least significant bit position, which alternates in the same manner as standard binary code. For many multiple simultaneous inputs, the modified quasi-Gray code substantially reduces errors when compared with quasi-Gray code. For example, the modified quasi-Gray code reduces the maximum error from 3 to 2 for two simultaneous inputs separated by two bit positions (n=8). In a typical parallel analog-to-digital converter employing the modified quasi-Gray code, the one-in-(2.sup.n -1) digital code is converted into modified quasi-Gray code using a read-only memory.