Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: The present invention provides a system and method for reducing memory requirements in a low resource computer system. Although examples herein are described in terms of embedded systems, the present invention is equally applicable to other low resource computer systems, such as palmtops, and laptops. Memory requirements, such as RAM requirements, can be reduced by combining virtual memory with a secondary memory with statically compressed contents. According to embodiments of the present invention, executable image of memory, such as the image of RAM, is compressed at image production time. The compressed image is then stored in a non-volatile memory, such as FLASH memory. At run-time, when a request identifying a virtual address is received, it is determined whether a physical address in the physical memory, such as RAM, is associated with that virtual address. If there is no physical memory associated with that virtual address, then a physical address is obtained to be associated with that virtual address.

Abstract: A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

Abstract: A single-chip video-graphics controller displays a color image stored in an external display memory simultaneously on two devices having different refresh and display requirements. The controller includes a first display processor which fetches the color image from the external memory and displays the image on a first device, such as a color CRT monitor or TV. The controller reduces the bandwidth of the fetched color image on-the-fly and stores a copy of the reduced bandwidth image in another part of the external display memory. A second display processor fetches the reduced bandwidth copy at a rate compatible with a second display device, such as a DSTN flat-panel device using dithering for color depth enhancement. The two display processes are independent of each other, controlled only by the refresh requirements of the two display devices.

Abstract: A multiple embedded memory frame buffer system includes a master graphics subsystem and a plurality of slave graphics subsystems. Each subsystem includes a frame buffer and a color palette for decompressing data in the frame buffer. The master subsystem further includes a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device. The system further includes a timing system for determining which outputs of the subsystems are to to be converted by the digital to analog converter at a given time.

Abstract: A display controller to upscale a source video image for display on a display unit of a computer system. An encoder circuit in the display controller chip stores in a local memory pixel data of previous scan lines required for interpolation in a compressed format using differential pulse code modulation (DPCM) scheme. A decoder circuit decompresses the pixel data into original format prior to sending to an interpolator. The interpolator receives a present scan line and the decompressed data of previous scan lines, and interpolates the received pixels to generate additional pixels required for upscaling the source video image.

Abstract: A processing system 100 is provided which includes processing circuitry 103 fabricated on an integrated circuit chip 107. An internal memory 104a is also fabricated on chip 107. A first first-in/first-out memory 201 is provided having an input for receiving data retrieved from the internal memory 104a and an output for providing data to processing circuitry 103. An external memory 104b is provided. A second first-in/first-out memory 202 includes an input for receiving data retrieved from the external memory 104a and an output for providing data to the processing circuitry 103.

Abstract: A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.

Abstract: A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM.

Abstract: A main memory comprises one or more memory devices which include logic for performing a predetermined graphics operation upon graphics primitives stored therein. The microprocessor(s) within the computer system may direct the memory to perform the predetermined operation upon the graphics primitives instead of performing the operation within the microprocessor(s). If the graphics primitives are stored into multiple memory devices, each memory device operates upon the graphics primitives stored within that memory device in parallel with the other memory device's operation. Accordingly, the bandwidth is a linear factor of the number of memory devices storing graphics primitives. In one embodiment, each memory device iteratively performs the predetermined operation upon the set of graphics primitives stored in that memory device. Because the memory device is iterative, logic for performing the predetermined graphics operation upon one graphics primitive at a time may be employed.

Abstract: The present invention discloses methods and apparatus for implementing automatic graphics operations with selectable triggering mechanism. One mechanism is hardware related, using the vertical counter in the video control section of the graphics processor. The other mechanism is software related, using the host to directly command the graphics processor. The graphics operations are specified in the header file written by the host in the frame buffer memory. Several header files can be chained together to form a sequence of header files corresponding to very complex graphics operations. Automatic graphics operations, therefore, can be completed without further host intervention resulting in powerful graphics, video, and animation performance.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-ship frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: A frame buffer memory includes, on a semiconductor substrate: a DRAM array in which image information including frame information and window information are stored; two serial access memories for serially outputting the image information read from DRAM array by interleave method; a look-up table for outputting a selection signal in accordance with window information input; and a multiplexer for selectively outputting frame information input in accordance with said selection signal.

Abstract: A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the individual units include parallel paths internally. Preferably some of the individual units are connected to look ahead by more than one stage, to keep the pipeline filled while minimizing the use of expensive deep FIFOs.

Abstract: A multiple embedded memory frame buffer system includes a master graphics subsystem and a plurality of slave graphics subsystems. Each subsystem includes a frame buffer and a color palette for decompressing data in the frame buffer. The master subsystem further includes a digital to analog converter coupled to receive the decompressed digital data from the palette of each subsystem and outputting analog versions of the digital data to an output device. The system further includes a timing system for determining which outputs of the subsystems are to to be converted by the digital to analog converter at a given time.

Abstract: A smart video memory (10) is provided that includes data storage (12 and 18), a serial access memory (19), and a processing core (14 and 16) for executing instructions stored in the data storage area (12 and 18). Externally, smart memory (10) is directly accessible as a standard video memory device.

Abstract: A highly integrated, single chip computer system having not only a central-processing unit (CPU) but also specialized coprocessors. The specialized coprocessors, for example, enable the single chip computer system to be reasonably sized, yet perform high quality video (e.g., MPEG-2) and graphics operations (e.g., three-dimensional graphics). The single chip computer system offers improved performance of video and graphics operations, resource scheduling and security. The improved security offered by the single chip computer system enables program code or data stored external to the single chip computer system to be encrypted so as to hinder unauthorized access, while internal to the single chip computer system the program code or data is decrypted. The single chip computer system is particularly suitable for video game consoles having high quality graphics and/or video, digital video disk (DVD) players, and set-top boxes.

Abstract: A single-chip video-graphics controller includes a novel circuit for eliminating full line buffers when reducing line-to-line flicker in a display image of non-interlaced data on an interlaced color display device such as an NTSC or PAL television projector. The flicker reduction circuit uses a pair of memory access agents for concurrently fetching even and odd interlace frames of the display image. Corresponding color pixels of the two frames are averaged on-the-fly, and the averaged output is converted to analog RGB output signals for driving the display device. The elimination of the full line buffers results in a savings of approximately 30,000 transistors per buffer and a corresponding reduction in operating power. A specific embodiment of the controller includes a vertical stretching circuit used to adjust the number of vertical lines corresponding to the display image permitting the vertical reformatting of any display image.

Abstract: A display controller 104 for use with a display device 107 operable to display images on a screen. Display controller 104 includes circuitry 201-210 for presenting first data to the display device 107 for generating an image in a first areas of the screen, the first data being retrieved from an external frame buffer 108. A display controller 104 further includes circuitry 205, 210 for presenting second data to the display device 107 for generating an image in the second area of the screen, the second data being retrieved from an internal frame buffer 206.

Abstract: The present invention provides a converging data pipeline device comprising a first pipeline data path for carrying data, a second pipeline data path for carrying data, a shared pipeline data path which is capable of receiving data from each of the first and second pipeline data paths, and a resending mechanism comprised by the second pipeline data path. The resending mechanism makes a backup copy of at least a portion of the data at a particular location on the second path. Each of the paths comprises a plurality of pipeline stages, each pipeline stage capable of holding data and propagating the data in a direction from a first end of the path toward a second end of the path. The first end of the shared path is in communication with the second ends of the first and second data paths for receiving data from the second ends of the first and second data paths. When the flow of data is suspended along the second path, data is sent down the first path and through the shared path.

Abstract: A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed.

Abstract: The present invention provides a method and apparatus for processing primitives in a computer graphics display system. The present invention comprises a geometry accelerator for processing polygons to provide two-sided lighting for front and back facing polygons. The geometry accelerator comprises a lighting machine and a memory device in communication with the lighting machine. The geometry accelerator receives command data, vertex data, and parameter data from a central processing unit (CPU) of a computer graphics display system. The vertex data comprises polygon vertex color data, vertex coordinate data and vertex normal data. The parameter data comprises front and back material parameters. The command data comprises information relating to the type of primitive to be processed by the lighting machine.

Abstract: Systems and methods are described for combining a plurality of memory sections with a controller, all in a single semiconductor chip. A data processing chip has two or more DRAM memory sections with at least one section being divided into a number of arrays. Data is stored in a particular memory section depending on its associated task. For instance, pixel data is stored in a frame buffer memory section, whereas data relating to pattern, cursor, and video line buffers are stored in an auxiliary memory section. These two separate sections of memory have their own set of address, read/write, activate, control and data lines. Hence, they can be accessed independently by the memory controller. Furthermore, a memory section can be subdivided into a number of distinct arrays. For the subdivided memory section, two separate and distinct address/control buses are implemented to access these arrays. The first address bus is used to specify which selected row within one of these arrays is to be activated.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor has, on a single VLSI device, a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors, and further has registers for controlling access, and the modes of access, to data held in memory.

Abstract: A Unified Memory Architecture (UMA) using intelligent media memory provides an improved way of solving the granularity and memory bandwidth problems in the electronic computer memory system. A specially designed memory chip is attached to an existing attachment point of the system by integrating the bus interface on the memory chip. The memory chip additionally integrates on-chip data-intensive computation functions with the dynamic random access memory (DRAM) macros. Two system attachment points for the new integrated DRAM and logic chip are disclosed; the first using the local central processing unit (CPU) bus interface, and the second using a combination of the main memory bus and an alternative system bus such as a Peripheral Component Interconnect (PCI) bus.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 64 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 64 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 64 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST").

Abstract: A digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Most audio and/or video compression algorithms use a Huffman style bit compression scheme with compression codes in variable length bit fields. The compressed data is a compacted bit stream which must be interpreted serially in order to extract the codes. In contrast to most microprocessors which process bit streams only inefficiently, the present invention uses a serialization FIFO to provide a hardware assist to the Huffman encoding/decoding.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST").

Abstract: A graphic system which includes a display device having a graphic display area which includes a plurality of display portions and a plurality of one-chip semiconductor integrated circuit devices. Each one-chip semiconductor integrated circuit includes memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out logic operation on a unit of one pixel data read out from the memory based on a function signal supplied to the one-chip semiconductor integrated circuit device. The function signal indicates a relation between the unit of one pixel data read out from the memory and pixel data output by the logic circuit. The invention further includes an external device for supplying the function signal to the one-chip semiconductor integrated circuit device. The logic circuits, of the plurality of one-chip semiconductor integrated circuit devices, each carry out the same logic operation in accordance with the function signal.

Abstract: The preferred embodiment discloses a pipelined graphics processor in which the sequence can be dynamically reconfigured (e.g. between primitives) in a rendering sequence. The pipeline sequence can be configured for compliance with specifications such as OpenGL, but may also be optimized by reconfiguring the pipeline sequence to eliminate unnecessary processing. In a preferred embodiment, pixel elimination sequences such as depth and stencil tests are performed before texturing calculations are performed, so that unneeded pixel data is discarded before said texturing calculations are performed.

Abstract: A computer unified memory architecture (UMA) system and method which includes a unified memory which is partitioned into a main memory and a main frame buffer memory, as well as a separate expansion frame buffer memory. Together, the main frame buffer memory and the expansion frame buffer memory form an entire frame buffer memory. The UMA system performs a display refresh operation by alternately accessing the main frame buffer memory and the expansion frame buffer memory. Because the display data bandwidth is split between the main frame buffer memory and the expansion frame buffer memory, the data bandwidth of the unified memory is effectively increased, thereby enabling higher system performance. The expansion frame buffer memory has a relatively small capacity, thereby retaining much of the cost benefit of a UMA system.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and special addressing modes. A single VLSI device has a plurality of processors which cooperate for generating video signal streams and which employ distinctive addressing modes for memory elements of the device. Each of the plurality of processors has associated instruction and data caches, and the processors are joined together by a wide data bus formed on the same substrate as the processors. Each processor has a load/store unit, a translation unit associated with the load/store unit, and an index control register for controlling any translation of data bit streams passed through the load/store unit.

Abstract: A graphics subsystem using a smart DMA controller to perform DMA data loading with some modified addressing. The DMA controller can operate in an incremental mode, in a hold mode (where each chunk of data is written into the same address), or in an indexed mode. The buffer registers are assigned to groups, and, in the indexed mode, a header in the DMA buffer precedes any data for a group. The header identifies the recipient group and each register (in the group) to be updated has its corresponding bit set. Thus a high-efficiency DMA operation is obtained even in cases when increment mode cannot be used directly, e.g. when not all registers in a group need to be written, and/or the registers which need to be written are not contiguous.

Abstract: A device for displaying pixel data on a graphic display area of a display device. The graphic display area includes a plurality of display portions. The invention includes a memory for storing a plurality of pixel data, each pixel data includes a plurality of bits and color data, and a logic circuit for carrying out a logic operation on a combination of a unit of one pixel data read out from the memory and external data supplied to the device. The logic circuit outputs pixel data based on the logic operation so as to display the pixel data on one of the display portions of the graphic display area of the display device.

Abstract: Two frame buffer memories are used. Depth coordinates are stored in a data bank memory of the first frame buffer memory. A comparing unit makes comparison between the depth coordinate of an image data currently displayed and the newly input depth coordinate, and thereby outputs a comparison result signal from a comparison result signal output terminal. In the second frame buffer memory, color data is stored in a data bank memory, and the comparison result signal sent from the first frame buffer memory is input via a comparison result signal input terminal. An image processing unit performs blending processing on the color data in response to the comparison result signal, and rewrites the color data.

Abstract: A rendering system with multi-pixel span processing capability. When 3D graphics processes are not required, 2D data is processed in multi-pixel span fragments. Span fragments permit parallel processing of multiple pixels in a serial architecture, and permit VRAM block fills for accelerated processing under optimal conditions.