Abstract: A method and apparatus for allocation and control of memory bandwidth within a video graphics system is accomplished by first determining the memory bandwidth needs of each of the plurality of memory clients in the video graphics system. Based on this determination, a plurality of timers are configured, wherein each of the timers corresponds to one of the plurality of memory clients. The timers associated with the memory clients store two values. One value indicates the memory access interval for the corresponding client, which determines the spacing between memory access requests that can be issued by that particular client. The other value stored in the time is a memory access limit value, which determines the maximum length of a protected access to the memory by that particular client. A memory controller in the system receives requests from the plurality of clients and determines the priority of the different requests.

Abstract: An on-screen display (OSD) processor, processing method and article of manufacture are provided having a color mapped mode, direct color mode, and 4:2:2 profile mode. The OSD processor implements both color mapped OSD region processing capability and direct color OSD region processing capability, along with an ability to store quantizer coefficients for the 4:2:2 profile mode of a video decoder coupled to the OSD processor. The capabilities of the OSD processor are implemented using a common embedded memory within the processor. During color mapped OSD region processing, color table data is temporarily stored within the embedded memory, while in direct color OSD region processing, direct color descriptions are stored within the embedded memory. When the video decoder is decoding a 4:2:2 formatted image, the embedded memory of the OSD processor is used to temporarily store inverse quantization data for the decode function.

Abstract: Apparatus and methods are provided for allowing two graphics controllers to cooperate on a single screen and for modifying the AGP protocol to provide symmetric capabilities for both AGP targets and AGP masters. According to one embodiment of the present invention, an Accelerated Graphics Port (AGP) master may initiate a data transaction. A graphics controller receives an AGP transaction request from a core logic device. The graphics controller buffers the AGP transaction request in a request queue. Then, the graphics controller initiates a data transaction in response to the AGP transaction request.

Abstract: An inklayer image transparency system of the present invention has a graphics controller or processor, memory, and a display device that may be external to the inklayer image transparency system. The graphics controller is suitable for receiving signals (e.g. an address signal and a transparency control signal) and for providing image information to the display device. The memory is divided into at least two memory sections including a first memory section for storing foreground image information and a second memory section for storing background image information. A single address signal received by the graphics controller is used for simultaneously fetching the foreground image information from the first memory section and the background image information from the second memory section. A transparency control signal having a nontransparent state and a transparent state is used to control whether the foreground image or background image is displayed.

Abstract: A video and graphics system uses multiple transport processors to receive compressed data streams to perform PID and section filtering as well as DVB and DES decryption and to demultiplex them. The compressed data streams may include in-band and out-of-band MPEG Transport streams. The video and graphics system processes the PES into digital audio, MPEG video and message data. A core transport processor includes a PCR recovery module for extracting PCRs contained in the compressed data streams and for providing the extracted PCRs to a video transport processor and an audio decode processor. The PCR recovery module has a direct load capability for receiving user defined PCRs and outputting them instead of outputting the extracted PCRs. The PCR recovery module extracts PCRs from both MPEG Transport streams and DIRECTV transport streams.

Abstract: An integrated circuit for graphics processing that includes a configurable display interface includes video graphics circuitry, a data encoder, transmission circuitry and configuration registers. The video graphics circuitry produces video data that is formatted to drive a display. The data encoder is operably coupled to the video graphics circuitry and encodes the digital video data to produce transmission data. The transmission data is then provided to the transmission circuitry operably coupled to the data encoder. The transmission circuitry combines the transmission data with control information that is retrieved from registers included in the integrated circuit. The transmission circuitry transmits the transmission data over a plurality of differential signals, where the swing amplitude of the differential signals is configured using additional registers included in the integrated circuit.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: A computer system includes a first integrated circuit that has a central processing unit (CPU) and a graphics controller. An I/O hub, which is coupled to a plurality of input/output buses, includes a RAMDAC. An interconnect bus couples the first integrated circuit and the I/O hub and carries both graphics data to or from a frame buffer and also carries asynchronous system data between the processor and the input/output integrated circuit. The frame buffer may be located in the I/O hub to reduce graphics traffic over the interconnect bus.

Abstract: A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.

Abstract: A method of processing print data allowing for rendering bands of print data in parallel. A main processor (52) of a single-chip multiprocessor converts an incoming page of print data into paths. The paths are then converted to primitives and the primitives are rasterized using parallel processor (60, 62, 64, 66). The parallel processors (60, 62, 64, 66) work in concert with the main processor (52) such that bands of the final print image are rendered into a frame buffer (58) in parallel, allowing for faster and more efficient processing of print data.

Abstract: A method and apparatus for graphical processing. A logic core to perform pixel fragment manipulation and processing is instantiated on a single substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.

Abstract: A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

Abstract: A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: There is provided a display controller which can execute, with the hardware process, the address conversion corresponding to each drawing format even when a plurality of display data which are different in drawing formats exist simultaneously on the video memory and thereby can simultaneously improve the memory access performance in the drawing process and reduce a load of the CPU. This display controller 1 comprises an input section to which a display data and an address data are inputted, a video memory interface for writing the input display data to a video memory corresponding to a physical address in which each pixel of a 2n×2m (n and m are natural numbers) rectangular area formed by dividing the display area is continuous and a drawing circuit for executing the designated drawing process by receiving a command code for drawing from an external circuit.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.

Abstract: A multi-function controller in a computer graphics system performs the functions of a graphics processor, a video processor, a system memory controller, a cache controller, and a PCI bridge. The multi-function controller is connected to the host bus of the computer graphics display system to maximize performance. A graphics frame buffer and a system memory are combined into a unified system memory, which is controlled by and coupled to the multi-function controller.

Abstract: An image processing apparatus which can effectively use a storage circuit provided together with a logic circuit, perform high speed processing, and reduce the power consumption without causing a decline in the performance. The image processing system includes a DRAM for storing image data and a logic circuit, which are provided together on a semiconductor chip. The DRAM is divided into a plurality of DRAM modules, and the divided plurality of DRAM modules are arranged around a logic circuit portion for carrying out graphic drawing processing etc. When the ratio of valid data occupying bit lines in one access increases, the distances from the DRAM modules to the logic circuit portion become uniform, the length of the longest path interconnection can be made shorter comparing with the case of arrangement fixed in one direction, and the overall operating speed can be improved.

Abstract: The present invention provides a method for operating a core logic unit including an embedded graphics controller. This method facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a method for operating a core logic unit with an embedded graphics controller. This method includes receiving processor communications from a processor through a processor interface in the core logic unit, and transferring the processor communications through a switch to a graphics controller located in the core logic unit. It also includes receiving memory communications from a system memory through a memory interface in the core logic unit, and transferring the memory communications through the switch to the graphics controller. These processor communications and graphics communications are used to perform graphics computations in the graphics controller.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for receiving vertex data. The transform module serves to transform the vertex data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module. During use, an antialiasing feature is implemented to improve a quality of the graphics rendering.

Abstract: A memory system and method uses common memory for multiple controllers associated with, for example, differing data manipulation functions, such as video graphics related functions or other suitable functions. A multiplexer, configured as a time slicer, selects data for transfer with the memory over a first bus at a first rate. The multichannel serializer is coupled between the multiplexer and a plurality of controllers through a plurality of second buses. Each of the second buses is associated with a different channel. The multichannel serializer has a serializer for each of the plurality of second buses wherein each of the serializers transfers data associated with a channel at a second rate associated with a corresponding controller.

Abstract: A graphics display system has a graphics processor system for forming a color image on a display, the display being composed of an array of pixels. A memory system has a first memory for storing at least respective color data and respective Z data that is render from primitives of the image, and a second memory for storing respective display data, derived from the rendered color data and Z data, for each of the pixels. The graphics processor system has a memory interface operatively connected to the first and second memories. During formation of an image frame, the memory interface writes to and reads from a Z buffer, and only writes to a render target color buffer. After the image is rendered, image data is copied from the first memory to the second memory from which the image is displayed.

Abstract: A display master control (200) apparatus and method is provided for controlling a digital video pipeline within a reduced instruction set processor (120) for performing field-level control of the post filter 110, includes field/frame filtering display with up a four-tap multi-phase filter, MPEG1 standard image format (SIF) interpolations, on-the-fly aspect ratio switch, on-the-fly letter box and pan scan switch, video fade-in/out, multiple picture/jacket picture display, and multiple angle-picture display. Display master control 200 sets up horizontal and vertical filters (134, 136) for display line control (176).

Abstract: A memory has a wide data bus to an associative array processor. An entire row of the memory is read to or written by the associative array processor in a single access cycle. A data I/O controller is also coupled to the wide data bus between the memory and associative array processor. The data I/O controller has multiplexers that select one word from the wide data bus for access by a word-width system bus. A block-access mode selects a multi-word block in a row for access. A register latches in a block or row from the wide data bus, and words from the register are then accessed by the data I/O controller. The wide data bus is at least 1024 bits wide, and can be 5760 bits wide, enough for the associative array processor to read an entire line of a graphics or video picture.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.

Abstract: image processing system is capable of expressing a 3-D image correctly even if semitransparent images are complicatedly mixed in the 3-D image. A plurality of image generators each generate image data including a depth distance, from a predetermined reference portion, of an image to be expressed by the image data, and color information thereof. A merger specifies, e.g. sorts, the plurality of received image data in order of the depth distance included in each of the image data and merges the color information of the image data which is for expressing a first image whose depth distance is relatively long and the color information of the image data which is for expressing a second image in an overlapping manner over the first image.

Abstract: A method and apparatus employing lookup tables in a time sequential manner. A substrate has a display, a digital to analog converter, and a lookup table (LUT) formed thereon. The LUT is loaded with a LUT data set corresponding to an image subframe to be driven to the display. Successive LUT data sets corresponding to the next subframe are loaded after each subframe is driven to the display.

Abstract: A computer system includes an integrated core and graphic controller device having a core logic controller portion and a graphic controller portion, a system memory pool, and a stand-alone frame buffer memory pool separate from the system memory pool. A first memory data bus interconnects the integrated core and graphic controller device and the system memory pool. A second memory data bus interconnects the integrated core and graphic controller device and the frame buffer memory pool. A memory address and control signal bus interconnects the integrated core and graphic controller device, the system memory pool and the frame buffer memory pool.

Abstract: The basic section of the multimedia data-processing system comprises CPU 1100, image display unit 2100, unified memory 1200, system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: The present invention provides a method for operating a core logic unit including an embedded graphics controller. This method facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a method for operating a core logic unit with an embedded graphics controller. This method includes receiving processor communications from a processor through a processor interface in the core logic unit, and transferring the processor communications through a switch to a graphics controller located in the core logic unit. It also includes receiving memory communications from a system memory through a memory interface in the core logic unit, and transferring the memory communications through the switch to the graphics controller. These processor communications and graphics communications are used to perform graphics computations in the graphics controller.

Abstract: A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.

Abstract: The present invention may be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing and provides an optimum arrangement along the flow of information in the case where a frame buffer, a command memory and an image processor are incorporated in one chip in order to improve the drawing performance of an image processing device. Thereby, unnecessary drawing-around of wiring is eliminated and it is possible to reduce the chip area. Further, since the wiring length is shortened, signal delay becomes small, thereby enabling a high-speed operation.

Abstract: A graphics system configured to operate on a collection of vertices to determine mappings from an initial order to secondary and tertiary ordering. The initial order corresponds to the ordering of the vertices in an input buffer. The secondary (tertiary) ordering corresponds to the ordering of the vertices along a triangle major (minor) axis. The graphics system computes horizontal and vertical displacements along edges of the triangle in the initial ordering, and uses the signs of the horizontal displacements and vertical displacements to access a mapping table which determines the mappings. The mappings may be used to rasterize the triangle in terms of pixels (or samples).

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations.

Abstract: The present invention provides an architecture for a core logic unit including an embedded graphics controller. This architecture facilitates high-bandwidth communications between the graphics controller and other computer system components, such as the processor and the system memory. Thus, one embodiment of the present invention provides a core logic unit within a computer system including a processor interface for communicating with a processor, a memory interface for communicating with a system memory, and a bus interface for communicating across a computer system bus. It also includes a switch, coupled to the processor interface, the memory interface and the bus interface, for facilitating data transfers between these interfaces. The switch is connected to a graphics controller, which is located on the same semiconductor chip as the switch, for performing computations for displaying images on a computer system display.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.

Abstract: A CPU including a CPU-side signal line for connecting each of CPU-side memory device, OSD device, and OSD-side memory device to the CPU, and switching means for disconnecting the OSD device and OSD-side memory device from the CPU-side signal line when the CPU erases or rewrites memory contents of the CPU-side memory device through the CPU-side signal line.

Abstract: An integrated circuit device is adapted for use in a computer system that includes a processing unit, a host bus connected to the processing unit, an input/output bus, a peripheral device connected to the input/output bus, a monitor, and a system memory. The integrated circuit device includes a core controller adapted to be connected to the host bus, a bus bridge connected to the core controller and adapted to be connected to the input/output bus, a graphical controller connected to the core controller and the bus bridge and adapted to be connected to the monitor, and a unified memory control unit connected to the core controller and the graphical controller and adapted to be connected to the system memory.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.

Abstract: An integrated circuit device is adapted for use in a computer system that includes a processing unit, a host bus connected to the processing unit, an input/output bus, a peripheral device connected to the input/output bus, a monitor, and a system memory. The integrated circuit device includes a core controller adapted to be connected to the host bus, a bus bridge connected to the core controller and adapted to be connected to the input/output bus, a graphical controller connected to the core controller and the bus bridge and adapted to be connected to the monitor, and a unified memory control unit connected to the core controller and the graphical controller and adapted to be connected to the system memory.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A command parser 308 is coupled to an incoming data stream to insert an end of state token at the end of a group of state data 480 and an end of primitive token at the end of a group of primitive data 484 to create a parsed data stream. The parsed state data stream is transmitted to a state controller 420 which loads state data 480 into shadow stages 412. The state controller 420 validates a shadow stage 412 upon receiving an end of state group token. The parsed primitive data 484 are also transmitted to primitive controllers 424. The primitive controllers 424 prevent primitive data from being transmitted into a processing element 464 responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller 424 ascertains whether the first shadow stage 412 has been validated.

Abstract: A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Abstract: A single-chip chipset is provided for a personal computer. A graphics controller is integrated with the chipset and can access system memory. In addition, a frame buffer controller is provided on the same chip to allow the graphics controller to use an optional narrow, high speed, external frame buffer. The single-chip chipset may be used either in a configuration in which the graphics controller shares the system memory, or in a configuration in which the graphics controller uses the optional frame buffer.

Abstract: A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port (“AGP”) bus and host and memory buses, or as a bridge between a system area network interface and the host bus and the system memory bus. The function of the multiple use chipset is determined at the time of manufacture of the computer system, or in the field whether an AGP bus bridge or a system area network interface is to be implemented. Selection of the type of bus bridge (AGP or system area network interface) in the multiple use core logic chipset may be implemented by a hardware signal input, or by software during computer system configuration or power on self test (“POST”). Software configuration may also be determined upon detection of either an AGP device or a system area network interface connected to the core logic chipset.

Abstract: A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.