Abstract: Systems and methods of the present disclosure relate to fine grained interleaved rendering applications in path tracing for cloud computing environments. For example, a renderer and a rendering process may be employed for ray or path tracing and image-space filtering that interleaves the pixels of a frame into partial image fields and corresponding reduced-resolution images that are individually processed in parallel. Parallelization techniques described herein may allow for high quality rendered frames in less time, thereby reducing latency (or lag, in gaming applications) in high performance applications.

Abstract: The disclosure provides a renderer and a rendering process employing ray tracing and image-space filtering that interleaves the pixels of a frame into partial image fields and corresponding reduced-resolution images that are individually processed in parallel. In one example, the renderer includes: (1) an interface configured to receive scene information for rendering a full frame, and (2) a graphics processing system, coupled to the interface, configured to separate pixels of the full frame into different partial image fields that each include a unique set of interleaved pixels, render reduced-resolution images of the full frame by ray tracing the different partial image fields in parallel, independently apply image-space filtering to the reduced-resolution images in parallel, and merge the reduced-resolution images to provide a full rendered frame.

Abstract: A display waveguide configured for conveying polychromatic image light to a viewer includes a substrate and a higher-index layer supported by the substrate. The high-index layer supports the transmission of the longer-wavelength color channel of the image light in at least a portion of the field of view.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: A method for operating a semiconductor device includes receiving a memory request for a memory; calculating a memory bandwidth such that the memory bandwidth is at least large enough to support allocation of the memory in accordance with the memory request; creating a memory path for accessing the memory using a memory hierarchical structure wherein a memory region that corresponds to the memory path is a memory region that is allocated to support the memory bandwidth; and performing memory interleaving with respect to the memory region that corresponds to the memory path.

Abstract: A tile image sequence obtained by dividing a frame into a predetermined size is further divided into another predetermined size on an image plane to generate a voxel (for example, a voxel. If a redundancy in a space direction or a time direction exists, then data is reduced in the direction, and sequences in the time direction are deployed on a two-dimensional plane. Voxel images are placed on an image plane of a predetermined size to generate one integrated image. In a grouping pattern which exhibits a minimum quantization error, pixels are collectively placed in the region of each voxel image for each group (integrated image). The integrated image after the re-placement is compressed in accordance with a predetermined compression method to generate a compressed image and reference information for determining the position of a needed pixel.

Abstract: Techniques related to coding data including techniques for coding data using a universal codec are generally described. In some examples, such techniques may provide a universal (or unified) codec parameterized using a small set of parameters, which may be used to adapt the codec to different types of data to be compressed.

Abstract: Memory resources that are stored in GPU-specific formats may be accessed as linear arrays by CPU applications. Shared virtual memory (SVM) support enables closer CPU/GPU interaction. This creates a need to efficiently access graphics data using SVM. CPU page mapping and memory management hardware may perform the address/data swizzling and tiled rendering translations required for GPU memory formats. As a result, CPU applications can access GPU resources as if they are stored in a linear array, while also using shared virtual memory.

Abstract: A convolutional de-interleaver for processing multiple groups of convolutional interleaved data is provided. The groups of convolutional interleaved data include multiple sets of convolutional interleaved data formed by performing a convolutional interleaving process on multiple groups of non-interleaved data. Each set of non-interleaved data includes L sets of data, where L is a positive integer. The convolutional de-interleaver includes: an input data buffer, buffering the groups of convolutional interleaved data; a memory controller, accessing the convolutional interleaved data buffered in the input data buffer with a memory to perform a convolutional de-interleaving process, a memory address of each set of stored convolutional interleaved data being determined according to a corresponding delay depth, the value L and a delay depth difference corresponding to the set of data; and an output data buffer, buffering the multiple groups of convolutional de-interleaved data read from the memory.

Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.

Abstract: Aspects include a multistage collector to receive outputs from plural processing elements. Processing elements may comprise (each or collectively) a plurality of clusters, with one or more ALUs that may perform SIMD operations on a data vector and produce outputs according to the instruction stream being used to configure the ALU(s). The multistage collector includes substituent components each with at least one input queue, a memory, a packing unit, and an output queue; these components can be sized to process groups of input elements of a given size, and can have multiple input queues and a single output queue. Some components couple to receive outputs from the ALUs and others receive outputs from other components. Ultimately, the multistage collector can output groupings of input elements. Each grouping of elements (e.g., at input queues, or stored in the memories of component) can be formed based on matching of index elements.

Abstract: This disclosure provides systems, methods, and apparatus related to electromechanical systems display devices. In one aspect, an apparatus includes a display assembly, a sensor, and a processor. The display assembly may include an array of electromechanical systems display devices. The sensor may be configured to provide a signal indicative of an illumination angle, a viewing angle, or both, with respect to a line perpendicular to the display assembly. The processor may be configured to receive the signal from the sensor, to determine the illumination angle and/or viewing angle, and to process image data to compensate for the determined illumination angle and/or viewing angle. In one implementation, the image data is processed to compensate for a shift in a wavelength of light reflected from at least one of the electromechanical systems display devices that would have occurred as a result of a non-normal illumination and/or viewing angle.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array including first interconnections, second interconnections intersecting the first interconnections, and memory cells having a variable resistance element and being provided at respective intersections of the first interconnections and the second interconnections, the memory cell array being divided into bays including a predetermined number of the memory cells; and a control circuit configured to execute a first write step and a second write step executed after the first write step at a data writing operation, wherein the control circuit is configured to change over the number of simultaneously selected bits and/or the number of simultaneously selected bays depending upon whether a write step is the first write step or the second write step.

Abstract: A data access method applicable to a storage apparatus for reducing or eliminating an image tearing effect includes defining at least one write check point; comparing an actual write speed for writing data into the storage apparatus with a predetermined write speed at the write check point; and adjusting the actual write speed when a difference between the actual write speed and the predetermined write speed is larger than a predetermined value, for adaptively reducing the difference to be smaller than or equal to the predetermined value.

Abstract: Methods, computer program products, and systems for controlling and editing video using a video editing application running on a touch screen device by using touch gestures on the media viewing area displayed by the video editing application. The methods involve displaying a frame of a video file in a preview area on a touch-sensitive display, detecting one or more touch points making initial contact at respective initial positions on the preview area, detecting the one or more touch points moving over the preview area, and in response to detecting the one or more touch points moving over the preview area determining a direction of motion of the one or more touch points, and if the direction of motion is horizontal, stepping through one or more frames of the video file in the preview area, and if the direction of motion is vertical, setting a cut point on the video file at the displayed frame of the video file.

Abstract: A method for the display of compressed supertile images is disclosed. In one embodiment, a method for displaying an image frame from a plurality of compressed supertile frames includes: reading the compressed supertile frames; expanding the compressed supertile frames; and combining the expanded supertile frames to generate the image frame. The expanding can include generating an expanded supertile frame corresponding to each of the compressed supertile frames by inserting blank pixels for tiles in the expanded supertile frame that are not in the corresponding compressed supertile frame. Corresponding system and computer program products are also disclosed.

Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: Provided are a mapping method and a video system for mapping pixel data included in the same pixel group to the same bank of a memory, A method for mapping the position of pixel data of a picture to an address of a memory comprises a pixel group dividing operation and an address mapping operation. The pixel group dividing operation divides the pixels of the picture into at least one pixel group. The address mapping operation maps pixel data of pixels included in the same pixel group to the same bank of the memory.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A method of transmitting visual data from a host computer to multiple displays across a computer network is disclosed. Visual data is stored in a plurality of frame buffers, each frame buffer associated with a separate display. A frame buffer update sequence is determined, with operations to be performed on frame buffers in the plurality. The data stored in the plurality of frame buffers is encoded as specified by the buffer update sequence to yield encoded images and each encoded image is sent across a computer network to the separate display associated with the frame buffer from which the encoded image was derived.

Abstract: Provided is an image rotation method and apparatus for rotating an original image of 2n×2n pixels when n is a natural number greater than 1, including loading each row of pixels of the original image into a corresponding load memory vector; and, after the load step, for at least one iteration, performing a transposition operation for each matched load memory vector after matching the load memory vectors and, for zero or more iterations, an interleaving operation between each matched load memory vector after matching the load memory vectors, while the transposition step and the interleaving step are performed a total of n iterations.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Abstract: A memory address mapping method of controlling storage of images in a memory device is provided. The memory device includes banks each having a plurality of pages. The memory address mapping method includes: receiving a first image; and referring to an image partition setting to generate a first memory address setting for each horizontal line partition in the first image, wherein the image partition setting defines that one image is divided into horizontal line groups each having at least one horizontal line, and each of the horizontal line groups is divided into horizontal line partitions in a horizontal line direction. First memory address settings of the horizontal line partitions in each horizontal line group of the first image control that a corresponding horizontal line group having the horizontal line partitions included therein is not stored into a same bank of the memory device.

Abstract: A method of operating an address generator configured to map an image onto a plurality of memories via an interleaving includes detecting information associated with the image and the interleaving; selecting an address mapping scheme according to the detection result; and mapping the image onto the plurality of memories according to the selected address mapping scheme.

Abstract: Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least two memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to the memory devices and retrieved in parallel from the memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.

Abstract: A circuit for serializing bits including a clock circuit and a serializer. The clock circuit may be configured to generate a plurality of clock signals from a received master clock signal. A plurality of bits may be transmitted to the serializer in response to a transition of a first clock signal. The serializer may comprise a system of latches and a rotary circuit. The system of latches may be configured to receive a first half of the plurality of bits in response to a first transition of a second clock signal and to receive a second half of the plurality of bits in response to a transition of a third clock signal. The rotary circuit may be configured to receive the plurality of bits from the system of latches and to output each bit at a particular time based on a plurality of rotary clock signals.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: A graphics display device comprises a first and second memory, and a data transfer controller coupled with the first and second memory. In some embodiments, a method of storing pixel data comprises receiving and latching first pixel data associated with a first pixel, receiving second pixel data associated with a second pixel, and concurrently writing the first pixel data in the first memory and the second pixel data in the second memory. In other embodiments, a method of accessing pixel data of an image frame comprises accessing the first and second memory for reading out pixel data of each pair of adjacent pixels, when the image frame has an odd total number of pixels determining whether a final pixel data is in a latched state, and reading out the final pixel data from the data transfer controller when the final pixel data is in the latched state.

Abstract: Exemplary methods and systems for providing access to content during the presentation of a media content instance are disclosed herein. As described in more detail below, a content presentation system may detect a predefined motion of a mobile device during a presentation of a media content instance by a media content access device, identify the media content instance, and provide access to the identified media content instance by way of the mobile device in response to the predefined motion. Corresponding methods and systems are also disclosed.

Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Abstract: One embodiment of the present invention sets forth a system for generating multiple video output signals from a single video pipeline within a graphics processing unit. Pixel data from more than one display surface is retrieved and multiplexed before being transmitted to a video pipeline for processing. The resulting video pixel data is routed to video output encoders, which selectively accept the video pixel data for transmission to attached display devices.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: A graphics system utilizes virtual memory pages and has a partitioned graphics memory that includes memory elements. The system supports having an non-power of two number of active memory elements. Additionally, a partition swizzling operation is used to adjust the partition numbers associated with individual units of virtual memory allocation on particular virtual memory pages to achieve a selected partition interleaving pattern.

Abstract: A driver for driving a display panel and a method for reading/writing in a memory thereof and thin film transistor liquid crystal display (TFT-LCD) using the same are provided. The method of the present invention is a reading timing of memory which different than the prior reading timing of memory, so that, if using the method of the present invention in the driver even having only one memory, the tearing effect of the prior TFT-LCD can be solved and the whole power consumption thereof can also be reduced.

Abstract: Data is written to one of two frame buffers in write access cycles having write and non-write sub-periods. Data is read out to a display device from the other of the two frame buffers in read access cycles having read and non-read sub-periods. The writing of data and the reading of data are switched to a respective opposite frame buffer during a switching opportunity, a switching opportunity occurring when a read access cycle is in a non-read sub-period and a write access cycle is in a non-write sub-period. A count of the number of times a switching opportunity is not executed because a read access cycle is in a non-read sub-period while a write access cycle is in a write sub-period is incremented. If the count exceeds a particular threshold, a write access cycle subsequent to the count exceeding the threshold is masked. When a write access cycle is a masked data is not written into a buffer.

Abstract: An apparatus for information extraction from electromagnetic energy via multi-characteristic spatial geometry processing to determine three-dimensional aspects of an object from which the electromagnetic energy is proceeding. The apparatus receives the electromagnetic energy. The received electromagnetic energy has a plurality of spatial phase characteristics. The apparatus separates the plurality of spatial phase characteristics of the received electromagnetic energy. The apparatus r identifies spatially segregated portions of each spatial phase characteristic, with each spatially segregated portion of each spatial phase characteristic corresponding to a spatially segregated portion of each of the other spatial phase characteristics in a group. The apparatus quantifies each segregated portion to provide a spatial phase metric of each segregated portion for providing a data map of the spatial phase metric of each separated spatial phase characteristic.

Abstract: An image data transfer method including the steps of: (a) reading pixel data of a two-dimensional image stored in a first image storage and having a plurality of pixels, the position of each of the pixels being represented by coordinates of first and second directions, the pixel data being read by scanning data transfer units of the pixel data in the second direction where each of the data transfer units is formed by data of a predetermined number of pixels consecutive in the first direction; (b) writing the data transfer units read at step (a) in a temporary data storage where data is stored at a position designated by a combination of first and second addresses, the data transfer units being written in burst mode in a region of the temporary data storage in which the first addresses are consecutive while the second address is fixed; and (c) reading the data transfer units written in the temporary data storage from the region in which the first addresses are consecutive while the second address is fixed in b

Abstract: Methods and systems for coordinating the handling of information are disclosed herein and may include scheduling multiple processing tasks for processing multimedia data by a processor. A portion of the scheduled multiple processing tasks may be preprocessed and the preprocessed portion may be buffered within a modifiable buffer that handles overflow and underflow. A portion of the buffered preprocessed portion of the scheduled multiple processing tasks may be executed. The scheduling may utilize a non-preemptive scheduling algorithm, such as an earliest deadline first (EDF) scheduling algorithm and/or a rate monotonic (RM) scheduling algorithm. The scheduled multiple processing tasks may include at least one maximum real deadline. The preprocessed portion of the scheduled multiple processing tasks may be outputted during processing of the blocking task, if a current task of the scheduled multiple processing tasks comprises a blocking task.

Abstract: Systems and methods for addressing memory where data is interleaved across different banks using different interleaving granularities improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected to modify the number of sequential addresses mapped to each DRAM and change the interleaving granularity. A memory addressing scheme is used to allow different partition strides for each virtual memory page without causing memory aliasing problems in which physical memory locations in one virtual memory page are also mapped to another virtual memory page. When a physical memory address lies within a virtual memory page crossing region, the smallest partition stride is used to access the physical memory.

Abstract: An apparatus comprising a memory and a coder/decoder circuit. The memory may have a first memory portion and a second memory portion. The coder/decoder circuit may be configured to (i) position a set of atoms across the memory, (ii) define a strip across a portion of the atoms, (iii) designate a first atom within the strip, (iv) locate one or more second atoms to be paired with the first atom, (v) determine whether the one or more second atoms when paired with the first atom forms a legitimate pair, and (vi) read the legitimate pair from the first memory portion and the second memory portion.

Abstract: Methods and apparatus for storing and retrieving data using two-dimensional arrays. In one implementation, a checkerboard buffer page system includes: a data source, providing data elements in a first order; a data destination, receiving data elements in a second order; memory devices having memory pages, data elements stored and retrieved in parallel to and from the memory devices; each buffer page having entries along a first dimension corresponding to the first order and along a second dimension corresponding to the second order, data elements stored in the first order and retrieved in the second order, at least one memory page stores data elements in multiple locations according to the first and second orders, at least two data elements consecutive in the first order are stored in parallel to the memory devices, and where at least two data elements consecutive in the second order are retrieved in parallel from the memories.

Abstract: Systems, methods, and apparatus, including computer program products, are provided for forming composite images. In some implementations, a method is provided. The method includes receiving a set of component images for forming a composite image, defining a projection for the set of images transforming each component image into a projected component image, and rendering the projected component images to form the composite image. The rendering of each component image includes decomposing a rotation of the projection into separate rotations for each axis, rotating the component image along a first axis, separately identifying pixel values for each row and each column of the projected component image, and rotating the image along a third axis to form a rendered component image.

Abstract: The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.

Abstract: Systems, methods, and computer program products receive an image request identifying an image having a width and a height. A number of interleaved buffers is identified, each of the interleaved buffers operable to store data associated with the image. The image is split into each of the interleaved buffers on a computing device. An interleaved image is displayed corresponding to at least one of the interleaved buffers, where the interleaved image having substantially the same width and height of the image.

Abstract: A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.

Abstract: Embodiments of the present invention relate to accessing a first pair of adjacent data blocks using a first channel of a dual channel memory device; and simultaneously accessing a second pair of adjacent data blocks using a second channel of the memory device, the second pair being spaced apart from the first pair by a predetermined interval.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: The proposed technique provides simultaneous read and writes from a display controller using low-cost SDRAMs. This is achieved, in one example embodiment, by receiving a sequence of video frames at a first variable frame rate. A first video frame is then written in a first single-ported memory. The first video frame is then read from the first single-ported memory upon completing the writing of the first video frame in the first single-ported memory. The reading of the first video frame is then repeated from the first single-ported memory to maintain a second frame rate. The second frame rate is higher than the first variable frame rate. A second video frame is then written in a second single-ported memory upon completing the writing of the first video frame in the first single-ported memory such that the writing of the first video frame and the second video frame is at the first variable frame rate.