Abstract: A medical image processing apparatus for rendering medical images includes a first GPU and a second GPU, each configured to read from and write to a data structure stored in virtual memory. The data structure is configured to be read by both the first GPU and the second GPU and the data structure is configured such that the first GPU can write to a first sub-space of the data structure and the second GPU can write to a second sub-space of the data structure. The first sub-space and the second sub-space are independent. The first GPU is configured to write data relating to pre-processing for rendering to the first sub-space and the second GPU is configured to read the written data and to render at least one image based on the written data.

Abstract: An electronic device includes a first processing unit and a second processing unit, a first memory unit correspondingly set for the first processing unit and configured for data access by the first processing unit, and a second memory unit correspondingly set for the second processing unit and configured for data access by the second processing unit. The first processing unit occupies at least part of storage space of the second memory unit when a first criteria is met, and/or the second processing unit occupies at least part of storage space of the first memory unit when a second criteria is met.

Abstract: Methods and apparatus for device driver operation in non-kernel space. In one embodiment, an apparatus configured to configured to interface to a component device driver within non-kernel space is disclosed. The exemplary embodiment restricts device drivers to fewer privileges than kernel processes, while still providing acceptable real-time performance. In another embodiment, mechanisms for non-kernel space device driver operation are described. In one exemplary embodiment, a shared memory interface between kernel space and device drivers enables e.g., a zero-copy device driver architecture.

Abstract: A data processing system includes a host processor, a processor suitable for processing a task instructed by the host processor, a memory, shared by the host processor and the processor, that is suitable for storing data processed by the host processor and the processor, respectively, and a memory controller suitable for checking whether a stored data processed by the host processor and the processor are reused, and for sorting and managing the stored data as a first data and a second data based on the check result.

Abstract: Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In an embodiment, a memory controller stores a value in a mode register of a DRAM device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled. An external contact of the DRAM device is coupled to the memory controller device via a signal line of a data bus. In another embodiment, the memory controller sends a signal to the external contact while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable.

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

Abstract: Methods and systems configured to virtualize graphic processing services in a virtual machine environment are disclosed. A virtual machine monitor (VMM) may be configured to maintain a virtual machine (VM) based on a host operating system (OS) executing in the system. The VM may contain a virtualized graphics library (vGLib) configured to support a graphic command from an application executing in the VM. The host OS may contain a graphics library (GLib) configured to support the graphic command and utilize a graphics processing unit (GPU) in the system to process the graphic command. Upon receiving the graphic command from the application, the vGLib may be configured to allocate a memory section in the VM to store the graphic command. And the VMM may be further configured to share access to the memory section with the host OS, thereby allowing the host OS to retrieve the graphic command from the memory section and deliver the graphic command to the GLib for processing.

Abstract: A display control device is connected to and controls a display device. The display control device comprises a frame buffer store, and a control component. The display control device is arranged to receive (S1) compressed display data, store (S2) the received compressed display data in the frame buffer store, and for each frame refresh of the display device access (S3) stored compressed display data, decompress (S4) the accessed display data, and output S5 the decompressed display data.

Abstract: A data storage device includes a memory that has a three-dimensional (3D) memory configuration, a controller, and a plurality of memory ports. The controller is configured to read mapping data from the memory. The mapping data maps the plurality of memory ports to the plurality of storage elements. The controller is further configured to, in response to receiving a command associated with a logical address, determine a physical address of the memory corresponding to the logical address, the physical address corresponding to a group of storage elements of the plurality of storage elements. The controller is further configured to select a memory port of the plurality of memory ports, where the memory port is mapped to the group of storage elements. The controller is further configured to access the group of storage elements via the memory port to perform first command.

Abstract: This disclosure presents techniques and structures for determining a rendering mode (e.g., a binning rendering mode and a direct rendering mode) as well as techniques and structures for switching between such rendering modes. Rendering mode may be determined by analyzing rendering characteristics. Rendering mode may also be determined by tracking overdraw in a bin. The rendering mode may be switched from a binning rendering mode to a direct rendering mode by patching commands that use graphics memory addresses to use system memory addresses. Patching may be handled by a CPU or by a second write command buffer executable by a GPU.

Abstract: A method and system for shared virtual memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a system memory. A CPU virtual address space may be created, and the surface may be mapped to the CPU virtual address space within a CPU page table. The method also includes creating a GPU virtual address space equivalent to the CPU virtual address space, mapping the surface to the GPU virtual address space within a GPU page table, and pinning the surface.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: Methods and systems for reducing communication during video processing utilizing merge buffering are disclosed and may include storing data in a merge buffer in the virtual machine layer in a wireless communication device comprising a virtual machine user layer, a native user layer, a kernel, and a video processor. The data may then be communicated to the kernel via the native user layer. The data may include function calls, and/or kernel remote procedure calls. The data may be communicated via an application programming interface. Video data may be processed in the video processor based on the communicated data. The virtual machine user layer may include a Java environment. The data may be communicated to the kernel via the native user layer when the merge buffer is full or filled to a predetermined level.

Abstract: One embodiment of the present invention sets forth a technique for addressing data in a hierarchical graphics processing unit cluster. A hierarchical address is constructed based on the location of a storage circuit where a target unit of data resides. The hierarchical address comprises a level field indicating a hierarchical level for the unit of data and a node identifier that indicates which GPU within the GPU cluster currently stores the unit of data. The hierarchical address may further comprise one or more identifiers that indicate which storage circuit in a particular hierarchical level currently stores the unit of data. The hierarchical address is constructed and interpreted based on the level field. The technique advantageously enables programs executing within the GPU cluster to efficiently access data residing in other GPUs using the hierarchical address.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.

Abstract: Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory.

Abstract: A method and system for coordinated data execution in a computer system. The system includes a first graphics processor coupled to a first memory and a second graphics processor coupled to a second memory. A graphics bus is configured to couple the first graphics processor and the second graphics processor. The first graphics processor and the second graphics processor are configured for coordinated data execution via communication across the graphics bus.

Abstract: The present invention relates to a display device for a glass cockpit of an aircraft, intended to provide video streams to a plurality of viewing screens of said glass cockpit, said aircraft being partitioned into a secured area, a so-called avionic world (AW), and a non-secured area, a so-called open world (OW), said system comprising at least one first port intended to receive first data to be displayed from a system (210, 310, 410) belonging to the avionic area and at least one second port intended to receive second data to be displayed from a system (220, 320, 420) belonging to the open world, the display device comprising: predetermined hardware resources allocated to the processing of the second data; a processor (241, 341, 441), belonging to the avionic area, adapted to controlling the hardware resources used by said processing and interrupting this processing if said hardware resources used exceed said allocated resources.

Abstract: An apparatus including a first memory, a second memory, and a memory interface. The first memory may be configured to store an entire image. The second memory may be configured to store a portion of the image during an image processing operation. The memory interface may be configured to transfer the portion of the image (i) from a source area of the first memory to the second memory prior to the image processing operation and (ii) from the second memory to a destination area of the first memory following the image processing operation. The memory interface may be further configured to select from among four modes of transferring image data from the source area of the first memory and to the destination area of the first memory based upon how the source area and the destination area overlap in the first memory.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: A memory system having a number of partitions each operative to independently service memory requests from a plurality of memory clients while maintaining the appearance to the memory client of a single partition memory subsystem. The memory request specifies a location in the memory system and a transfer size. A partition receives input from an arbiter circuit which, in turn, receives input from a number of client queues for the partition. The arbiter circuit selects a client queue based on a priority policy such as round robin or least recently used or a static or dynamic policy. A router receives a memory request, determines the one or more partitions needed to service the request and stores the request in the client queues for the servicing partitions.

Abstract: In order to reduce degradation of the processing performance of the data processor due to use of a part of the main memory as a display frame buffer, when an access request to the memory 200 is generated from the CPU 310, the memory controller 400 holds it once, requests the display controller 560 to stop the access to the memory 200 which is in execution, when data to the access executed already is transferred from the memory 200, holds it, and transfers the access request from the CPU bus 310 which is held by the memory 200. When the access from the CPU bus 310 ends, the memory controller 400 restarts the access stopped in the display controller 560 and passes the held data to the display controller 560.

Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a Z-buffer memory. The apparatus also includes a set of bits, each of which corresponds to a block of the Z-buffer memory. The apparatus also includes an initialization (init) register. The apparatus also includes control logic coupled to the Z-buffer memory, the set of bits, and the init register. The control logic sets the set of bits upon receipt of an initialization request. The control logic retrieves a Z value from either the init register or from the Z-buffer memory according to the states of the set of bits.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Abstract: A method and an apparatus for an integrated high definition television controller are described. The integrated high definition digital television controller includes two or more the following functions in a single chip: MPEG2 Transport, Audio and Video Decoders, Video input capture and converter, flexible video scan rate converter, de-interlace processor, display controller and video D/A converters, graphics controller, a unified local bus, N-plane alpha blending, a warping engine, audio digital signal processor, disk drive interface, peripheral bus interfaces, such as PCI bus and local bus interfaces, various I/O peripherals, a bus bridge with a partitioned chip, and a CPU with caches. The integrated controller, in one embodiment, is designed to handle multiple television standards (for example ATSC, ARIB, DVB, AES, SMPTE, ITU) and designed to be deployed in various countries in the world.

Abstract: Apparatus for controlling a digital television display, the apparatus comprising a main processor 4, a main memory 5 coupled to said main processor 4 via address and data busses, the main memory 5 being arranged to store at least temporarily video data for display, and on-screen display graphics for overlaying on video data. Mixing means 15 is provided for mixing video data read from the main memory 5 under the control of the main processor 4, with on-screen display graphic data. At least one line buffer 13a,13b is provided for storing a line of on-screen display graphic data. Hardware processing means 9 is arranged to compose a line of on-screen display graphic data in the line buffer 13a,13b by reading appropriate on-screen display graphic data from said main memory 5 and writing it to the line buffer, and for providing the composed line of data to said mixing means 15.

Abstract: A method, data processing system, and computer instructions for simulating direct frame buffer access. A request for access to a frame buffer memory is received from an application. A portion of system memory is allocated for use as the frame buffer memory in response to receiving the request. A pointer to the portion of system memory is returned to the application. The application writes data to the portion of system memory, treating the portion of system memory like the frame buffer memory.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A memory controller hub includes a graphics subsystem adapted to perform graphics operations on data and a cache adapted to store of locations in physical memory available to the graphics subsystem for storing graphics data and available to a graphics controller coupled to the memory controller hub to store graphics data.

Abstract: The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.