Abstract: Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

Abstract: A system to perform processing operations of input (video) streams, including is disclosed. The system consists of an input module, a stream type detection engine, a plurality of processing resources a resource monitoring engine, an attribution module, a dispatching module, and various other optional interface modules.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for generating, by an image sensor of a computing device, frame data comprising sub-frames of image pixel data. A first resource of the system-on-chip provides the frame data to a second resource of the system-on-chip. The frame data is provided to the second resource using a first data path included in the system-on-chip. The first resource provides a token to the second resource using a second data path included in the system-on-chip. A processor of the system-on-chip, uses the token to synchronize production of sub-frames of image pixel data provided by the first resource to the second resource and to synchronize consumption of the sub-frames of image pixel data received by the second resource from the elastic memory buffer.

Abstract: A processing section executes processes concerning a plurality of applications in a time division manner. A Context Switching Direct Memory Access (CSDMA) engine detects a switching timing of an application to be executed in the processing section. When detecting the switching timing, the CSDMA engine saves a context of an application that is being executed in the processing section 46, to a main memory from the processing section, and installs a context of an application to be subsequently executed in the processing section, from the main memory to the processing section, not through a process by software managing the plurality of applications.

Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.

Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Abstract: When generating a set of tile-lists for use in a tile-based graphics processing system when rendering a scene for display, vertex data is obtained for a plurality of draw calls, and the obtained vertex data is then processed to generate for each of the draw calls data indicative of which tile(s) the primitives associated with that draw call should be rendered for when rendering the scene for display. The vertex data for at least some of the plurality of draw calls can be obtained and processed out of order and/or in parallel and the data is then sorted based on a desired rendering order for the draw calls in order to generating a tile-list identifying the sequence of draw calls to be rendered. In embodiments, the generated data is sorted using a re-ordering buffer.

Abstract: An electronic device is disclosed. The device includes a memory, a communication interface, and a processor configured to change, based on an event for turning off the electronic apparatus, first information indicating support for a fixed rate link (FRL) in EEID information stored in the memory into second information indicating no support for the FRL, and provide the second information to a source device connected through the communication interface.

Abstract: A memory device having an improved booting speed includes: a memory cell array, and a control logic configured to set a memory block as one of a special block for storing special information and a user block for storing user data and configured to store data in a memory block in response to commands from a memory controller, wherein the control logic comprises: a control signal generator configured to generate a special information read signal for reading plural pieces of special information stored in at least two special blocks among the plurality of memory blocks, in response to a special information read command provided by the memory controller, a special information merger configured to read the plural pieces of special information in response to the special information read signal, and a special information storage configured to store the read plural pieces of special information as merged special information.

Abstract: In accordance with an embodiment, described herein is a system and method for loading and transforming data to a cloud database, using a hybrid set-based extract, load, transform approach. During the loading and transforming of large amounts of data, from one or more data sources, a data synchronization application sends small batches of data, in parallel streams, to the database, which operates as a transformation engine to load the data. Each stream can be associated with a separate staging table in the database. For each staging table, the subset of data therein is transformed and loaded, before the next subset is processed. A transform and merge process operating at the database can then be used to transform and merge the data, from each of the staging tables, to the target table.

Abstract: Interfacing with a graphics processing unit (GPU) in a computer system in a transactional manner is disclosed. Discovering feature data regarding the GPU includes determining if the GPU understands transactional-based communication and may be determined by query or by using a look up table (LUT) containing one or more configuration identifiers. Transactions include information including directives to be performed by the GPU and data on which to perform the directives. Transactions may be provided through an application program interface from a user level software module or possibly at the kernel level of an operating system. Transactions may be applied as atomic operations at a discrete point in time to prevent visible glitching or other undesirable display artifacts from being discernable on a display device (e.g., directly connected monitor or remote display device).

Abstract: An apparatus to facilitate an update of shader data constants. The apparatus includes one or more processors to detect a change to one or more data constants in a shader program, generate a micro-code block including updated constants data during execution of the shader program and transmit the micro-code block to the shader program.

Abstract: A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores.

Abstract: Methods are provided for creating objects in a way that permits an API client to explicitly participate in memory management for an object created using the API. Methods for managing data object memory include requesting memory requirements for an object using an API and expressly allocating a memory location for the object based on the memory requirements. Methods are also provided for cloning objects such that a state of the object remains unchanged from the original object to the cloned object or can be explicitly specified.

Abstract: A system and method for binding instructions to a graphical processing unit (GPU) includes a GPU configured to receive bindlessly compiled instructions and interpret the bindlessly compiled instruction at runtime to identify a needed conversion The GPU generates a conversion information based on the bindlessly compiled instruction and needed conversion and converts the bindlessly compiled instruction according to the conversion information to generate a bound format instruction. The GPU may then execute the bound format instruction.

Abstract: System on chip comprising a general purpose processing element, a graphics processing unit and a display interface, supporting graphics visualization on mobile computing devices and on embedded systems.

Abstract: A data processing apparatus includes a first agent which generates a cache dormant indication when a cache is in a dormant state, and a second agent which issues cache maintenance requests for data stored in the cache accessed by the first agent. In response to the cache dormant indication generated by the first agent, the second agent may suppress issuing of cache maintenance requests for the cache accessed by the first agent.

Abstract: An apparatus and method for page table management. For example, one embodiment of an apparatus comprises: a memory management circuit to perform address translations using a page directory, a base page directory address identifying a location of the page directory in a system memory; a cache to reserve a first cache line containing the base page directory address stored in a modified state; cache snoop circuitry to detect a read to the base page directory address by a processor or graphics processing unit (GPU); and locking circuitry to assert a lock signal to change the state of the first cache line to a locked state, the memory management circuit to refrain from performing a page table walk until the lock signal is de-asserted.

Abstract: A method of binding graphics resources is provided that includes: (1) identifying graphics resources for binding, (2) generating a bind group for the graphics resources, (3) organizing the bind group into a bind group memory using a bind group layout and (4) providing bind group control for processing of the bind group. A method of organizing graphics resources and a resource organizing unit are also provided.

Abstract: A computing system includes a memory device comprising a memory array and an internal processor configured to perform a first sub pipeline of a graphics pipeline for tile-based rendering by using graphics data stored in the memory array, for offload processing of the first sub pipeline from a host processor; and the host processor configured to perform a second sub pipeline of the graphics pipeline by using a result of the first sub pipeline stored in the memory array.

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

Abstract: An apparatus and method for extracting and using path shading coherence in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: ray generation logic to generate a ray stream from one or more image tiles; ray sorting logic to sort the rays within the ray stream based on a material identifier (ID) associated with each of the rays to generate a sorted ray stream; and one or more shaders to perform shading operations on rays within the sorted ray stream in an order in which the rays are sorted within the sorted ray stream.

Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

Abstract: In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.

Abstract: One embodiment provides for a graphics processor comprising first logic coupled with a first execution unit, the first logic to receive a first single instruction multiple data (SIMD) message from the first execution unit; second logic coupled with a second execution unit, the second logic to receive a second SIMD message from the second execution unit; and third logic coupled with a bank of shared local memory (SLM), the third logic to receive a first request to access the bank of SLM from the first logic, a second request to access the bank of SLM from the second logic, and in a single access cycle, schedule a read access to a read port for the first request and a write access to a write port for the second request.

Abstract: A processing apparatus is provided that includes a plurality of memory regions each corresponding to a memory address and configured to store data associated with the corresponding memory address. The processing apparatus also includes an accelerated processing device in communication with the memory regions and configured to determine a request to allocate an initial memory buffer comprising a number of contiguous memory regions, create a new memory buffer comprising one or more additional memory regions adjacent to the contiguous memory regions of the initial memory buffer, assign one or more values to the one or more additional memory regions and detect a change to the one or more values at the one or more additional memory regions.

Abstract: Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.

Abstract: A graphics effect data structure and method of use thereof. One embodiment of the graphics effect data structure is embodied in an effect processing system, including: (1) a memory configured to store an effect data structure that describes a graphics effect implemented by a plurality of passes and shader code modules contained in the effect data structure, (2) a graphics processing unit (GPU) operable to render the graphics effect according to a shader program based on the shader code modules, assembled according to the plurality of passes, and (3) a central processing unit (CPU) configured to execute an application that employs the graphics effect and to gain access to the effect data structure during run time, at which time the shader program is passed to the GPU for processing.

Abstract: Apparatus, computer readable medium, integrated circuit, and method of moving a plurality of data items to a first cache or a second cache are presented. The method includes receiving an indication that the first cache requested the plurality of data items. The method includes storing information indicating that the first cache requested the plurality of data items. The information may include an address for each of the plurality of data items. The method includes determining based at least on the stored information to move the plurality of data items to the second cache. The method includes moving the plurality of data items to the second cache. The method may include determining a time interval between receiving the indication that the first cache requested the plurality of data items and moving the plurality of data items to the second cache. A scratch pad memory is disclosed.

Abstract: A video decoding apparatus and method for enhancing video quality of lower resolution than the resolution of a display of a terminal is provided. The video decoding apparatus includes a quality enhancer and a controller. The quality enhancer includes a resizer and quality enhancement filters, each configured to perform a different video quality enhancement operation, and to perform a quality enhancement process on a decoded video with at least one selected enhancement filter from among the quality enhancement filters and perform upscaling with the resizer. The controller selects at least one of the quality enhancement filters to be involved in the quality enhancement and sets up a processing sequence of the resizer and the at least one selected quality enhancement filter.

Abstract: A graphics processing unit is disclosed, the graphics processing unit having a processor having one or more SIMD processing units, and a local data share corresponding to one of the one or more SIMD processing units, the local data share comprising one or more low latency accessible memory regions for each group of threads assigned to one or more execution wavefronts, and a global data share comprising one or more low latency memory regions for each group of threads.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine that a shared surface is shared between a first application and a second application, determine that a fast clear operation has been performed on the shared surface, the fast clear operation comprising clearing one or more locations of one or more buffers. Further, various embodiments may include writing pixel value information to the one or more locations of the one or more buffers and performing a resolve operation on the shared surface.

Abstract: One or more embodiments of the invention set forth techniques to create a process in a graphical processing unit (GPU) that has access to memory buffers in the system memory of a computer system that are shared among a plurality of GPUs in the computer system. The GPU of the process is able to engage in Direct Memory Access (DMA) with any of the shared memory buffers thereby eliminating additional copying steps that have been needed to combine data output of the various GPUs without such shared access.

Abstract: A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

Abstract: An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one of compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory.

Abstract: In a sharing display processing system having a plurality of display processing systems each including one or a plurality of display apparatuses, each display processing system arranges display regions corresponding to the respective display apparatuses on a first memory region shared with another display processing system, arranges contents on a second memory region managed by the self system, extracts a part of the second memory region on which the contents are arranged as an extracted region, and arranges the extracted region on the first memory region. Each display apparatus displays the extracted region arranged within the range of the display region corresponding to itself on the first memory region.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: Various embodiments provide techniques for enabling multiple graphics interfaces to be accessed to perform graphics-related operations. In at least some embodiments, techniques determine if the multiple graphics interfaces can share a memory resource for performing graphics operations. If the multiple graphics interfaces can share the memory resource, a coalescing graphics element is provided that can be used by applications to perform multiple graphics operations.

Abstract: A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a second user environment. Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. Real-time display of applications running in the mobile operating system within an environment of the desktop operating system is provided by rendering the application through an extended graphics context of the mobile operating system. Application graphics for multiple applications are rendered into separate graphics frames.

Abstract: Dynamic configuration of cross-environment applications enhances the computing experience in a computing environment with an extended active user environment and/or multiple active user environments. A mobile computing device maintains multiple active device configurations associated with multiple active user environments and/or application windows within active user environments. Device configuration qualifiers are determined from a variety of sources including device characteristics, device indicators, user settings, and/or application presentation. The mobile computing device selects active resource sets for applications based on the device configuration qualifiers. Application presentation is dynamically updated by disestablishing an application screen and establishing a new active application screen using a different resource set. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel.

Abstract: A mobile computing device with a mobile operating system and desktop operating system running concurrently and independently on a shared kernel without virtualization. The mobile operating system provides a user experience for the mobile computing device that suits the mobile environment. The desktop operating system provides a full desktop user experience when the mobile computing device is docked to a second user environment. Cross-environment rendering and user interaction support provide a seamless computing experience in a multi-operating system computing environment. The seamless computing experience includes mirroring the active user interaction space of the mobile operating system to a display of a user environment associated with the desktop operating system. The mobile computing device may be a smartphone running the Android mobile operating system and a full desktop Linux distribution on a modified Android kernel.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: This disclosure describes communication techniques that may be used within a multiple-processor computing platform. The techniques may, in some examples, provide software interfaces that may be used to support message passing within a multiple-processor computing platform that initiates tasks using command queues. The techniques may, in additional examples, provide software interfaces that may be used for shared memory inter-processor communication within a multiple-processor computing platform. In further examples, the techniques may provide a graphics processing unit (GPU) that includes hardware for supporting message passing and/or shared memory communication between the GPU and a host CPU.

Abstract: A program module executing in a first process space of a mobile computing device receives a buffer request from a graphics driver running in a second process space of the mobile computing device, wherein the second process space is isolated from the first process space. The program module assigns a buffer to the graphics driver to store image data processed by a graphical processing unit (GPU) controlled by the graphics driver. The program module receives a release of the buffer from the graphics driver. The program module assigns the buffer to a media encoder driver for a hardware media encoder to encode the image data in the buffer into a file.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

Abstract: A method and system are disclosed for automatic instrumentation that modifies a video game's shaders at run-time to collect detailed statistics about texture fetches such as MIP usage. The tracking may be transparent to the game application and therefore not require modifications to the application. In an embodiment, the method may be implemented in a software development kit used to record and provide texture usage data and optionally generate a report.

Abstract: Many computing device may now include two or more graphics subsystems. The multiple graphics subsystems may have different abilities, and may, for example, consume differing amount of electrical power, with one subsystem consuming more average power than the others. The higher power consuming graphics subsystem may be coupled to the device and used instead of, or in addition to, the lower power consuming graphics subsystem, resulting in higher performance or additional capabilities, but increased overall power consumption. By transitioning from the use of the higher power consuming graphics subsystem to the lower power consuming graphics subsystem, while placing the higher power consuming graphics subsystem in a lower power consumption mode, overall power consumption is reduced.

Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.

Abstract: Disclosed is a method of processing a digital representation comprising a plurality of cells having respective cell values and being arranged in a regular grid. The method comprises performing at least one cell data reordering operation and performing at least one arithmetic operation for computing at least a first cell value of a first cell from one or more cell values of respective cells of the digital representation, each arithmetic operation including at least one multiplication. The method comprises performing the at least one reordering operation and the at least one arithmetic operation as at least two concurrent processes, each of the concurrent processes reading respective parts of the digital representation from respective memory buffers of a shared memory.