Abstract: A display device includes a first processor, a second processor, and a display module. The first processor is configured to: acquire version information of the second processor upon completion of startup of the second processor; determine version information of the corresponding first processor based on version information of the second processor; load a second configuration file corresponding to the version information of the first processor to output a second display screen associated with the second configuration file to the display module. The display module is configured to display the second display screen.

Abstract: A controller for controlling a memory device including memory cells, the controller includes: a memory suitable for storing offset level information which is determined based on a sample read level according to characteristics of the memory cells and Gaussian modeling of the memory cells; and a processor suitable for generating an estimated read level based on the Gaussian madding and data read from the memory cells, and applying a compensated read voltage to control the memory device to perform read operations of the memory cells, wherein the compensated read voltage is generated by applying the offset level information to the estimated read level.

Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing, section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-convert d are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed.

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed.

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed.

Abstract: In layered Visual Dynamic range (VDR) coding, inter-layer prediction requires several color-format transformations between the input VDR and Standard Dynamic Range (SDR) signals. Coding and decoding architectures are presented wherein inter-layer prediction is performed in the SDR-based color format, thus reducing computational complexity in both the encoder and the decoder, without compromising coding efficiency or coding quality.

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed.

Abstract: In a high speed image capturing state, a camera signal processing circuit is not needed to perform a signal process at a high screen rate, but at a regular screen rate. In the high speed image capturing mode, raw data of 240 fps received from an image sensor 101 are recorded on a recording device 111 through a conversion processing section 201 and a recording device controlling circuit 210. Raw data that have been decimated and size-converted are supplied to a camera signal processing circuit 203 through a pre-processing circuit 202 and an image being captured is displayed on a display section 112 with a signal for which a camera process has been performed.

Abstract: A module may provide codec-independent services including determining frame display order, frame dependency sets, and queuing the dependency frames in advance so as to enable display of a video. The module enables a video to be played forwards or backwards at a variety of playback speeds from any position within the video. In one implementation, a device communicatively coupled to a plurality of decoders accesses a video that includes a plurality of frames. One or more of the frames are decodable by one or more of the communicatively coupled decoders. The device identifies a frame in the video that is to be displayed, and determines a plurality of dependency frames in the video upon which decoding of the frame to be displayed depends. The device provides an indication that one or more associated dependency frames are to be decoded.

Abstract: An embodiment of the present invention includes a device for real-time graphics processing. The device includes an interface coupled to exterior for receiving external data. The device includes a data converter coupled to the interface for converting the external data received from the interface. The device includes a graphics processing unit coupled to the data converter to process the external data that has been converted.

Abstract: A video processing apparatus includes a control unit, a storage device, a video decoder and a video processor. The control unit is arranged for generating a color depth control signal. The video decoder is coupled to the storage device, and arranged for decoding an encoded video bitstream and accordingly generating decoded video pictures (sequence) to the storage device. The video processor is coupled to the control unit and the storage device, and arranged for referring to the color depth control signal to enable a target video processing mode selected from a plurality of supported video processing modes respectively corresponding to different output color depths, and processing picture data derived from the data buffered in the storage device under the target video processing mode to generate output video pictures (sequence) to a display apparatus.

Abstract: This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques for performing hierarchical z-culling may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques for performing hierarchical z-culling may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.

Abstract: A hybrid display frame buffer for a display subsystem. An embodiment of an apparatus a first logic to split a video image into a first data portion and a second data portion; a display frame buffer including a first memory component having a first type of memory and a second memory component having a second type of memory, the first logic to write the first data portion to the first memory component and the second data portion to the second memory component; and a second logic to read the first data portion from the first memory component and the second data component from the second memory component, and to combine the first data portion and the second data portion to generate a combined video image.

Abstract: A 3D image capturing device and a controller chip thereof. The controller chip includes a first and a second sensor interface, a pixel data synchronization module, a 3D image generator and an output interface. The first and second sensor interfaces are coupled to a first and a second 2D image capturing device, respectively, to receive a first and a second image. The pixel data synchronization module synchronizes the pixel data of the first and second images. Based on the synchronized first and second images, the 3D image generator generates a 3D-image. By the output interface, the 3D-image capturing device transmits the generated 3D image to be received by a host.

Abstract: When a display target determination unit determines image data to be displayed, a reproduction control unit identifies the type of the image data to be displayed. The reproduction control unit divides the region of a display buffer according to the identified type. While an image display control unit displays an image, on a display device, by using image data stored in a spare buffer, a decoding execution unit decodes said image data and stores the decoded image data in a divided region of the display buffer.

Abstract: An apparatus generally having a plurality of memories and a first circuit is disclosed. The memories may be configured to store a plurality of first data points. The first data points generally form a two-dimensional block. The first data points may be arranged among the memories such that a load cycle from the memories accesses a rectangular region of the two-dimensional block. The load cycle generally comprises a plurality of read cycles, a different one of the read cycles corresponding to each one of the memories. The first circuit may be configured to (i) receive the first data points as read from the memories and (ii) generate a plurality of second data points by a video codec transformation of the first data points between a spatial domain and a frequency domain.

Abstract: The video output system in a computer system reads pixel information from a frame buffer to generate a video output signal. In addition, a full-motion video may also be displayed. Reading from both the frame buffer and the full-motion video buffer when displaying the full-motion video window wastes valuable memory bandwidth. Thus, the disclosed system provides a system and methods for identifying where the video output system must read from the frame buffer and where it must read from the full-motion video buffer while minimizing the amount of area it reads from both the frame buffer and the full-motion video buffer.

Abstract: An electronic device has a display, a video memory, a video data buffer unit, a central processing unit, and a video processing unit. The central processing unit, according to a number of divided screens and a resolution for each of the divided screens, retrieves different but continuous video data corresponding to the resolution of each of the divided screens from the video data buffer unit, and stores the retrieved continuous video data in consecutive memory addresses in the video memory. The video processing unit reads in sequence the continuous video data stored in the video memory, and sends the continuous video data in sequence to the display according to a direction of arrangement of the divided screens such that video contents displayed on the divided screens by the display are continuous.

Abstract: Embodiments include a single integrated circuit comprising: a first display controller configured to control a non-bistable display screen; and a second display controller configured to control a bistable display screen. Embodiments also include disposing, on a single integrated circuit, a first display controller capable of controlling a non-bistable display screen; and a second display controller capable of controlling a bistable display screen.

Abstract: A method encodes or decodes a frame (also file), such as a video, graphic, media, or other frame or data, representing a real-time graphic output from a frame buffer, output by a video camera, or another file or data. The file includes frames each comprising macroblocks. Reference frame buffers (PFTs), virtual frame buffer tables (VFTBs) of equal number to the PFTs, each VFTB corresponds to a respective PFT, and respective sectors of each PFT for respective macroblocks are created. Frames of the file are encoded/decoded by successive encode/decode of macroblocks. A pointer is created in the VFBT associated with the PFT rather than encoding/decoding any matching macroblock. The pointer and its reference are relied on for each already encoded/decoded macroblock retained in the PFT. Processing, memory, bandwidth and power requirements for encoding or decoding are reduced.

Abstract: A frame-rate conversion system having an interpolation mode and a synchronization mode. The synchronization mode is selected when temporal interpolation confidence is and images can be retimed without dropping or repeating of images. The interpolation mode is selected when the measure of temporal interpolation confidence is high or repeating of images. Images are exchanged between a temporal interpolator and a buffer at an exchange rate which is varied in the interpolation mode to optimise the buffer occupancy for retiming of images without dropping or repeating of images in s subsequent synchronization.

Abstract: A display comprises a front-end component having light shutters and a plurality of backlight devices, wherein the display operates in a full screen video display mode and partial screen energy-saving auxiliary mode. In the full screen video display mode, the backlight devices are activated and in the partial screen energy-saving auxiliary mode, at least one backlight device is not activated. In the auxiliary mode, the light shutters can control luminance or the light shutters along with attenuating the backlight device control luminance. In the auxiliary mode, the backlight devices are driven via enabled inputs, a digital bus system, or an analog control signal.

Abstract: A videoconference may be initiated between a plurality of endpoints. At least one of the endpoints may be coupled to a recording server, which may be configured to record the videoconference. A configuration may be selected (e.g., automatically or manually) for performing the recording. The endpoint (e.g., acting as an MCU) may transmit information to endpoints and may transmit recording information to the recording server. The recording information may be different from the videoconference information. For example, it may be in a “streaming friendly” format, at a different bit rate, encoded differently, have different inputs, etc. The manner in which the videoconference is stored and/or recorded may be based on the selected configuration. Clients may be configured to receive and display the videoconference from the recording server and may be configured to change the provided layout to different layouts, e.g., based on user input.

Abstract: A novel method for driving a display device in which generation of flickers caused by rewriting pixels is reduced and which has a high aperture ratio is provided. The driving method includes a first step of determining whether displayed still image data is two-valued still image data or multivalued still image data, and a second step of performing display by rewriting (refreshing) the two-valued still image data with lower frequency than the multivalued still image data.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: When updating an impulse-driven, electrophoretic display, a pixel synthesis operation is started first. After a first quantity of synthesized pixels has been generated, a display output operation is started. After generating the first quantity of synthesized pixels, the first frame of the display output operation is performed at substantially the same time as the pixel synthesis operation.

Abstract: The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Abstract: A display control device for controlling a display panel includes a contents frame rate detector detecting a contents frame rate of an input image data and outputting a repetitive frame number dependent from a display frame rate of the display panel and the detected contents frame rate; a frame memory for storing a level data of a previous frame; and an emulated level generator in communication with the contents frame rate detector and the frame memory. An output level data to the display panel is generated according to the repetitive frame number from the contents frame rate detector, the previous level data from the frame memory and an input level data of the input image data.

Abstract: Methods and device for in-system firmware update in an information output device are provided. In one aspect, a method of firmware update in a display device receives a set of data in an image format through a video signal input channel of an input port of the display device. The set of data is converted from the image format to an instruction set format that is different from the image format. A first set of instructions that is used to operate the display device is updated with the set of data in the instruction set format.

Abstract: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or written to the shared buffer; and when it is determined that the first instruction causes data to be read from or written to the shared buffer, 1) identify one or more replacement instructions to execute in place of the first instruction; 2) store the one or more replacement instructions; and 3) replace the first instruction at the first memory location with a second instruction that, when executed, causes the stored one or more replacement instructions to be executed.

Abstract: An image display device includes a timing controller capable of overdriving. The timing controller has three line buffers, an image reverse processing unit, and an overdrive unit. The first line buffer buffers first line data of a second frame, wherein the second frame is generated later than a first frame. The second line buffer buffers first compressed data. The image reverse processing unit estimates first and second line data of the first frame according to the first compressed data. According to the first and second line data of the first and second frames, the overdrive unit outputs first and second lines of interleaving data for an interleaving frame. The interleaving frame is inserted between the first and second frames. With the third line buffer, the timing controller outputs the first and second lines of interleaving data at different time point.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: A system and method for converting data from one format to another in a processing pipeline architecture. Data is stored in a shared cache that is coupled between one or more clients and an external memory. The shared cache provides storage that is used by multiple clients rather than being dedicated to separately convert the data format for each client. Each client may interface with the memory using a different format, such as a compressed data format. Data is converted to the format expected by the particular client as it is read from the cache and output to the client during a read operation. Bytes of a cache line may be remapped to bytes of an unpack register for output to a naïve client, which may be configured to perform texture mapping operations. Data is converted from the client format to the memory format as it is stored into the cache during a write operation.

Abstract: An image converter converts an image rendered at a given vertical synchronous frequency into an image compatible with the specification of a display. A frame memory holds the image converted by the image converter by switching a plurality of buffers. A display controller selects one of the buffers in accordance with the vertical synchronous frequency of the display, and scans out the image from the frame memory accordingly. A switch instruction issuing unit issues a frame buffer switch instruction for designating a frame buffer to scan out from subsequently, in synchronization with the vertical synchronous frequency of the display, instead of immediately after the execution of an image converting process by the image converter.

Abstract: A portable display device transitions between a first and second state. The device has a display portion, a power source for supplying power in the first state and supplying less power in the second state than in the first state, a controller that drives the display portion, an operation portion that executes commands, and a mode storage portion that stores one of a first and second mode. The first mode corresponds to displaying preset information, and the second mode corresponds to particular information to be continuously displayed. The particular information is information displayed in the display portion when the device is in the first state. When the device is in the second state, the preset information is displayed in the display portion when the first mode is stored in the mode storage portion, and the particular information is continuously displayed when the second mode is stored in the mode storage portion.

Abstract: Described are a video graphics system, graphics processor, and methods for rendering three-dimensional objects. A buffer is partitioned into tiles of pixels. Each pixel of each tile includes at least one sample. A primitive is received and determined to cover fully one of the tiles. A section of the primitive that maps to the fully covered tile is tested to determine if every sample within the fully covered tile is to undergo the same stencil operation. The stencil operation is performed on the fully covered tile in the buffer if every sample within the fully covered tile is to undergo the same stencil operation.

Abstract: A computer-program product may have instructions that, when executed, cause a processor to perform operations including managing execution of application functions that access data in a shared buffer; determining if a first instruction that is stored at a first memory location causes, upon execution, data to be read from or written to the shared buffer; and when it is determined that the first instruction causes data to be read from or written to the shared buffer, 1) identify one or more replacement instructions to execute in place of the first instruction; 2) store the one or more replacement instructions; and 3) replace the first instruction at the first memory location with a second instruction that, when executed, causes the stored one or more replacement instructions to be executed.

Abstract: A floating point rasterization and frame buffer in a computer system graphics program. The rasterization, fog, lighting, texturing, blending, and antialiasing processes operate on floating point values. In one embodiment, a 16-bit floating point format consisting of one sign bit, ten mantissa bits, and five exponent bits (s10e5), is used to optimize the range and precision afforded by the 16 available bits of information. In other embodiments, the floating point format can be defined in the manner preferred in order to achieve a desired range and precision of the data stored in the frame buffer. The final floating point values corresponding to pixel attributes are stored in a frame buffer and eventually read and drawn for display. The graphics program can operate directly on the data in the frame buffer without losing any of the desired range and precision of the data.

Abstract: Systems and methods for converting between a first color space format and a second color space format are described herein. The system receives a video cell in a first color space format comprising a plurality of pixels. Each pixel in the cell has a luminance value and a chrominance value. The luminance values of each pixel are compared to determine the brightest pixel in the received cell. The cell is downsampled to generate a second cell in a second color space format. The second cell in the second color space format comprises a downsampled chrominance value that is computed based at least in part on the chrominance value of the brightest pixel. The method advantageously reduces tinting of a high intensity pixel by the chrominance component of a neighboring low-intensity pixel.

Abstract: A graphics processing apparatus 2 includes graphics processing pipelines 8. The graphics processing pipelines 8 include a programmable hardware stage 12, a pipeline memory 22 and writeback circuitry 16. Programmable resolving circuitry 18 is provided by the programmable hardware stage 12 within each pipeline and is responsive to one or more graphics program instructions to read pixel values at a first resolution generated within the pipeline memory 22 by pixel value generating circuitry 18 provided by the programmable hardware stage 12 and to perform a resolving operation upon these pixels values so as to generate pixel values at a second resolution. These pixel values at the second resolution are then written back to a frame buffer memory 6.

Abstract: A system and method for adjusting pictures minimizes the impact on graphics processing performance of a discrete processor. A hybrid system configuration includes the discrete processor and an integrated processor, where the discrete processor typically consumes more power and provides greater processing performance compared with the integrated processor. A picture is produced by a video or graphics engine of a discrete processor within a hybrid system. Each picture is then transferred to a back buffer in the host processing memory. The picture is analyzed to produce picture analysis results that are used to generate adjustment settings. The back buffer is swapped to become the front buffer and the adjustment settings are applied to the picture by an integrated processor to display an adjusted picture. The adjustment may be used in conjunction with power saving techniques to maintain the image quality when display backlighting is reduced.

Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.

Abstract: Apparatus and a method for communicating media over a network including encoding the media into a server database at a server, downloading from the server database to a client database generally only those portions of the media which are necessary to satisfy user requests and in response to a user request for a given item of media, determining whether the media is present in the client database, and if not, automatically downloading those portions of the media which are necessary to supply the user with the given item of media from the server database.

Abstract: A method of generating illumination characteristic data around an image display device, includes making predetermined illumination characteristic data around the image display device into a data format comprising a type block and an illuminance block. The type block indicates information on a type of illumination, and the illuminance block indicates information on the illuminance of illumination.

Abstract: The present invention includes a method and device that allows efficient mixing of multiple video images with a graphics screen while utilizing only one video buffer. The present invention partitions the sole video buffer, pre-scales the plurality of video images and inserts them into the partitioned video buffer in a predetermined range of buffer addresses. The present invention mixes the partitioned video including the pre-scaled video images with the graphics screen to produce a video display including both a video screen and a graphics screen.

Abstract: Techniques for adaptively accessing image data in a data memory space are disclosed. According to one aspect of the present invention, a data transfer bandwidth between a display controller and a memory device is detected to obtain bandwidth characteristics. An image format to be used is determined by comparing the bandwidth characteristics with a preset mapping relationship between at least two image formats and the bandwidth characteristics. A current image format is updated by the determined image format to be used if the determined image format to be used is different from the current image format. The image data in the memory is then read out according to the current image format.

Abstract: A method and system for rendering a desktop on a computer using a composited desktop model operating system are provided. A composited desktop window manager, upon receiving base object and content object information for one or more content objects from an application program, draws the window to a buffer memory, and takes advantage of advanced graphics hardware and visual effects to render windows based on content on which they are drawn. The frame portion of each window may be generated by pixel shading a bitmap having the appearance of frosted glass based on the content of the desktop on top of which the frame is displayed. Legacy support is provided so that the operating system can draw and render windows generated by legacy applications to look consistent with non-legacy application windows.

Abstract: A method and system are disclosed for synchronizing graphics processing events in a multi-GPU computer system. A master GPU renders a first image into a first portion of a master buffer associated with a display interface, and then writes a first predetermined value corresponding to the first image in a first memory unit. A slave GPU renders a second image into a slave buffer, and then transfers the second image to a second portion of the master buffer, and writes a second predetermined value corresponding to the second image in the first memory unit. The first and second predetermined values represent a queuing sequence of the rendered images. The master GPU flips the first image to display only after examining the first predetermined value in the first memory unit, and flips the second image to display only after examining the second predetermined value in the first memory unit.

Abstract: A three-dimensional graphics data rendering method. The method divides initially inputted first graphics data into a static object and a dynamic object, performs a rendering process with respect to the static object, and updates a predetermined buffer with the rendering result. Then the method performs a transformation process, a portion of the rendering process with respect to the dynamic object, determines an updating area, and stores a rendering result of the buffer corresponding to the updating area in a predetermined storage unit; performs a remaining rendering process with respect to the dynamic object, updates the buffer and outputs a first image whose rendering is completed. Finally, the method restores a rendering result of the updating area to the buffer by referring to the storage unit and utilizes a rendering result of the restored buffer as a rendering result of subsequently inputted second graphics data.