Display List Memory Patents (Class 345/553)
  • Patent number: 10095521
    Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises execution logic to execute a plurality of instructions including an accelerator invocation instruction to invoke one or more accelerator commands. The accelerator invocation instruction stores command data specifying the command within a command register. One or more accelerators read the command data from the command register and responsively attempt to execute the command identified by the command data. Upon a switch from a first context to a second context, an accelerator context save/restore pointer identifies a region within system memory where the accelerator is to save its state and later the accelerator context save/restore pointer aids in restoring its state upon returning to the first context.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Oren Ben-Kiki, Ilan Pardo, Robert Valentine, Eliezer Weissmann, Dror Markovich, Yuval Yosef
  • Patent number: 9601092
    Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Thomas A. Piazza, Bimal Poddar
  • Patent number: 9336555
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for optimizing a display list. Graphics processing commands are identified for generation of one or more graphical images on a computer device. During an initial recording of a graphics display list to include the graphics processing commands, if a sub-list of the display list is determined to not include any drawing commands, the display list is recorded so that commands on the sub-list are not executed when the display list is executed.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: May 10, 2016
    Assignee: Google Inc.
    Inventor: Romain P. Guy
  • Patent number: 9041524
    Abstract: A technique for enabling scenario files and image files for supply to a scenario generating device to be created easily is provided. The scenario creating device creates a scenario file supplied to a scenario reproducing device capable of reproducing only image files of a predetermined format. The scenario creating device comprises: an input section including a pointing device; a display section; and a scenario creating section for creating the scenario file. The scenario creating section provides a display of an execution icon on the display screen for causing the scenario creating section to execute a process. When a file icon for a source file of a predetermined format including pagewise scenario information and image information is dragged and dropped on the execution icon by means of operation of the pointing device, a scenario file is created on the basis of the scenario information, and an image file of the predetermined format is generated on the basis of the image information.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 26, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Toru Karasawa, Shoichi Akaiwa, Miki Nagano
  • Patent number: 9041721
    Abstract: A system, method, and computer program product are provided for evaluating an integral utilizing a low discrepancy sequence and a block size. In use, a low discrepancy sequence and a block size are determined. Additionally, an integral is evaluated, utilizing the low discrepancy sequence and the block size.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 26, 2015
    Assignee: NVIDIA Corporation
    Inventors: Alexander Keller, Nikolaus Binder
  • Patent number: 9001891
    Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Martin Schlockermann, Bernhard Schuur, Shinya Kadono
  • Patent number: 8989264
    Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Martin Schlockermann, Bernhard Schuur, Shinya Kadono
  • Patent number: 8982134
    Abstract: A method and device are provided for performing tile based rendering. The method and device analyze past and current commands to determine when tiles are renderable independently of other tiles. In such cases, all rendering passes are performed successively without rendering other tiles in between.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 17, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William W. Licea-Kane
  • Patent number: 8933963
    Abstract: A system may include a memory that stores instructions and a processor to execute the instructions to create a first set of objects, describing a graphical scene, in a first data structure based on data relating to the graphical scene. The processor may create a second set of objects in a second data structure based on the first set of objects in the first data structure, where at least one object of the first set of objects is associated with at least one object of the second set of objects and one or more properties for an object of the second set of objects is based on information associated with the first data structure. The processor may modify the second set of objects and provide the modified second set of objects to a browser for rendering the graphical scene.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: January 13, 2015
    Assignee: The MathWorks, Inc.
    Inventor: Michael P. Garrity
  • Patent number: 8902242
    Abstract: Remote desktop servers include a display encoder that maintains a secondary framebuffer that contains display data to be encoded and transmitted to a remote client display and a list of display primitives effectuating updated display data in the secondary framebuffer. The display encoder submits requests to receive the list of drawing primitives to a video adapter driver that receives and tracks drawing primitives that, when executed, update a primary framebuffer.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 2, 2014
    Assignee: VMware, Inc.
    Inventors: Dustin Byford, Anthony Cannon, Ramesh Dharan
  • Patent number: 8890879
    Abstract: A system may include a processor and memory that stores instructions to cause the processor to create a first set of objects in a first structure based on first data, where the first set of objects describes a graphical scene specified by the first data. The processor may add a command for at least one object, of the first set of objects, to a composite command that includes commands for the graphical scene and create a second set of objects in a second structure based on the first set of objects in the first structure and the composite command. The processor may receive second data, change one or more objects of the first set of objects based on the second data, and change one or more objects of the second set of objects based on the changes to the one or more objects of the first set of objects. The processor may further provide the changed second set of objects to a browser for rendering a new graphical scene.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: November 18, 2014
    Assignee: The MathWorks, Inc.
    Inventor: Michael Patrick Garrity
  • Patent number: 8836710
    Abstract: There is provided a method and apparatus for managing memory in a system for generating 3-dimensional computer images. The image is subdivided into a plurality of rectangular areas. A memory is provided and a page of the memory is allocated for storing object data for objects in the image. Object data for objects in the image are then written to the allocated page of memory. Finally, a bit mask for the allocated page of memory is compiled, the bit mask indicating the rectangular areas having object data stored in the allocated page of memory. A rectangular area of the image can then be rendered by deriving data for display from the object data stored in the memory, for objects in that rectangular area. Once the rectangular area has been rendered, the bit mask for each page of memory which stored, before the step of rendering, object data for that rectangular area, is updated so that the bit mask no longer indicates that rectangular area.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Imagination Technologies, Limited
    Inventor: Jonathan Redshaw
  • Patent number: 8797457
    Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: August 5, 2014
    Assignee: Entropic Communications, Inc.
    Inventor: Andrew Stevens
  • Patent number: 8704836
    Abstract: One embodiment of the present invention sets forth a technique for parallel distribution of primitives to multiple rasterizers. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives from the multiple geometry units concurrently to multiple rasterizers at rates of multiple primitives per clock. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: April 22, 2014
    Assignee: NVIDIA Corporation
    Inventors: Johnny S. Rhoades, Steven E. Molnar, Emmett M. Kilgariff, Michael C. Shebanow, Ziyad S. Hakura, Dale L. Kirkland, James Daniel Kelly
  • Patent number: 8707132
    Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akio Nakagawa, Hisashi Ishikawa
  • Patent number: 8669987
    Abstract: Memory management system and method for use with systems for generating 3-dimensional computer generated images are provided.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: March 11, 2014
    Assignee: Imagination Technologies, Ltd.
    Inventors: Jonathan Redshaw, Steve Morphet
  • Patent number: 8514247
    Abstract: A system includes a memory, a specialized processing unit and a processor. The processor receives data from a user and creates a first set of objects in a first structure based on the data. The system further creates, contemporaneously with the creation of the first set of objects and based on the first set of objects in the first structure, a second set of objects in a second structure, where the second set of objects is optimized for use by the specialized processing unit, and stores the first and second sets of objects in the memory. The specialized processing unit executes an algorithm based on the second set of objects.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 20, 2013
    Assignee: The MathWorks, Inc.
    Inventor: Michael P. Garrity
  • Patent number: 8508759
    Abstract: A communication apparatus includes a first reception unit which receives an instruction from a server, a second reception unit which receives an instruction from a path other than the server, an executing unit which executes a function when the first reception unit receives a first execution instruction from the server or when the second reception unit receives a second execution instruction from the path other than the server, and a display control unit which displays a display instruction correspondence screen when the first reception unit receives a display instruction from the server, and which displays an execution correspondence screen when the executing unit executes the function. During a time period while the display instruction correspondence screen is being displayed, the display control unit displays the execution correspondence screen when receiving the first execution instruction, but doesn't display the execution correspondence screen when receiving the second execution instruction.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: August 13, 2013
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Yutaka Urakawa
  • Patent number: 8463244
    Abstract: A display apparatus for use in a wireless terminal is provided. A memory stores user interface (UI) data for cases mapped to events occurring in the wireless terminal. A controller collects the events occurring in the wireless terminal. The controller selects at least one executable case for the collected events. The controller selects UI data including a character image for the at least one selected executable case from the memory and outputs the selected UI data. A display unit displays the UI data.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Ho Kim, Jeong-Wook Seo, Sung-Pil Kim, Hyun-Ji Kim, Sang-Min Park
  • Patent number: 8358315
    Abstract: A method and an apparatus for mirroring a frame are provided. The method is suitable for a display device having a first storage unit and a second storage unit. In the present method, pixel values of a pixel row of the frame are read from the first storage unit and written into the second storage unit. Then, the pixel values of the pixel row of the frame are read from the second storage unit and written back to the first storage unit. When performing one of foregoing reading and writing steps, the pixel values of the pixel row are read or written in a reverse direction to mirror the pixel row. Finally, foregoing steps are repeated to mirror each pixel row of the frame, so as to mirror the entire frame.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: January 22, 2013
    Assignee: Novatek Microelectronics Corp.
    Inventor: Li-Chun Huang
  • Patent number: 8314813
    Abstract: A system includes a memory, a specialized processing unit and a processor. The processor receives data from a user and creates a first set of objects in a first structure based on the data. The system further creates, contemporaneously with the creation of the first set of objects and based on the first set of objects in the first structure, a second set of objects in a second structure, where the second set of objects is optimized for use by the specialized processing unit, and stores the first and second sets of objects in the memory. The specialized processing unit executes an algorithm based on the second set of objects.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: November 20, 2012
    Assignee: The Mathworks, Inc.
    Inventor: Michael Patrick Garrity
  • Patent number: 8207973
    Abstract: An electronic device is disclosed. The electronic device comprises a transmitter, a converter, and a receiver. The transmitter transmits data and a control signal. The converter receives the control signal from the transmitter and converts the control signal. The receiver receives the data from the transmitter via a data bus isolated from the converter and receives the converted control signal from the converter. The data transmitted from the transmitter is directly electrically connected to the receiver.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: June 26, 2012
    Assignee: Mediatek Inc.
    Inventors: Chang-Fu Lin, Shu-Wen Teng, Cheng-Che Chen, Wei-Cheng Gu
  • Patent number: 8139637
    Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: March 20, 2012
    Assignee: Panasonic Corporation
    Inventors: Martin Schlockermann, Bernhard Schuur, Shinya Kadono
  • Patent number: 8130239
    Abstract: A system stores a first object tree that describes a graphical scene in memory and creates a second object tree based on the first object tree, where the second object tree is optimized for use by a graphics processing unit (GPU) to render a graphical scene. The system receives indications of one or more changes associated with the first object tree and traverses the first object tree to make the one or more changes to the first object tree and to generate a composite command for use in making corresponding changes in the second object tree. The system executes the composite command to make the corresponding changes in the second object tree.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 6, 2012
    Assignee: The Mathworks, Inc.
    Inventor: Michael Patrick Garrity
  • Publication number: 20110298815
    Abstract: A method and apparatus for displaying image data is disclosed. The method includes receiving one of a plurality of sets of stored image update data to be displayed on a display device, wherein each set corresponds to one image in a sequence of images and wherein the plurality of sets of image update data comprise information identifying pixels that change from a previous image in the sequence of images, wherein the display device comprises an array of bi-stable display elements. The method further includes updating a portion of the display device, the portion containing the pixels identified in the received set of stored image update data.
    Type: Application
    Filed: August 15, 2011
    Publication date: December 8, 2011
    Applicant: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventor: Jeffrey B. Sampsell
  • Patent number: 7999813
    Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system for performing graphics processing is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors can perform graphics processing on a first set of graphics data to generate a second set of graphics data, and another of the second processors can perform graphics processing on the second set to generate a third set of graphics data.
    Type: Grant
    Filed: October 18, 2004
    Date of Patent: August 16, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Masakazu Suzuoki, Takeshi Yamazaki
  • Patent number: 7925306
    Abstract: Embodiments of a system and method for providing a preview of the content of messages (e.g. electronic mail messages) to users of mobile devices. A portion of the message body of a message associated with a user-identified list entry of a message list is shown in an area of a display screen (e.g. in a window) that overlaps the area in which one or more list entries of the message list is displayed.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: April 12, 2011
    Assignee: Research In Motion Limited
    Inventors: Michael James Carmody, Anthony Fabian Scian, Ian Michael Robertson
  • Patent number: 7898549
    Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: March 1, 2011
    Assignee: NVIDIA Corporation
    Inventors: Ross A. Cunniff, Matthew J. Craighead
  • Patent number: 7852341
    Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: December 14, 2010
    Assignee: Nvidia Corporation
    Inventors: Christian Rouet, Rui Bastos, Lordson Yue
  • Patent number: 7825935
    Abstract: A system, method and computer program product are provided for retrieving instructions from memory utilizing a texture module in a graphics pipeline. During use, an instruction request is sent to memory utilizing a texture module in a graphics pipeline. In response thereto, instructions are received from the memory in response to the instruction request utilizing the texture module in the graphics pipeline.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 2, 2010
    Assignee: NVIDIA Corporation
    Inventors: Christopher D. S. Donham, Edward Hutchins, Alexander Minkin, George E. Scott, III
  • Patent number: 7800622
    Abstract: A method and apparatus for selective control of display data sequencing in a mobile computing device is disclosed. The method may include storing a plurality of display data sequencing instruction sets in a memory of the mobile computing device, each of the display data sequencing instruction sets being usable for transferring data in accordance with a different sequencing of display data than other ones of the display data sequencing instruction sets, receiving an indication of a particular type of display data sequencing to be used, selecting one of the display data sequencing instruction sets based on the received indication of the particular type of display data sequencing to be used, transferring data for display based on the selected one of the display data sequencing instruction sets, and controlling the transfer of data to the display device in order to synchronize the data transfer with the data and timing requirements of the display device.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: September 21, 2010
    Assignee: Motorola, Inc.
    Inventors: Jon Schindler, Irfan Nasir
  • Patent number: 7760803
    Abstract: A video encoder (70) for coding moving pictures comprising a buffer (16c) with a plurality of memory areas capable of storing frames composed of top fields and bottom fields, a motion estimation unit (19) operable to code, field by field, inputted pictures performing moving estimation and moving compensation by referring, field by field, to the picture data stored in a memory area, a motion compensation unit (16d), a subtractor (11), a transformation unit (13) and a quantization unit (14), a memory management unit (71) operable to manage, frame by frame, a plurality of memory areas, an inverse quantization unit (16a) and inverse discrete cosine transform unit (16b) operable to decode picture data in coded fields and store the picture data in the decoded field in any of the plurality of memory areas under the management by the memory management unit (71).
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: July 20, 2010
    Assignee: Panasonic Corporation
    Inventors: Martin Schlockermann, Bernhard Schuur, Shinya Kadono
  • Publication number: 20100177105
    Abstract: In a tile-based graphics processor, primitive lists (bins) are prepared for 2×2 blocks of tiles 40. The processor also determines and stores for each primitive in a bin, distribution information indicating the distribution of the primitive within the set of tiles that the bin corresponds to. Thus a primitive 42 that is found by its bounding box 43 to reside in two of the four tiles that make up the set of 2×2 tiles 40 is also associated with a tile coverage bitmap of the form “0101” to indicate that it lies in tiles “1” and “3” of the 2×2 group of tiles 40. The graphics processor uses the coverage bitmap (information) to determine whether a primitive should be processed for the tile currently being processed.
    Type: Application
    Filed: January 12, 2010
    Publication date: July 15, 2010
    Applicant: ARM Limited
    Inventors: Jørn NYSTAD, Frank Langtind, Joe Tapply, Daren Croxford
  • Patent number: 7742054
    Abstract: A display module for displaying information on a screen, using a display data structure, wherein the display data structure is a doubly linked list. A display space in defined in video memory and the display space is filled by sequentially copying at least a portion of a set of characters from the display data structure into the video memory.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: June 22, 2010
    Inventor: Jacques Nault
  • Patent number: 7719539
    Abstract: A 3-dimensional computer generated image is generated by subdividing the image into a plurality of rectangular areas. Object data for each rectangular area is loaded into a display list memory until that memory is substantially full. Image data and shading data for each picture element of each rectangular area are derived by an image synthesis processor from the object data. The image data is then stored in a local memory. Additional object data is loaded into the display list memory and replaces existing contents. Then, the stored image data and the shading data are retrieved, and additional image data and shading data are derived for each picture element by the image synthesis processor using the additional object data and the previously derived image and shading data. When there is no further object data to load to the display list memory, the shading data is provided for display for the rectangular areas by a frame buffer.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: May 18, 2010
    Assignee: Imagination Technologies Limited
    Inventor: Stephen Morphet
  • Patent number: 7701461
    Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Techniques for efficiently buffering graphics data between a producer and a consumer within a low-cost graphics systems such as a 3D home video game overcome the problem that a small-sized FIFO buffer in the graphics hardware may not adequately load balance a producer and consumer—causing the producer to stall when the consumer renders bit primitives. One aspect of the invention solves this invention by allocating part of main memory to provide a variable number of variable sized graphics commands buffers. Applications can specify the number of buffers and the size of each. All writes to the graphics FIFO can be routed a buffer in main memory. The producer and consumer independently maintain their own read and write pointers, decoupling the producer from the consumer.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: April 20, 2010
    Assignee: Nintendo Co., Ltd.
    Inventors: Farhad Fouladi, Robert Moore
  • Publication number: 20100079474
    Abstract: A method for rendering source content of a file for display in a destination figure is provided. The method may include receiving the source content of the file including a brush that defines a viewbox having a first coordinate system, composing a viewport having a second coordinate system to which a brush transform is applied, creating an empty destination bitmap sized according to a destination figure transform, and rendering the source content onto the empty destination bitmap such that the first coordinate system is transformed into the second coordinate system.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Applicant: MICROSOFT CORPORATION
    Inventors: Ambarish Sridharanarayanan, Georgi M. Chalakov
  • Publication number: 20090295816
    Abstract: A video graphics system, graphics processor, and method of reducing memory bandwidth consumption include logic that groups binary data of a block of pixels into bit-planes. Each bit-plane corresponds to a different bit position in the binary data of the block and includes a bit value from each pixel in the block at that corresponding bit position. An encoding, associated with the block of pixels, represents which ones of the bit-planes are constant-value bit-planes having binary data comprised of a same bit value from every pixel in the block and which of the bit-planes are mixed-value bit-planes. Logic accesses memory storing the block of pixels to process the binary data of each mixed-value bit-plane and accesses memory storing the encoding to process the binary data of each constant-value bit-plane when a processing operation is performed on the block of pixels.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventor: Kiia K. Kallio
  • Patent number: 7599716
    Abstract: A method is provided for processing data in a mobile communication terminal including a first data memory for storing first data indicating user-stored information and a second data memory for storing second data indicating user-stored information. The method includes creating a first data list corresponding to the first data and a second data list corresponding to the second data and displaying items of the first data list and items of the second data list on a screen of the mobile communication terminal in response to a user's data movement request, selecting at least one item from one that is selected from the first data list and the second data list that are separately displayed based on user's selection information, and storing data of the selected item in the first data memory or the second data memory into the other memory if a predetermined key is input.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: October 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sun Yoon, Dong-Wook Kwon
  • Patent number: 7554551
    Abstract: A display color buffer in a unified memory architecture is decoupled from main memory by partitioning the address space for the color buffer into a frame-preparation memory accessed by a graphics subsystem at a frame rate to prepare color data and a refresh memory that is accessed by a display device at a refresh rate to display the color data. The color data is periodically transferred between the frame-preparation memory and the refresh memory, or when a frame of color data is ready for display.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: June 30, 2009
    Assignee: Apple Inc.
    Inventor: Sara Ruhina Biyabani
  • Patent number: 7546542
    Abstract: Methods are disclosed for selectively loading one control at a time based on the location of a selection component relative to a graphical representation of a user interface.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: June 9, 2009
    Assignee: Microsoft Corporation
    Inventor: Girish Premchandran
  • Patent number: 7528839
    Abstract: A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need to be cleared. A graphics pipeline includes a bounding area memory to store bounding area values. The bounding area values are modified during rendering so that each rendered primitive falls within the bounding area values. The graphics processing subsystem clears a portion of the memory buffer in response to a clear command specifying a bounding area. The clear command may include a set of bounding area values defining the bounding area, or alternatively a reference to the bounding area memory. For applications that draw objects in isolation, the bounding area will be smaller than the window, resulting in a decreased time requirement for clearing the memory buffer.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 5, 2009
    Assignee: Nvidia Corporation
    Inventors: Ross A. Cunniff, Matthew J. Craighead
  • Patent number: 7526118
    Abstract: A method for generating a vertical section of an object surface under inspection by a digital optical-video inspection system movable along a vertical Z axis, comprising obtaining a video image of the object surface; overlaying over the video image on the object surface a sectioning band along a section vector to make a vertical section of the object, the band comprising a number of regions of pixels, the center of each region being a sampling point along the section vector; generating a series of video images of the object surface at several Z axis positions; computing a focus quality measurement Q(n) for each region at each Z axis position Z(n); computing a best focus quality measurement the series of Q(n); and generating a vertical cross-section of the object surface from a set of points x,y,z obtained at each best focus location.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: April 28, 2009
    Assignee: Quality Vision International, Inc
    Inventors: David Scott Davis, Albert G. Choate, Jason N. Couvutsakis, Karl J. Lenz
  • Patent number: 7397476
    Abstract: In response to a requirement of transferring a file from a personal computer PC to a projector 10 that is output by dragging and dropping a corresponding file icon onto a projector icon, a CPU 50 requires setting of a password. The CPU 50 maps the preset password to a file and transfers the file with the password to an external storage device of the projector 10. The projector 10 requires input of a password, which is expected to be assigned to the file, and allows reproduction of the file when the input password is coincident with the preset password.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: July 8, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Shoichi Akaiwa, Tomohiro Nomizo, Miki Nagano, Masaru Kono
  • Publication number: 20080055326
    Abstract: Techniques to allow multiple graphics processing units to operate in parallel, even with limited storage space, are described. An apparatus includes first and second processing units and a memory. The first processing unit performs pre-processing on a batch of graphics application data for an image (e.g., for vertices in the image) and generates command sub-lists for the batch. The second processing unit performs post-processing on the command sub-lists (e.g., for pixels of the image) and generates output data for the image. The first and second processing units may operate in parallel on different command sub-lists. The memory stores the command sub-lists and may also store a header for each command sub-list, a look-up table of memory addresses for the command sub-lists, a write counter indicating the most recently generated command sub-list, and a read counter indicating the most recently post-processed command sub-list.
    Type: Application
    Filed: September 5, 2006
    Publication date: March 6, 2008
    Inventors: Yun Du, Chun Yu, Guofang Jiao, Lingjun Chen
  • Patent number: 7324115
    Abstract: A 3-dimensional computer graphics rendering system receives object data for a scene to be rendered. This includes vertex data and index data. The scene is subdivided into priority of rectangular areas (202). Object 8 of each rectangular area in the scene is assembled (203) and subsequently compressed (207). This data can subsequently be retrieved and decompressed and used for producing a properly shaded and texted image for display.
    Type: Grant
    Filed: June 3, 2004
    Date of Patent: January 29, 2008
    Assignee: Imagination Technologies Limited
    Inventor: Christopher Fraser
  • Patent number: 7295210
    Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Jonathan B. Sadowski, Aditya Navale
  • Patent number: 7245304
    Abstract: Compressed graphic image data files, such as Compressed ARC (Arc-second Raster Chart/map) Digitized Raster Graphics (CADRG) map files for a region of interest, are stored in blocks of memory (nodes) preferably arranged as a linked list. Portions of files containing data for an area of interest including an image of interest are decompressed before the data are sent to a frame buffer for display. Nodes that do not contain requested data are flagged as unused, but not deallocated, making the data in such nodes available for use or replacement.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: July 17, 2007
    Assignee: Lockheed Martin Corporation
    Inventor: Marc A. Blais
  • Patent number: 7196710
    Abstract: A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. Techniques for efficiently buffering graphics data between a producer and a consumer within a low-cost graphics systems such as a 3D home video game overcome the problem that a small-sized FIFO buffer in the graphics hardware may not adequately load balance a producer and consumer—causing the producer to stall when the consumer renders bit primitives. One aspect of the invention solves this invention by allocating part of main memory to provide a variable number of variable sized graphics commands buffers. Applications can specify the number of buffers and the size of each. All writes to the graphics FIFO can be routed a buffer in main memory. The producer and consumer independently maintain their own read and write pointers, decoupling the producer from the consumer.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: March 27, 2007
    Assignee: Nintendo Co., Ltd.
    Inventors: Farhad Fouladi, Robert Moore
  • Patent number: 7176927
    Abstract: A computer-implemented method and system for performing graphics rendering on demand on a graphics subsystem, with only nominal host system operations being required. High-level specifications of graphics operations in a computer program are captured as I/O hardware programs in a memory. A graphics processor in the subsystem issues instructions in the captured programs to a graphics accelerator, which executes the instructions to perform graphics operations. The graphics accelerator has a status indicator containing status information relating to hardware events incident to the graphics operations. Under the control of instructions in the captured program, the graphics processor monitors the status indicator, and either issues, or delays issuing, the instructions in the captured programs, depending upon the status information in the indicator.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: February 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Devins, Paul M. Schanely