Mask Data Operation Patents (Class 345/563)
  • Patent number: 11438109
    Abstract: Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Marlon Gunderson, Kurt Ware
  • Patent number: 10860732
    Abstract: A system and method for providing transactional data privacy while maintaining data usability, including the use of different obfuscation functions for different data types to securely obfuscate the data, in real-time, while maintaining its statistical characteristics. In accordance with an embodiment, the system comprises an obfuscation process that captures data while it is being received in the form of data changes at a first or source system, selects one or more obfuscation techniques to be used with the data according to the type of data captured, and obfuscates the data, using the selected one or more obfuscation techniques, to create an obfuscated data, for use in generating a trail file containing the obfuscated data, or applying the data changes to a target or second system.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: December 8, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Shenoda Guirguis, Alok Pareek, Stephen Wilkes
  • Patent number: 10678546
    Abstract: Instructions and logic provide SIMD vector population count functionality. Some embodiments store in each data field of a portion of n data fields of a vector register or memory vector, at least two bits of data. In a processor, a SIMD instruction for a vector population count is executed, such that for that portion of the n data fields in the vector register or memory vector, the occurrences of binary values equal to each of a first one or more predetermined binary values, are counted and the counted occurrences are stored, in a portion of a destination register corresponding to the portion of the n data fields in the vector register or memory vector, as a first one or more counts corresponding to the first one or more predetermined binary values.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Terence Sych, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 10649925
    Abstract: A portion of the memory space, supported by memory chips that are being controlled by a memory controller logic, can be set aside and read requests directed to memory addresses within that portion can be redirected, by the memory controller logic, to other memory addresses at which is stored the data equivalent to the internal data of the memory controller logic that the memory controller logic seeks to return, thereby enabling the memory controller logic to indirectly return data to processes executing on the host computing device. Additionally, requests to write data to specific memory addresses, including memory addresses that can be within the set aside portion, can be interpreted, by the memory controller logic, as commands that the memory controller logic is to perform, and which impact its own internal data including commands to reset values, or start or end data collection, or other like commands.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: May 12, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: John Grant Bennett
  • Patent number: 10593030
    Abstract: An image forming apparatus that is capable of adjusting thickness of a graphic character. An image forming apparatus including at least one controller, having one or more processors that execute instructions stored in at least one memory and/or one or more circuitries, being configured to generate an graphic object from a drawing command set for printing the graphic object included in a print job, generate a first mask image by rendering the graphic object, generate a second mask image by shifting the first mask image in a thickening direction by the number of pixels of a thickening width, generate a third mask image by logically composing the first mask image and the second mask image, convert the third mask image into intermediate data, and generate raster image by rendering of the intermediate data.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: March 17, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroyuki Nakane
  • Patent number: 10165201
    Abstract: A method for processing images is performed at a client device having a camera, including: capturing a first image using the camera and extracting a first subject and a first background from the first image; rendering the first background in the display; comparing the first background with a set of second backgrounds dynamically captured by the camera on the display; generating a visual or audible indicator upon determining that one of the set of second backgrounds matches the first background; in response to the visual or audible indicator, capturing a second image using the camera, the second image including a second subject; and generating a third image by combining the first image and the second image, the third image including the first subject, the second subject and the first background.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: December 25, 2018
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yinghua Ye, Na Shao
  • Patent number: 9916663
    Abstract: An image processing method includes the steps of detecting edge information from an input image, identifying a plurality of lines from the edge information, dividing the input image into a plurality of areas based on the relative locations of the plurality of identified lines, calculating a similarity between adjacent areas of the plurality of divided areas, detecting boundaries between the adjacent areas as line segments partitioning the adjacent areas based on a degree of dissimilarity of the adjacent areas, wherein each of the line segments is at least a portion of the plurality of lines, and connecting the line segments forming the boundaries, and generating a connected shape using the boundaries.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akiko Kawamoto
  • Patent number: 9854181
    Abstract: A method is disclosed, for performing image processing at a client device, including taking a first photograph comprising a first subject and a first background. The method further includes processing the first photograph to generate a first processed photograph comprising a modified first subject and a modified first background, and aligning the first processed photograph through the display of the client device until a second background shown on the display matches the modified first background. The method further includes taking a second photograph with the first processed photograph aligned in the display of the client device, wherein the second photograph comprises a second subject and the second background, and combining the first photograph and the second photograph to create a third photograph, wherein the third photograph comprises the first subject, the second subject and the first background.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: December 26, 2017
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Yinghua Ye, Na Shao
  • Patent number: 8952976
    Abstract: A SIMD parallel processor is described comprising an array comprising processing elements, associated data storage components and access means configured to enable access to at least one of the data storage components associated with at least one of the processing elements; a control processor; memory control means configured to enable addressing of at least one of the access means for the control processor; and connecting means configured to connect the memory control means to the access means.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: February 10, 2015
    Assignee: NXP B.V.
    Inventors: Alexander Alexandrovich Danilin, Richard Petrus Kleihorst, Paul Wielage
  • Patent number: 8928681
    Abstract: Sequential write operations to a unit of compressed memory, known as a compression tile, are examined to see if the same compression tile is being written. If the same compression tile is being written, the sequential write operations are coalesced into a single write operation and the entire compression tile is overwritten with the new data. Coalescing multiple write operations into a single write operation improves performance, because it avoids the read-modify-write operations that would otherwise be needed.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 6, 2015
    Assignee: NVIDIA Corporation
    Inventors: John H. Edmondson, Robert A. Alfieri, Michael F. Harris, Steven E. Molnar
  • Patent number: 8922555
    Abstract: One embodiment of the present invention sets forth a technique for storing only the enabled components for each enabled vector and writing only enabled components to one or more specified render targets. A shader program header (SPH) file provides per-component mask bits for each render target. Each enabled mask bit indicates that the pixel shader generates the corresponding component as an output to the raster operations unit. In the hardware, the per-component mask bits are combined with the applications programming interface (API)-level per-component write masks to determine the components that are updated by the shader program. The combined mask is used as the write enable bits for components in one or more render targets. One advantage of the combined mask is that the components that are not updated are not forwarded from the pixel shader to the ROP, thereby saving bandwidth between those processing units.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: December 30, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., Jesse David Hall, Patrick R. Brown, Mark Dennis Stadler
  • Patent number: 8754900
    Abstract: Methods, systems and apparatuses for selecting graphics data of a server system for transmission are disclosed. One method includes reading data from graphics memory of the server system. The data read from the graphics memory is placed in a transmit buffer if the data is being read for the first time, and was not written by a processor of the server system. One system includes a server system including graphics memory, a frame buffer and a processor. The server system is operable to read data from the graphics memory. The server system is operable to place the data in a transmit buffer if the data is being read for the first time, and was not written by the processor during rendering.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 17, 2014
    Inventors: Satyaki Koneru, Ke Yin, Dinakar Munagala
  • Patent number: 8599212
    Abstract: The present invention discloses a character display method and apparatus. The method includes: obtaining a display color value of a character; obtaining a background color value of the character according to a position of the character; obtaining a difference between the display color value and the background color value; obtaining an outline of the character when the difference is smaller than a preset threshold; and displaying the character that has the outline. By adopting the present invention, the character may be clearly displayed in a background without changing a color of the character and a color of the background.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: December 3, 2013
    Assignee: Huawei Device Co., Ltd.
    Inventor: Dejie Zhao
  • Patent number: 8581920
    Abstract: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 12, 2013
    Assignee: Rambus Inc.
    Inventors: Lei Luo, Frederick A. Ware, John Wilson, Jade M. Kizer
  • Patent number: 8407615
    Abstract: A system and method by which menus, displays, charts, maps and pictures may be presented to a user and very quickly seen and used in the context of a larger display without obscuring key elements of that display. Menus or other graphical displays are anchored to the sides of a solid figure, which can be rotated to display the menu panels and other textual and graphical information.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: March 26, 2013
    Assignee: Pitney Bowes Software Inc.
    Inventor: Arthur R. Berrill
  • Patent number: 8356162
    Abstract: An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Adam James Muff, Matthew Ray Tubbs
  • Patent number: 8319794
    Abstract: An image display control apparatus includes an image data supply section that supplies an image composed of a plurality of pixels arranged two-dimensionally in a matrix form as captured image data, a mask data supply section that supplies mask data for masking the image data, an imaging instruction accepting section that validates an imaging instruction acceptance signal when accepting an operation input corresponding to an imaging instruction, and a drawing section that sequentially draws the respective pixels, each having a pixel value, in the image data every predetermined period. When detecting that the imaging instruction acceptance signal is valid, the drawing section draws the pixels such that each pixel has a value including the mask data as the pixel value after the detection.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: November 27, 2012
    Assignee: Sony Corporation
    Inventor: Nobuhiro Doi
  • Patent number: 7903108
    Abstract: The invention describes a method and system for use in occlusion culling of polygons in an interactive environment, such as a game. The invention employs a boundary box to simplify the testing of occludee polygons. Occluders and occludees are also transformed into non-interpenetrating, non-overlapping polygons. Winged-edges are employed to minimize a per occludee computational cost due to precision problems that may arise at non-overlapping edges. The invention then proceeds through an active edge list to identify edge discontinuities (e.g., where an edge is added or removed from the active edge list). Depth analysis is employed to determine whether an occluder occludes an occludee at the edge discontinuity. Moreover, the invention only performs depth analysis for those locations of a screen display where an occludee is determined to reside, thereby minimizing unnecessary computations.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: March 8, 2011
    Assignee: Valve Corporation
    Inventor: Brian Jacobson
  • Patent number: 7889206
    Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: February 15, 2011
    Assignee: Broadcom Corporation
    Inventors: R. Lakshmikanth Pai, Ravindra Bidnur, Sandeep Bhatia, Lakshmanan Ramakrishnan, Vijayanand Aralaguppe
  • Patent number: 7528843
    Abstract: Systems and methods for dynamically canceling texture fetches may improve texture mapping performance. A shader program compiler inserts condition code writes and condition code comparison operations for shader program instructions that contribute to a texture read instruction and do not need to be executed if certain conditions are met. During execution of the shader program, the inserted condition codes are used to compute a dynamic writemask that indicates if the texture data resulting from the texture read is unnecessary. The dynamic writemask is used to cancel unnecessary texture fetches during execution of the shader program.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: May 5, 2009
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Rui M. Bastos, Johnny S. Rhoades, Cass W. Everitt, Wei-Chao Chen
  • Patent number: 7523189
    Abstract: Methods and computer readable media for generating displays of user-defined blocks of networking addresses on a map of an associated address space are provided. Each block of networking addresses is described in a user-defined table with a start address and a map size. The display for each block of network addresses may be rendered on the map at a location based on the relative position of the start address within the associated address space and of a size based on the mask size in relation to the associated address space.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: April 21, 2009
    Assignee: Internet Associates, LLC
    Inventors: Dennis Joseph Boylan, Kenneth Douglas Burroughs, Sean Ming Drun, John Leland Lee, Angela Kristine Schneider
  • Patent number: 7508397
    Abstract: Methods, apparatuses, and systems are presented for modifying data in memory associated with an image, involving processing data operations in a pipelined process affecting data in memory corresponding to the image. The data operations include a first data operation involving a first read operation followed by a first write operation, and a second data operation involving a second read operation followed by a second write operation. After starting the first read operation, a determination is made whether data associated with the first data operation overlaps with data associated with the second data operation. If a data overlap occurs, the second read operation is started after the first write operation is completed, and if no data overlap occurs, the second read operation is started before the first write operation is completed.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: March 24, 2009
    Assignee: Nvidia Corporation
    Inventors: Steven E. Molnar, Justin Legakis
  • Patent number: 7456838
    Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: November 25, 2008
    Assignee: NVIDIA Corporation
    Inventors: Patrick R. Brown, Mark J. Kilgard, Robert Steven Glanville
  • Patent number: 7394462
    Abstract: A superimposing apparatus and method for broadcasting a 3DCG image can calculate and superimpose additional information such as characters and figures expressed by a 3DCG image on a TV frame in real time by combining a general three-dimensional graphics accelerator board and a conventional TV broadcasting hardware and devising a software processing. The superimposing apparatus performs a rendering process for rendering a 3DCG image datum by a three-dimensional graphics accelerator and a mixing process for mixing a 3DCG image and an input TV signal by a superimposer. The rendering process is carried out concurrently with the mixing process. A frame to be mixed is a previous frame advanced by one frame from a frame to be concurrently rendered. A system memory to be read out is changed to even frames and odd frames in accordance with an input TV signal so as to avoid an interference of rendering and superimposing.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: July 1, 2008
    Assignee: Kabushiki Kaisha Micronet
    Inventor: Kozo Murakami
  • Patent number: 7370170
    Abstract: Methods and apparatuses that enable memory devices to inform graphical processing systems about the results of WRITE de-skew training. A WRITE-TRAINING mode is added to a memory device. When the WRITE-TRAINING mode is asserted the memory data mask (DM) pin is converted to an output port. Incoming WRITE data is strobed-into the memory device and the resulting data pattern is compared to a desired pattern. If the incoming WRITE data and strobed-in data match, that result is sent to the graphical processing system by setting the DM pin HIGH. If the incoming WRITE data and the strobed-in data do not match, that result is sent to the graphical processing system by setting the DM pin LOW. Beneficially, the incoming data and the desired pattern are derived from pseudo random bit sequence (PRBS) sources.
    Type: Grant
    Filed: August 3, 2004
    Date of Patent: May 6, 2008
    Assignee: NVIDIA Corporation
    Inventors: Ashfaq R. Shaikh, Barry A. Wagner
  • Publication number: 20080068393
    Abstract: A computer-readable recording medium recording a mask data generation program, the mask data generation program causes the computer to execute: Fourier-Transforming a function indicating an effective light source to generate a coherent map expressing a coherence distribution on the object plane of the projection optical system, on which the mask is arranged; specifying a reference vector from the origin of the coherent map to a region where the coherence is less than a reference value; selecting one element from a pattern including a plurality of elements, and removing, from the pattern, an element existing at a position matching the terminal point of the reference vector arranged such that the center of the selected element serves as the starting point, to generate data of a first pattern different from the pattern; and generating data of a second pattern including the element removed in generating the data of the first pattern.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 20, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Kenji Yamazoe
  • Patent number: 7202872
    Abstract: One embodiment of the present invention is directed to a graphics system comprising logic for generating a mask that identifies bits within a plurality of bits that are not to be impacted by a subsequent computation. The graphics system further comprises compression logic that is responsive to the mask for generating a compressed bit stream, such that the bits that are not to be impacted by the computation are not included in the compressed bit stream. Another embodiment of the present invention is directed to a graphics system comprising logic for generating a mask identifying positions within a plurality of positions of a bit stream that are to be removed during a compression operation.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: April 10, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Timour Paltashev, Boris Prokopenko
  • Patent number: 7062088
    Abstract: Methods and apparatus for generating a compressed image from a source image by compressing the source image using a dictionary based lossy compression algorithm that regionally varies the amount of information loss from the source image based on regional image quality levels contained in an image quality mask. The image quality mask can be an alpha channel of the source image, can be stored as a raster map, or can be stored as a resolution independent function. The regional image quality levels in the image quality mask can be determined by a user, automatically generated from the image, or automatically generated from user input. The dictionary based lossy compression algorithm can be a lossy Lempel-Ziv-Welch (LZW) compression algorithm.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: June 13, 2006
    Assignee: Adobe Systems Incorporated
    Inventor: Jon D. Clauson
  • Patent number: 7032092
    Abstract: A common DRAM controller is provided for supporting a plurality of memory types such as double data rate or quad data rate mode or types. The controller is adapted to use a number of clock signals to process data. The controller can further delay the data for a predetermined time period and capture the same.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: April 18, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: Jiin Lai
  • Patent number: 6937244
    Abstract: A system and method for rendering a graphics primitive. A two pass method is employed where, in the first pass, for each block affected by the primitive, whether the pixels of the affected block intersect the front and/or back layers of the block is determined. If there are intersected pixels in the block, a flag is set indicating that the z-buffer must be read to determine the visibility of the affected pixels in the block. On a second pass, the blocks affected by the graphics primitive are again examined. If the flag is not set, then the visible pixels are rendered to the frame buffer based on the front and back layers of the block. If the flag is set, then for each sub-block affected by the primitive, the z-buffer is read and the visible pixels are rendered to the frame buffer based on the reading of the z-buffer.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: August 30, 2005
    Inventor: Zhou (Mike) Hong
  • Patent number: 6894700
    Abstract: A system and method for generating random coverage masks for rendering images with transparent objects. The system uses shuffle tables for addresses of a pixel to index into a transparency table and to obtain a transparency mask, which is then ANDed with a coverage mask to obtain a new coverage mask.
    Type: Grant
    Filed: February 25, 2004
    Date of Patent: May 17, 2005
    Assignee: 3Dlabs, Inc., Ltd.
    Inventors: Dale L. Kirkland, James L. Deming
  • Patent number: 6744533
    Abstract: A method and system for efficient buffer rendering. An object mask, typically a character font mask, is aligned with a memory tiling arrangement (1102). A tile map is generated (1104) to indicate active tiles. An active tile is selected (1106) and the portion of the buffer corresponding to the active tile is transferred (1108) from a first memory, typically an off-chip memory, to a second memory, typically an on-chip memory to allow a processor to render the band buffer tile. The portion of the band buffer is rendered (1110) and returned (1112) to the first memory. The next active tile is selected and the process continues until all active tiles have been rendered (1114).
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: June 1, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Venkat V. Easwar, Fred J. Reuter, Ralph Payne
  • Patent number: 6738101
    Abstract: An information-outputting apparatus, an information-reporting method and an information-signal-supply-route-selecting method, which provide a digital-content utilization environment giving the user a high degree of freedom to make use of the apparatus and the methods. The information-outputting apparatus receives an isochronous packet transmitted by a source external apparatus by adoption of an isochronous communication method through a digital bus connecting the external apparatus to the information-outputting apparatus. In the information-outputting apparatus, an IEEE 1394 I/F circuit extracts information on the source electronic apparatus and information on the transmission format. A control unit supplies these pieces of information to an OSD-generating circuit for displaying them on a screen of a display unit employed in the information-outputting apparatus.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: May 18, 2004
    Assignee: Sony Corporation
    Inventors: Hiroshi Utsunomiya, Satoshi Kobayashi, Futoshi Kaibuki
  • Patent number: 6642926
    Abstract: A telecom mask testing zoom function draws mask. pixels into a raster memory. In this way, the mask is treated as a waveform. Comparison of the mask pixels and waveform pixels to detect collision between a waveform pixel and a mask pixel (i.e., a mask violation) is performed substantially in real time, as the pixels are being composited into the raster memory by the rasterizer. The mask is scalable and repositionable by the rasterizer under control of a controller, because it is treated as a waveform. The mask is lockable to the waveform because both are stored in pixel form in raster memory by the rasterizer under control of the controller.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: November 4, 2003
    Assignee: Tektronix, Inc.
    Inventor: Peter J. Letts
  • Publication number: 20030164835
    Abstract: In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The data output by the first component may include both the requested data and unrequested data, and the unrequested data may have an unpredictable value. A controller coupled to the bus may be configured to replace the unrequested data with data that has a predictable value. A signature analysis register included in the second component is configured to capture the requested data and the predictable data output by the controller. Thus, the signature captured in the second component may be predictable, despite the unpredictable data output by the first component.
    Type: Application
    Filed: March 4, 2002
    Publication date: September 4, 2003
    Inventors: Wayne Eric Burk, David Gibbs, David Kehlet
  • Patent number: 6597363
    Abstract: Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: July 22, 2003
    Assignee: Apple Computer, Inc.
    Inventors: Jerome F. Duluk, Jr., Richard E. Hessel, Vaughn T. Arnold, Jack Benkual, Joseph P. Bratt, George Cuan, Stephen L. Dodgen, Emerson S. Fang, Zhaoyu Gong, Thomas Y. Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N. Papakipos, Jason R. Redgrave, Sushma S. Trivedi, Nathan D. Tuck
  • Patent number: 6552730
    Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: April 22, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Kiichiro Urabe
  • Patent number: 6529284
    Abstract: A method and system for expanding a pixel bitmap mask. The pixel bitmap mask (102) is expanded by the use of a lookup table (104) to create an m*n bit expanded mask, where m is the depth of a screen and n is the number of pixels described by the original pixel bitmap mask (102). The expanded mask is logically ANDed with a foreground screen (106). The inverse of the expanded mask is logically ANDed with existing data in a screen buffer (108). The results of the two AND operations are logically OR'd to create a new screen buffer that is eventually sent to a printer.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: March 4, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Praveen K. Ganapathy, Venkat V. Easwar
  • Patent number: 6504495
    Abstract: A clipping and quantization technique is described for producing clipped numbers in a range of 0 to N−1 (from unclipped numbers in a range of −0.5N to (1.5N−1)), where N is 2m and m is the bit length of the desired clipped and quantized number. The most significant bit of the unclipped data value indicates whether an overflow of the permitted range has occurred and that clipping is required. The next most significant bit (m−1th) indicates which saturated value should be adopted. These properties of the unclipped data value may be exploited to generate the desired clipped and quantized numbers using logical left shifting and conditionally executed saturating instructions executing upon a general purpose processor 24. The shifting operations performed to achieve saturation operation may simultaneously yield quantization.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: January 7, 2003
    Assignee: Arm Limited
    Inventors: Dominic Hugo Symes, Wilco Dijkstra
  • Patent number: 6437790
    Abstract: A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 20, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Koichi Kimura, Toshihiko Ogura, Hiroaki Aotsu, Kiichiro Urabe
  • Publication number: 20020109700
    Abstract: A method for modifying a selected data portion (8) of a data item (10) with a bit pattern (36) is disclosed. Said method identifies a data portion (8) to be modified. Said method further selects a field (38) by accessing a plurality of fields (30). Said fields (30) include a plurality of recurring bit patterns (36). Adjacent fields (38, 40) have identical bit patterns offset by at least one bit. Said method selects a mask (58) to obtain a selected one of said bit patterns (36) in said selected field (38) that is aligned with said identified data portion (8). Said method modifies said identified data portion (8) by performing a predetermined bit operation on said identified data portion (8) with said selected one of said bit patterns (36). A processor for performing the above method is also disclosed.
    Type: Application
    Filed: December 14, 2000
    Publication date: August 15, 2002
    Applicant: Motorola, Inc.
    Inventors: Chun Kee Ma, Wai Tung Chan, Kwan Leung Mok, Ho Yu Wong
  • Patent number: 6429873
    Abstract: A method and circuit for determining the address of texture maps in memory, when only the base address of the primary texture map is known. The various maps associated with a given texture are sized and stored in a manner that allows any texel in any of the maps to be located based on the map number and the base address of the primary map. A circuit is provided that determines the necessary addresses with minimal calculations.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: August 6, 2002
    Assignee: Intel Corporation
    Inventors: Nicolas I. Kacevas, Val G. Cook, Peter L. Doyle
  • Publication number: 20020085012
    Abstract: Disclosed are method and apparatus for applying a convolution operator to an input image to produce an output image. Image pixel data corresponding to at least a predetermined number of scan lines of the input image is provided to a buffer memory adapted to store a portion of said image. The image data may be provided from a source of such data, or alternatively it may be rendered from a object grahics environment. A finite convolution mask is applied to the image pixel data to produce a scan line of the output image. The finite convolution mask has a plurality of coefficients arranged in a predetermined number of rows and a predetermined number of columns and the predetermined number of scan lines substantially equals at least one of the number of rows or the number of columns of the convolution mask. In a preferred implementation, a scan line of the input image is discarded and a next scan line is provided for each scan line of the output image produced by the convolution.
    Type: Application
    Filed: January 21, 1998
    Publication date: July 4, 2002
    Inventor: GEORGE POLITIS
  • Patent number: 5758259
    Abstract: This method includes a method of identifying for a selected viewer a preferred program available from an interactive television or televideo (IT) system at a selected time. The IT system establishes for each viewer a database or table of viewer preferences representing the particular characteristics of programming previously delivered to the viewer. The IT system compares the particular characteristics in the viewer preference table to predetermined characteristics of video programming available at the selected time. The IT system determines for the video programming available at the selected time degrees of correlation to the predetermined characteristics in the viewer preference table. The IT system identifies as the preferred program the video programming available at the selected time having a greatest degree of correlation.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: May 26, 1998
    Assignee: Microsoft Corporation
    Inventor: Frank A. Lawler