Logical Operations Patents (Class 345/561)
  • Patent number: 9901828
    Abstract: Methods and systems for enabling an augmented reality character to maintain and exhibit awareness of an observer are provided. A portable device held by a user is utilized to capture an image stream of a real environment, and generate an augmented reality image stream which includes a virtual character. The augmented reality image stream is displayed on the portable device to the user. As the user maneuvers the portable device, its position and movement are continuously tracked. The virtual character is configured to demonstrate awareness of the user by, for example, adjusting its gaze so as to look in the direction of the portable device.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: February 27, 2018
    Assignee: Sony Interactive Entertainment America LLC
    Inventors: Thomas Miller, George Weising
  • Patent number: 9898829
    Abstract: A monitoring apparatus using three-dimensional (3D) information of images includes: an image acquisition unit to acquire a two-dimensional (2D) image from a pan/tilt/zoom (PTZ) camera; an information extraction unit to extract 2D coordinate information of an object based on a pan/tilt angle of the PTZ camera and extract distance information between the PTZ camera and the object; an operation unit to calculate at least one of variation of the 2D coordinate information and the distance information by comparing a current frame and a previous frame of the 2D image, and variation of the 2D coordinate information and height information of the object by comparing a current frame and a previous frame of a 3D image of the object; and a position tracking unit to track a position of the object by controlling the PTZ camera based on the at least one of the two variations.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: February 20, 2018
    Assignee: Hanwha Techwin Co., Ltd.
    Inventor: Chang Soo Kim
  • Patent number: 9641822
    Abstract: Provided is point-based efficient three-dimensional (3D) information representation from a color image that is obtained from a general Charge-Coupled Device (CCD)/Complementary Metal Oxide Semiconductor (CMOS) camera, and a depth image that is obtained from a depth camera. A 3D image processing method includes storing a depth image associated with an object as first data of a 3D data format, and storing a color image associated with the object as color image data of a 2D image format, independent of the first data.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Young Sim, Do Kyoon Kim, Kee Chang Lee, Gael Guennebaud, Mario Botsch, Markus Gross, Robert Carnecky
  • Patent number: 9443344
    Abstract: Some embodiments of the invention pertain to a method for displaying a representation of a portion of a three-dimensional surface by rendering data representing physical features of the portion of the three-dimensional surface. The data may be apportioned into a multitude of tiles at a plurality of different detail levels. The representation may include a multitude of image pixels and/or a buffer being assigned to each image pixel. The method may also include identifying tiles that need to be rendered, and rendering the identified tiles. At least a portion of a tile may be displayed by a multitude of image pixels, by assigning an unambiguous distance value to each of the identified tiles, and storing a default buffer value in the buffers of the image pixels. The rendering may include comparing the buffer values of image pixels and the distance value of a presently rendered tile.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: September 13, 2016
    Assignee: HEXAGON TECHNOLOGY CENTER GMBH
    Inventor: Olivier Chatry
  • Patent number: 9381157
    Abstract: A method for direct therapeutic treatment of myocardial tissue in a localized region of a heart having a pathological condition. The method includes identifying a target region of the myocardium and applying material directly and substantially only to at least a portion of the myocardial tissue of the target region. The material applied results in a physically modification the mechanical properties, including stiffness, of said tissue. Various devices and modes of practicing the method are disclosed for stiffening, restraining and constraining myocardial tissue for the treatment of conditions including myocardial infarction or mitral valve regurgitation.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 5, 2016
    Assignee: CORMEND TECHNOLOGIES, LLC
    Inventors: William P. Santamore, Jeanne M. Lesniak
  • Patent number: 9264265
    Abstract: A method of generating white noise for use in graphic and image processing, in accordance with one embodiment of the present invention, includes receiving one or more hash inputs. The hash inputs may be one or more primitive coordinates, one or more texel addresses, a base image, a device identifier, or a user password. The one or more hash inputs are evaluated utilizing a cryptographic hash function. The output of the cryptographic hash function generates one or more white noise samples. The white noise samples may be utilized as texel data. The white noise samples may also be utilized for encrypting images.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 16, 2016
    Assignee: NVIDIA CORPORATION
    Inventor: Li-Yi Wei
  • Patent number: 9148699
    Abstract: A method includes reading a composite video descriptor data structure and a plurality of window descriptor data structures. The composite video descriptor data structure defines a width and height of a composite video frame and each window descriptor data structure defines the starting X and Y coordinate, width and height of each constituent video window to be rendered in the composite video frame. The method further includes determining top and bottom Y coordinates for each constituent video window, as well as determining left and right X coordinates for each constituent video window. The method also includes dividing each constituent video window using the top and bottom Y coordinates to obtain Y-divided sub-windows, dividing each Y-divided sub-window using left and right X coordinates to obtain X and Y divided sub-windows, and storing X, Y coordinates of opposing corners of each X and Y divided sub-window in the storage device.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: September 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sujith Shivalingappa, Sivaraj Rajamonickam
  • Patent number: 9143826
    Abstract: Systems and methods are provided for cross-platform rendering of video content on a user-computing platform that is one type of a plurality of different user-computing platform types. A script is transmitted to the user-computing platform and is interpreted by an application program compiled to operate on any one of the plurality of user-computing platform types. Transmitting the script causes the script to be interpreted by the application program operating on the user-computing platform to cause the interpreted script to directly decode encoded video data transmitted or otherwise accessible to the user-computing platform into decoded video data and to further cause the rendering of the decoded video data.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: September 22, 2015
    Inventors: Steven Erik Vestergaard, Che-Wai Tsui, Shaoning Tu
  • Patent number: 9071785
    Abstract: The present disclosure concerns a method and system to accurately remove a three-dimensional distortion in an image of a document and convert the image into an accurate two dimensional image. A method for accurately deducing an image of a document to a precise document boundary is also disclosed. A portable computing device may employ the disclosed method and system. The methods involve a marker embedded in a document which provides three-dimensional positional information of a recording device with reference to the marker continuously in real time.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: June 30, 2015
    Assignee: Gradeable, Inc.
    Inventor: Dante Cassanego
  • Patent number: 9064347
    Abstract: A method, medium, and system efficiently rendering 3 dimensional (3D) graphics data. The rendering method includes calculating the strength of a fog effect that is to be applied to graphics data, determining whether texture mapping must be performed on the graphics data, according to the strength of the fog effect, and performing the texture mapping according to the determination result. Accordingly, it is possible to reduce the number of memory access operations for reading textures.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: June 23, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-oak Woo, Seok-yoon Jung, Chan-min Park
  • Patent number: 9046942
    Abstract: In one embodiment, a method comprises detecting, by a hardware accelerator, that a value has been written to a first location of a memory, the first location identified by a first address. The method further includes adding the value to an accumulated value stored in an accumulator register of the hardware accelerator and storing the result in the accumulator register. The method further includes comparing the value to a maximum value stored in a first register of the hardware accelerator and overwriting the maximum value with the value if the value is greater than the maximum value. The method also includes comparing the value to a minimum value stored in a second register of the hardware accelerator and overwriting the minimum value with the value if the value is less than the minimum value.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: June 2, 2015
    Assignee: Atmel Corporation
    Inventors: John Stanley Dubery, Paul Heslop, Yahya Yassin
  • Publication number: 20150097852
    Abstract: A display driver that receives display line data of plural display lines to perform drive control on a display panel includes a line memory for storing display line data which is supplied from the outside. The display driver includes a logic circuit that controls write and read-out of the display line data in and from the line memory, and sorts pixel data of the display line data using read out data from the line memory, to generate display drive data. Drive circuits drive the display panel in units of display lines based on the drive data which is output from the logic circuit. The drive circuits are separately arranged on both sides of the logic circuit and the line memory which are interposed therebetween. The storage capacity of the line memory corresponds to the number of lines smaller than the number of display lines of a display frame.
    Type: Application
    Filed: September 20, 2014
    Publication date: April 9, 2015
    Inventors: Hikaru SHIBAHARA, Hideaki HONDA, Hiroki TAKEUCHI
  • Patent number: 8937624
    Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: January 20, 2015
    Assignees: Samsung Electronics Co., Ltd., Industry-Academia Cooperation Group of Sejong University
    Inventors: Gi Ho Park, Won Chang Lee, Shi Hwa Lee, Do Hyung Kim, Joon Ho Song, Sung Uk Jeong
  • Publication number: 20150015595
    Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Eric B. LUM, Jerome F. DULUK, Jr.
  • Publication number: 20150015594
    Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Eric B. LUM, Jerome F. DULUK, JR.
  • Patent number: 8922576
    Abstract: Methods and systems for interacting with multiple three-dimensional (3D) object data models are provided. An example method may involve providing to a display device for display a first 3D object data model and a second 3D object data model. Information associated with a modification to the first 3D object data model may be received. Based on the received information, a same change may be applied to the first 3D object data model and applied to the second 3D object data model to obtain a first modified 3D object data model and a second modified 3D object data model. According to the method, the first modified 3D object data model and the second modified 3D object data model may be provided to the display device for substantially simultaneous display.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: December 30, 2014
    Assignee: Google Inc.
    Inventors: Ryan Hickman, James J. Kuffner, Jr., Anthony Gerald Francis, Jr., Arshan Poursohi, James R. Bruce, Thor Lewis, Chaitanya Gharpure
  • Patent number: 8780121
    Abstract: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Lai Kuan Chong, Lai Guan Tang
  • Patent number: 8773459
    Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: July 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Guofang Jiao, Chun Yu, Lingjun Chen, Yun Du
  • Patent number: 8736628
    Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: May 27, 2014
    Assignee: Nvidia Corporation
    Inventors: Edward A. Hutchins, Brian K. Angell
  • Patent number: 8625673
    Abstract: Systems and methods of determining motion vectors, such as for video encoding, are disclosed. In one example, motion vectors are determined for a current frame, using sampled pixel information from a reference frame. Sampled pixel information is obtained using a sampling pattern. The sampling pattern, in one example, includes subsampling pixels at different rates for horizontal and vertical directions. The subsampling rate can differ, based on an amount of motion represented by a matching block (e.g., the farther a match is found away from an origin of the block, the more subsampling can be done). In another example, a full pixel resolution is maintained proximal an original location of the block; as distance increases in one or more directions, subsampling can begin and/or increase. Sampled pixels can be stored. Interpolation of the sampled pixels can be performed and the sampled and resulting interpolated pixels can be used for comparison.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 7, 2014
    Assignee: Imagination Technologies, Ltd.
    Inventor: Simon Nicholas Heyward
  • Patent number: 8581920
    Abstract: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: November 12, 2013
    Assignee: Rambus Inc.
    Inventors: Lei Luo, Frederick A. Ware, John Wilson, Jade M. Kizer
  • Patent number: 8502830
    Abstract: An image processing apparatus is configured to rasterize an object into a bitmap using a first memory and a second memory which can be accessed quicker than the first memory. The image processing apparatus includes an extraction unit configured to extract a plurality of objects to be rasterized on the second memory from a plurality of the objects, and a first combination unit configured to combine a plurality of objects which can be rasterized within capacity of the second memory from among the objects extracted by the extraction unit into an object.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: August 6, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shuuji Ozawa
  • Patent number: 8432409
    Abstract: A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: April 30, 2013
    Inventors: Frederick S. Dunlap, Mark A. Krom, Adam Snay
  • Patent number: 8248422
    Abstract: A circuit arrangement and method perform concurrent texture processing of groups of pixels with a single instruction multiple data (SIMD) execution unit to improve the utilization of the SIMD execution unit when performing scalar operations associated with a texture processing algorithm. In addition, when utilized in connection with a multi-threaded SIMD execution unit, groups of pixels may be concurrently processed in different threads executed by the SIMD execution unit to further maximize the utilization of the SIMD execution unit by reducing the adverse effects of dependencies in scalar and/or vector operations incorporated into a texture processing algorithm.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Eric Oliver Mejdrich, Paul Emery Schardt, Robert Allen Shearer
  • Patent number: 8243069
    Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: August 14, 2012
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Phillip Keslin, Steven E Molnar, Adam Clark Weitkemper
  • Patent number: 8232991
    Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: July 31, 2012
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Phillip Keslin, Steven E Molnar, Adam Clark Weitkemper
  • Patent number: 8228328
    Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: July 24, 2012
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Phillip Keslin, Steven E Molnar, Adam Clark Weitkemper
  • Patent number: 8212840
    Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: July 3, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Guofang Jiao, Chun Yu, Lingjun Chen, Yun Du
  • Patent number: 8155469
    Abstract: A filter circuit includes: an adder/subtractor that performs at least addition; and a shifter that performs multiplication/division by a power of two through a shift operation. The adder/subtractors and the shifter are configured to obtain a first calculation result representing a pixel value of a target pixel included in image data multiplied by a first filter coefficient. At least the adder/subtractors and the shifter is configured to obtain a second calculation result representing pixel values of a plurality of peripheral pixels adjacent to the target pixel, with each of the pixel values being multiplied by a second filter coefficient. The adder/subtractor is configured obtain a third calculation result by adding the first and second calculation results. The shifter configured to divide the third calculation result by a power of two which is equivalent to a sum of the first and second filter coefficients, so as to output the division result.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: April 10, 2012
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiyuki Ono
  • Patent number: 8130837
    Abstract: An apparatus is provided for determining motion between a first and second video image. The apparatus includes an input device for receiving the first and the second video image with a plurality of pixels, a block selector for selecting a block of pixels within the first video image, a search area selector for selecting at least part of the second video image to produce a search area, a sampler for sampling the pixels of the search area in a predetermined pattern and a comparator for comparing the selected block of pixels within the first video image with at least one block of the sampled pixels of the search area to determine the motion of the block of pixels between the images. The pattern of sampled pixels varies throughout the search area.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: March 6, 2012
    Assignee: Imagination Technologies Limited
    Inventor: Simon Nicholas Heyward
  • Patent number: 8112560
    Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: February 7, 2012
    Assignee: ARM Limited
    Inventors: Paul Kimelman, Edmond John Simon Ashfield, Steven Richard Mellor, Ian Field
  • Patent number: 8049760
    Abstract: The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: November 1, 2011
    Assignee: Via Technologies, Inc.
    Inventors: Yang (Jeff) Jiao, Chien Te Ho
  • Publication number: 20110169851
    Abstract: An overdriving apparatus including a memory unit, a position unit and an overdriving unit is provided. The memory unit stores a present frame received and outputs a previous frame stored in the memory unit. The position unit generates pixel position information according to a display control signal of the present frame. The overdriving unit determines a corresponding relationship between several pixel grey values of the present frame and several display areas of a display panel according to the pixel position information, so as to select a corresponding specific table group of each of the pixel grey values from a plurality of overdriving tables. The overdriving unit further generates an overdriving frame by looking up the corresponding specific table group of each of the pixel grey values.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 14, 2011
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chun-Chieh Chiu, Yue-Li Chao, Chien-Hung Chen
  • Patent number: 7969446
    Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: June 28, 2011
    Assignee: NVIDIA Corporation
    Inventors: Edward A. Hutchins, Brian K. Angell, Paul Kim
  • Publication number: 20110057942
    Abstract: Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.
    Type: Application
    Filed: March 24, 2010
    Publication date: March 10, 2011
    Inventors: Michael Mantor, Michael Mang, Karl Mann
  • Patent number: 7864201
    Abstract: A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: January 4, 2011
    Assignee: Broadcom Corporation
    Inventors: Richard J. Selvaggi, Gary W. Root
  • Patent number: 7852341
    Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.
    Type: Grant
    Filed: October 5, 2004
    Date of Patent: December 14, 2010
    Assignee: Nvidia Corporation
    Inventors: Christian Rouet, Rui Bastos, Lordson Yue
  • Publication number: 20100271377
    Abstract: Data pixels defining first and second images are stored in first and second image buffers, respectively. A second image coordinate location within a display matrix of a display device having display pixels that have multiple stable states is stored in a memory. Data pixels of the first image are read from the first image buffer. If a data pixel read from the first image buffer is within the second image coordinate location, a data pixel from the second image buffer corresponding with the data pixel read from the first image buffer is read, and the data pixel read from the second image buffer is combined with the corresponding data pixel read from the first image buffer to generate a derived data pixel. Synthesized pixels corresponding with at least each of the data pixels of the second image are generated. The synthesized pixels respectively include the derived data pixels.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 28, 2010
    Inventors: Yun Shon Low, Eric Jeffrey
  • Patent number: 7821521
    Abstract: Embodiments of the present invention provide a seamless way to emulate legacy graphics processing on modern graphics hardware. In particular, in some embodiments, the present invention provides a way for modern GPUs to emulate the bitwise operations and rendering processes of previous generations of graphics hardware. The present invention utilizes a novel pixel shader program. The pixel shader program provides a texture lookup functionality that compensates for any missing bitwise functionality. When a bitwise operation is requested, the system will copy out the destination area to a temporary image. This temporary image is fed to the pixel shader program along with a precomputed texture. The texture is precomputed by the CPU for the various bitwise operations and acts as a lookup table for the requested operation. With the temporary image and precomputed texture, the shader program on the GPU can then emulate the legacy graphics operations seamlessly.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: October 26, 2010
    Assignee: Red Hat, Inc.
    Inventor: Adam Jackson
  • Patent number: 7796095
    Abstract: An image processing circuit, such as a graphics accelerator chip or any other suitable circuit, includes display output control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing gamma correction, image scaling, graphics or video overlaying, or other suitable processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer. Fixed function or dedicated, display type specific temporal processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: September 14, 2010
    Assignee: ATI Technologies ULC
    Inventor: David I. J. Glen
  • Patent number: 7755634
    Abstract: A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation and the second operation are associated with instructions selected from a predetermined instruction set.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 13, 2010
    Assignee: NVIDIA Corporation
    Inventors: John Erik Lindholm, Simon S. Moy, Robert Steven Glanville
  • Patent number: 7710427
    Abstract: Embodiments of the present invention include an arithmetic logic unit for use in a graphics pipeline. The arithmetic logic unit comprising a plurality of scalar arithmetic logic subunits wherein each subunit performs a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d. The arithmetic logic unit also for produces a result based thereon wherein “op” represents a programmable operation and wherein further the resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: May 4, 2010
    Assignee: NVIDIA Corporation
    Inventors: Edward A. Hutchins, Brian K. Angell
  • Patent number: 7675524
    Abstract: A system and method for performing convolutions on image data using pre-computed acceleration data structures is disclosed. The method may include calculating intermediate convolution values for each of a plurality of blocks of pixels by performing an associative operation on the pixel values in each block. Each intermediate value may be associated with the block and indexed dependent on index values of pixels in the block. An image pyramid may include intermediate convolution values for multiple levels of acceleration by calculating intermediate convolution values for multiple block sizes. A convolution result for a kernel of an image may be produced by performing the associative operation on intermediate convolution values for non-overlapping blocks enclosed within the kernel and on pixel values associated with pixels in the kernel but not in one of the non-overlapping blocks. The methods may be implemented by program instructions executing in parallel on CPU(s) or GPUs.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: March 9, 2010
    Assignee: Adobe Systems, Incorporated
    Inventors: Gavin S. P. Miller, Nathan A. Carr
  • Patent number: 7659909
    Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: February 9, 2010
    Assignee: NVIDIA Corporation
    Inventor: Edward A. Hutchins
  • Patent number: 7584242
    Abstract: The printing system of the present invention enables the display of information to an operator indicating that printing has been halted even when it is the host computer that causes the halt in printing. When a print data preview is set, a print processor reads print data from a spool file, generates a preview image using a printer graphics driver and provides that preview image to a previewer. A status monitor then monitors and displays the status of a printer and the print processor.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: September 1, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuhisa Ebuchi
  • Patent number: 7551177
    Abstract: Disclosed are methods and apparatus for accomplishing the fetching or sampling of channels of pixels or texels such as neighboring pixels or texels or non-neighboring pixels or texels in a simultaneous operation in order to achieve optimization of the performance of a texture pipeline. In particular, logic is disclosed including selector logic configured to retrieve data including a plurality of channels from each of a plurality of pixels or texels and operable to select one channel from the plurality of channels of the data from each of the pixels or texels. The logic also includes combination logic configured to combine two or more of the selected channels into a single vector, such as an RGBA vector representing the color.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: June 23, 2009
    Assignee: ATI Technologies, Inc.
    Inventors: Chris Brennan, John Isidoro, Anthony DeLaurier
  • Publication number: 20090046103
    Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 19, 2009
    Inventors: Tyson J. Bergland, Craig M. Okruhlica, Edward A. Hutchins, Michael J.M. Toksvig, Justin M. Mahan
  • Patent number: 7460130
    Abstract: Image acquisition refers to the taking of digital images of multiple views of the object of interest. In the processing step, the constituent images collected in the image acquisition step are selected and further processed to form a multimedia sequence which allows for the interactive view of the object. Furthermore, during the Processing phase, the entire multimedia sequence is compressed and digitally signed to authorize it viewing. In the Storage and Caching Step, the resulting multimedia sequence is sent to a storage servers. In the Transmission and viewing step, a Viewer (individual) may request a particular multi-media sequence, for example, by selecting a particular hyperlink within a browser, which initiates the downloading, checking of authorization to view, decompression and interactive rendering of the multi-media sequence on the end-users terminal, which could be any one of a variety of devices, including a desktop PC, or a hand-held device.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: December 2, 2008
    Assignee: Advantage 3D LLC
    Inventor: Marcos Salganicoff
  • Patent number: 7456838
    Abstract: A system, method and computer program product are provided for programmable vertex processing. Initially, a vertex program is identified including branch labels and instruction sequences with branch commands. The vertex program is then converted to a binary format capable of being executed by a hardware graphics pipeline. The vertex program may then be executed in the binary format utilizing the hardware graphics pipeline for transforming vertices. As an option, the vertex program is initially written in a textual format capable of being read by a human prior to being converted.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: November 25, 2008
    Assignee: NVIDIA Corporation
    Inventors: Patrick R. Brown, Mark J. Kilgard, Robert Steven Glanville
  • Patent number: 7327373
    Abstract: A four-time resolution refinement of 3D-dither algorithm is provided in this present invention. A 4×2 pixel-block is treated as an observed unit in this present invention, which includes two 2×2 pixel-blocks. In order to eliminate moving lines and dithered edges, the two least significant bits (LSBs) of the pixels are treated depending on cases. For the first 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is an upper-left, lower-right, lower-left, and upper-right sequence in a 2×2 pixel-block for four sequential frames. For the second 2×2 pixel-block, when 2-bit LSBs being 01 and 11, the pixel being assigned a carry is a lower-left, upper-right, upper-left, and lower-right sequence in a 2×2 pixel-block for four sequential frames. For both 2×2 pixel blocks, no pixel is treated for 2-bit LSBs being 00. For 2-bit LSBs being 10, the pixel row of the 4×2 block switches between the upper and the lower row for every frame.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: February 5, 2008
    Assignee: Novatek Microelectronics Corp.
    Inventor: Richard Hung