Abstract: The present application relates to a compensation method for a display and a display, wherein the method includes: acquiring a display image of the display; determining to-be-compensated regions corresponding to the display image, wherein the to-be-compensated regions include at least one first to-be-compensated region and at least one second to-be-compensated region; the display image is compensated based on the to-be-compensated regions, and a compensation mode of the at least one to-be-compensated region is different from a compensation mode of the at least one second to-be-compensated region.

Abstract: A test apparatus includes a mura detection filter for detecting a mura area based on a detected image signal and outputting position information of the mura area and a filtered image signal, an image enhancement processor for performing deblurring on the filtered image signal based on the position information and outputting a deblurred image signal, a mura corrector for generating first compensation data for the mura area based on the deblurred image signal, a sampling corrector for generating second compensation data for a non-mura area based on the detected image signal, and a compensator for outputting compensation data based on the first compensation data and the second compensation data.

Abstract: Systems and method to implement a geometry processing phase of tile-based rendering. The systems include a plurality of parallel geometry pipelines, a plurality of tiling pipelines and a geometry to tiling arbiter situated between the plurality of geometry pipelines and the plurality of tiling pipelines. Each geometry pipeline is configured to generate one or more geometry blocks for each geometry group of a subset of ordered geometry groups; generate a corresponding primitive position block for each geometry block, and compress each geometry blocks to generate a corresponding compressed geometry block. The tiling pipelines are configured to generate, from the primitive position blocks, a list for each tile indicating primitives that fall within the bounds of that tile. The geometry to tiling arbiter is configured to forward the primitive position blocks generated by the plurality of geometry pipelines to the plurality of tiling pipelines in the correct order based on the order of the geometry groups.

Abstract: Embodiments of a telemetry device and methods to convert a binary floating point number to a compressed number is described herein. The binary floating point number may comprise a mantissa and an exponent. The telemetry device may determine a first number based on a product of the exponent and a constant, wherein the constant may be proportional to a logarithm of the number two. The telemetry device may determine a second number using one or more bits of the mantissa as an index into a predetermined lookup table. Values of the lookup table may be proportional to logarithms of candidate mantissa values. The telemetry device may determine the compressed number based on rounding of a sum. The sum may include the first and second numbers. The rounding may be based on a predetermined step size.

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device such that, when a first refresh scan command is received from a host device, a first refresh scan operation for the plurality of memory blocks is performed and then a first refresh scan result for the first refresh scan operation is transmitted to the host device, and when a first refresh operation command is received from the host device, a first refresh operation for the nonvolatile memory device is performed.

Abstract: The image forming apparatus comprises a determination unit configured to determine whether or not corresponding image data is cached in accordance with an instruction for generation of image data for the file stored in the memory, and an image processing unit configured to generate image data for the file in a case that the determination unit determines that the corresponding image data is not cached. The image forming apparatus controls to skip generation of image data by the image processing unit in a case that the instruction for generation of image data for the file is an instruction for an anticipation cache of image data for the file, and a file type of the file is a second type requiring, for generation of image data, a longer amount of time than a first type.

Abstract: The invention provides a mura compensation method and system. The method comprises: Step 10: defining a position of a bright/dark boundary line as a first area, and defining an area outside the first area as a second area; Step 20: using a pixel as a unit to directly query each pixel in the first area in a preset first mura compensation data lookup table to obtain a corresponding first mura compensation data; and using a preset block as a unit to directly query each pixel in the second area in a preset second mura compensation data lookup table and calculate to obtain a corresponding second mura compensation data; Step 30: for pixels in first area, performing mura compensation on each pixel according to the corresponding first mura compensation data, and for pixels in second area, performing mura on each pixel according to the corresponding first mura compensation data.

Abstract: When executing a shader program to perform graphics shading operations in a graphics processor, the graphics processor determines for instructions to be executed for the shader program, whether to replace the instructions with alternative instructions, based on the nature of the instructions and the values of input operands to be processed by the instructions, and either retains an instruction or replaces the instruction with an alternative instruction, accordingly.

Abstract: A method of testing a camera for vision system for a vehicle includes providing a camera configured for mounting and use on a vehicle. The camera is operable at selected ones of a plurality of register settings. A test pattern is disposed in the field of view of the camera and at least two frames of image data are captured with the camera using different register settings having noise filtering at a respective one of at least two levels between a maximum noise filtering and a minimum noise filtering. The signal to noise ratio is measured for each of the at least two frames of captured image data. A texture value is measured for each of the at least two frames of captured image data. A compromise is selected between noise reduction and texture preservation.

Abstract: Methods and systems for enabling an augmented reality character to maintain and exhibit awareness of an observer are provided. A portable device held by a user is utilized to capture an image stream of a real environment, and generate an augmented reality image stream which includes a virtual character. The augmented reality image stream is displayed on the portable device to the user. As the user maneuvers the portable device, its position and movement are continuously tracked. The virtual character is configured to demonstrate awareness of the user by, for example, adjusting its gaze so as to look in the direction of the portable device.

Abstract: A monitoring apparatus using three-dimensional (3D) information of images includes: an image acquisition unit to acquire a two-dimensional (2D) image from a pan/tilt/zoom (PTZ) camera; an information extraction unit to extract 2D coordinate information of an object based on a pan/tilt angle of the PTZ camera and extract distance information between the PTZ camera and the object; an operation unit to calculate at least one of variation of the 2D coordinate information and the distance information by comparing a current frame and a previous frame of the 2D image, and variation of the 2D coordinate information and height information of the object by comparing a current frame and a previous frame of a 3D image of the object; and a position tracking unit to track a position of the object by controlling the PTZ camera based on the at least one of the two variations.

Abstract: Provided is point-based efficient three-dimensional (3D) information representation from a color image that is obtained from a general Charge-Coupled Device (CCD)/Complementary Metal Oxide Semiconductor (CMOS) camera, and a depth image that is obtained from a depth camera. A 3D image processing method includes storing a depth image associated with an object as first data of a 3D data format, and storing a color image associated with the object as color image data of a 2D image format, independent of the first data.

Abstract: Some embodiments of the invention pertain to a method for displaying a representation of a portion of a three-dimensional surface by rendering data representing physical features of the portion of the three-dimensional surface. The data may be apportioned into a multitude of tiles at a plurality of different detail levels. The representation may include a multitude of image pixels and/or a buffer being assigned to each image pixel. The method may also include identifying tiles that need to be rendered, and rendering the identified tiles. At least a portion of a tile may be displayed by a multitude of image pixels, by assigning an unambiguous distance value to each of the identified tiles, and storing a default buffer value in the buffers of the image pixels. The rendering may include comparing the buffer values of image pixels and the distance value of a presently rendered tile.

Abstract: A method for direct therapeutic treatment of myocardial tissue in a localized region of a heart having a pathological condition. The method includes identifying a target region of the myocardium and applying material directly and substantially only to at least a portion of the myocardial tissue of the target region. The material applied results in a physically modification the mechanical properties, including stiffness, of said tissue. Various devices and modes of practicing the method are disclosed for stiffening, restraining and constraining myocardial tissue for the treatment of conditions including myocardial infarction or mitral valve regurgitation.

Abstract: A method of generating white noise for use in graphic and image processing, in accordance with one embodiment of the present invention, includes receiving one or more hash inputs. The hash inputs may be one or more primitive coordinates, one or more texel addresses, a base image, a device identifier, or a user password. The one or more hash inputs are evaluated utilizing a cryptographic hash function. The output of the cryptographic hash function generates one or more white noise samples. The white noise samples may be utilized as texel data. The white noise samples may also be utilized for encrypting images.

Abstract: A method includes reading a composite video descriptor data structure and a plurality of window descriptor data structures. The composite video descriptor data structure defines a width and height of a composite video frame and each window descriptor data structure defines the starting X and Y coordinate, width and height of each constituent video window to be rendered in the composite video frame. The method further includes determining top and bottom Y coordinates for each constituent video window, as well as determining left and right X coordinates for each constituent video window. The method also includes dividing each constituent video window using the top and bottom Y coordinates to obtain Y-divided sub-windows, dividing each Y-divided sub-window using left and right X coordinates to obtain X and Y divided sub-windows, and storing X, Y coordinates of opposing corners of each X and Y divided sub-window in the storage device.

Abstract: Systems and methods are provided for cross-platform rendering of video content on a user-computing platform that is one type of a plurality of different user-computing platform types. A script is transmitted to the user-computing platform and is interpreted by an application program compiled to operate on any one of the plurality of user-computing platform types. Transmitting the script causes the script to be interpreted by the application program operating on the user-computing platform to cause the interpreted script to directly decode encoded video data transmitted or otherwise accessible to the user-computing platform into decoded video data and to further cause the rendering of the decoded video data.

Abstract: The present disclosure concerns a method and system to accurately remove a three-dimensional distortion in an image of a document and convert the image into an accurate two dimensional image. A method for accurately deducing an image of a document to a precise document boundary is also disclosed. A portable computing device may employ the disclosed method and system. The methods involve a marker embedded in a document which provides three-dimensional positional information of a recording device with reference to the marker continuously in real time.

Abstract: A method, medium, and system efficiently rendering 3 dimensional (3D) graphics data. The rendering method includes calculating the strength of a fog effect that is to be applied to graphics data, determining whether texture mapping must be performed on the graphics data, according to the strength of the fog effect, and performing the texture mapping according to the determination result. Accordingly, it is possible to reduce the number of memory access operations for reading textures.

Abstract: In one embodiment, a method comprises detecting, by a hardware accelerator, that a value has been written to a first location of a memory, the first location identified by a first address. The method further includes adding the value to an accumulated value stored in an accumulator register of the hardware accelerator and storing the result in the accumulator register. The method further includes comparing the value to a maximum value stored in a first register of the hardware accelerator and overwriting the maximum value with the value if the value is greater than the maximum value. The method also includes comparing the value to a minimum value stored in a second register of the hardware accelerator and overwriting the minimum value with the value if the value is less than the minimum value.

Abstract: A display driver that receives display line data of plural display lines to perform drive control on a display panel includes a line memory for storing display line data which is supplied from the outside. The display driver includes a logic circuit that controls write and read-out of the display line data in and from the line memory, and sorts pixel data of the display line data using read out data from the line memory, to generate display drive data. Drive circuits drive the display panel in units of display lines based on the drive data which is output from the logic circuit. The drive circuits are separately arranged on both sides of the logic circuit and the line memory which are interposed therebetween. The storage capacity of the line memory corresponds to the number of lines smaller than the number of display lines of a display frame.

Abstract: A memory access address translating apparatus and method may each classify pixels included in an input image into a plurality of tiles, and may generate a new memory for each of the successive tiles to enable the successive tiles, among a plurality of tiles, to be stored in different banks.

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: Methods and systems for interacting with multiple three-dimensional (3D) object data models are provided. An example method may involve providing to a display device for display a first 3D object data model and a second 3D object data model. Information associated with a modification to the first 3D object data model may be received. Based on the received information, a same change may be applied to the first 3D object data model and applied to the second 3D object data model to obtain a first modified 3D object data model and a second modified 3D object data model. According to the method, the first modified 3D object data model and the second modified 3D object data model may be provided to the display device for substantially simultaneous display.

Abstract: An example of a controller circuit may include a policy module to generate a power reduction policy output based on a processor power state input. The power reduction policy output may also be generated based on a graphics render engine idleness input. The circuit can also include a clock masking cell to apply a clock masking configuration to a graphics render clock trunk based on the power reduction policy output.

Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values for different attribute types (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel packet rows including the pixel surface attribute values are forwarded to other graphics pipeline stages for single thread processing (e.g. to a universal arithmetic logic unit capable of performing multiple graphics functions on the pixel surface attribute values).

Abstract: Systems and methods of determining motion vectors, such as for video encoding, are disclosed. In one example, motion vectors are determined for a current frame, using sampled pixel information from a reference frame. Sampled pixel information is obtained using a sampling pattern. The sampling pattern, in one example, includes subsampling pixels at different rates for horizontal and vertical directions. The subsampling rate can differ, based on an amount of motion represented by a matching block (e.g., the farther a match is found away from an origin of the block, the more subsampling can be done). In another example, a full pixel resolution is maintained proximal an original location of the block; as distance increases in one or more directions, subsampling can begin and/or increase. Sampled pixels can be stored. Interpolation of the sampled pixels can be performed and the sampled and resulting interpolated pixels can be used for comparison.

Abstract: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

Abstract: An image processing apparatus is configured to rasterize an object into a bitmap using a first memory and a second memory which can be accessed quicker than the first memory. The image processing apparatus includes an extraction unit configured to extract a plurality of objects to be rasterized on the second memory from a plurality of the objects, and a first combination unit configured to combine a plurality of objects which can be rasterized within capacity of the second memory from among the objects extracted by the extraction unit into an object.

Abstract: A computer readable medium embodies a set of instructions. The set of instructions includes an instruction to manipulate a processor to determine a first value representative of a source memory location of a source storage component, a second value representative of a destination memory location of a destination storage component, a third value representative of a number of lines of a data block to be transferred from the source storage component to the destination storage component, a fourth value representative of a number of bytes to be transferred per line of the data block, a fifth value representative of a byte width of the source storage component and a sixth value representative of a byte width of the destination storage component. The instruction further is to transfer a data block from the source storage component to the destination storage component based on the first, second, third, fourth, fifth and sixth values.

Abstract: A circuit arrangement and method perform concurrent texture processing of groups of pixels with a single instruction multiple data (SIMD) execution unit to improve the utilization of the SIMD execution unit when performing scalar operations associated with a texture processing algorithm. In addition, when utilized in connection with a multi-threaded SIMD execution unit, groups of pixels may be concurrently processed in different threads executed by the SIMD execution unit to further maximize the utilization of the SIMD execution unit by reducing the adverse effects of dependencies in scalar and/or vector operations incorporated into a texture processing algorithm.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: The current invention involves new systems and methods for computing per-sample post-z test coverage when the memory is organized in multiple partitions that may not match the number of shaders. Shaded pixels output by the shaders can be processed by one of several z raster operations units. The shading processing capability can be configured independent of the number of memory partitions and number of z raster operations units. The current invention also involves new systems and method for using different z test modes with multiple render targets with a single or multiple memory partitions. Rendering performance may be improved by using an early z testing mode is used to eliminate non-visible samples prior to shading.

Abstract: A graphics processing unit (GPU) efficiently performs 3-dimensional (3-D) clipping using processing units used for other graphics functions. The GPU includes first and second hardware units and at least one buffer. The first hardware unit performs 3-D clipping of primitives using a first processing unit used for a first graphics function, e.g., an ALU used for triangle setup, depth gradient setup, etc. The first hardware unit may perform 3-D clipping by (a) computing clip codes for each vertex of each primitive, (b) determining whether to pass, discard or clip each primitive based on the clip codes for all vertices of the primitive, and (c) clipping each primitive to be clipped against clipping planes. The second hardware unit computes attribute component values for new vertices resulting from the 3-D clipping, e.g., using an ALU used for attribute gradient setup, attribute interpolation, etc. The buffer(s) store intermediate results of the 3-D clipping.

Abstract: A filter circuit includes: an adder/subtractor that performs at least addition; and a shifter that performs multiplication/division by a power of two through a shift operation. The adder/subtractors and the shifter are configured to obtain a first calculation result representing a pixel value of a target pixel included in image data multiplied by a first filter coefficient. At least the adder/subtractors and the shifter is configured to obtain a second calculation result representing pixel values of a plurality of peripheral pixels adjacent to the target pixel, with each of the pixel values being multiplied by a second filter coefficient. The adder/subtractor is configured obtain a third calculation result by adding the first and second calculation results. The shifter configured to divide the third calculation result by a power of two which is equivalent to a sum of the first and second filter coefficients, so as to output the division result.

Abstract: An apparatus is provided for determining motion between a first and second video image. The apparatus includes an input device for receiving the first and the second video image with a plurality of pixels, a block selector for selecting a block of pixels within the first video image, a search area selector for selecting at least part of the second video image to produce a search area, a sampler for sampling the pixels of the search area in a predetermined pattern and a comparator for comparing the selected block of pixels within the first video image with at least one block of the sampled pixels of the search area to determine the motion of the block of pixels between the images. The pattern of sampled pixels varies throughout the search area.

Abstract: A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plurality of channels, the direct memory access controller further communicates with a memory and a processor. The memory stores two sets of control data for each of the plurality of channels and for the processor. The direct memory access controller is responsive to a data transfer request received from one of said plurality of channels or from said processor to access one set of said corresponding control data stored in said memory, said direct memory access performing at least a portion of said data transfer requested in dependence upon said accessed control data.

Abstract: The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.

Abstract: An overdriving apparatus including a memory unit, a position unit and an overdriving unit is provided. The memory unit stores a present frame received and outputs a previous frame stored in the memory unit. The position unit generates pixel position information according to a display control signal of the present frame. The overdriving unit determines a corresponding relationship between several pixel grey values of the present frame and several display areas of a display panel according to the pixel position information, so as to select a corresponding specific table group of each of the pixel grey values from a plurality of overdriving tables. The overdriving unit further generates an overdriving frame by looking up the corresponding specific table group of each of the pixel grey values.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: Disclosed herein are methods, apparatuses, and systems for accessing vertex data stored in a memory, and applications thereof. Such a method includes writing vertex data of primitives into contiguous banks of a memory such that the vertex data of consecutively written primitives spans more than one row of the memory. Vertex data of two consecutively written primitives are read from the memory in a single clock cycle.

Abstract: A method for processing video image data including a plurality of different image data types begins by providing tasks to be performed on each different image data type. The image data is divided into a plurality of groups based on the image data type. A set of arithmetic operations required to accomplish the tasks provided for the corresponding image data type is determined. Each arithmetic operation is assigned to one of a plurality of commonly used arithmetic units which performs the arithmetic operation, whereby each image data type is transformed in accordance with the corresponding provided tasks. The transformed image data of each group is combined, completing the processing.

Abstract: A method and system for patching instructions in a 3-D graphics pipeline. Specifically, in one embodiment, instructions to be executed within a scheduling process for a shader pipeline of the 3-D graphics pipeline are patchable. A scheduler includes a decode table, an expansion table, and a resource table that are each patchable. The decode table translates high level instructions to an appropriate microcode sequence. The patchable expansion table expands a high level instruction to a program of microcode if the high level instruction is complex. The resource table assigns the units for executing the microcode. Addresses within each of the tables can be patched to modify existing instructions and create new instructions. That is, contents in each address in the tables that are tagged can be replaced with a patch value of a corresponding register.

Abstract: Data pixels defining first and second images are stored in first and second image buffers, respectively. A second image coordinate location within a display matrix of a display device having display pixels that have multiple stable states is stored in a memory. Data pixels of the first image are read from the first image buffer. If a data pixel read from the first image buffer is within the second image coordinate location, a data pixel from the second image buffer corresponding with the data pixel read from the first image buffer is read, and the data pixel read from the second image buffer is combined with the corresponding data pixel read from the first image buffer to generate a derived data pixel. Synthesized pixels corresponding with at least each of the data pixels of the second image are generated. The synthesized pixels respectively include the derived data pixels.

Abstract: Embodiments of the present invention provide a seamless way to emulate legacy graphics processing on modern graphics hardware. In particular, in some embodiments, the present invention provides a way for modern GPUs to emulate the bitwise operations and rendering processes of previous generations of graphics hardware. The present invention utilizes a novel pixel shader program. The pixel shader program provides a texture lookup functionality that compensates for any missing bitwise functionality. When a bitwise operation is requested, the system will copy out the destination area to a temporary image. This temporary image is fed to the pixel shader program along with a precomputed texture. The texture is precomputed by the CPU for the various bitwise operations and acts as a lookup table for the requested operation. With the temporary image and precomputed texture, the shader program on the GPU can then emulate the legacy graphics operations seamlessly.

Abstract: An image processing circuit, such as a graphics accelerator chip or any other suitable circuit, includes display output control logic that is operative to receive a current frame of information from a frame buffer and is operative to process a current frame, such as by providing gamma correction, image scaling, graphics or video overlaying, or other suitable processing, to produce a processed current display frame and stores the processed current display frame back in the frame buffer. Fixed function or dedicated, display type specific temporal processing logic receives the processed current display frame stored in the frame buffer and also obtains at least one previous processed current display frame from the frame buffer and temporally processes pixels from each of the processed current display frame and the previous processed current display frame to produce a temporally compensated display frame for a specific type of display.