Abstract: Systems and methods for managing memory are disclosed. In one embodiment, a first data structure is generated, where the first data structure is associated with one or more virtual addresses mapped to one or more physical addresses of the memory. A size of the first data structure is based on a characteristic of the memory. Data to be stored in the memory is received, and a virtual address of the one or more virtual addresses is identified based on the first data structure. The virtual address is mapped to a physical address, and the data is stored in the physical address. The first data structure is updated based on the storing of the data.

Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.

Abstract: An image processing device and an image processing method are provided. A frame divider divides an original frame into a plurality of divided blocks. A multi-core circuit coupled to the frame divider and includes a plurality of processing cores and a frame stitching circuit. The processing cores perform an image processing process on the divided blocks to generate a plurality of processed frame blocks. The frame stitching circuit performs an image stitching process according to the processed frame blocks to generate a processed frame. The processing cores fetch the divided blocks and a plurality of extension pixels extending from the divided blocks to perform the image processing process, and a column number of the extension pixels is configured according to a window size requested by at least one window algorithm of the image processing process.

Abstract: Apparatus and method for resilient interface for updating a graphics processor.

Abstract: Examples of the present invention provide a method of converting a multicast stream into unicast segments. In particular, sequence identifiers are generated based on a clock reference field in the transport stream packets that make up the multicast stream. Every time a new sequence identifier is calculated, a new unicast segment is generated and assigned with the new sequence identifier. Transport stream packets are placed into the new segment until a packet is processed that causes a new sequence identifier to be generated, at which point another new segment is generated and packets placed into that segment. In an improved method, random access indicators in the transports stream packets are used to further constrain when a new segment is generated, to ensure that new segments are coincident with a packet having a random access indicator. This improvement makes random access easier back and forth between and within a stream.

Abstract: Systems and techniques for testing audio-video synchronization using one or more timestamps are presented. On a media sender end, a media stream with a video stream and an audio stream is generated. A matrix barcode timestamp is added onto a video frame of the video stream at a particular time. Furthermore, a tone timestamp is embedded into the audio stream at the particular time. Additionally, on a media receiver end, a modified media stream is received. For example, the video stream with the matrix barcode timestamp at the particular time and the audio stream with the tone timestamp at the particular time are received. The matrix barcode timestamp is decoded to determine a first time value and the tone timestamp is decoded to determine a second time value. The first time value is compared with the second time value to determine synchronization of the video stream and the audio stream.

Abstract: A data processing circuit for performing a de-interleaving process in a DVB-T2 system is provided. The data processing circuit includes: a buffer, buffering a plurality of data symbols; a memory, coupled to the buffer; an address generator, generating a plurality of addresses according to an operation logic and a permutation rule, and selecting and outputting a target address from the addresses; and a memory controller, coupled to the memory, the buffer and the address generator, writing the target data into the memory according to the target address, or/and reading the target data from the memory according to the target address, until the data symbols are de-interleaved when the data symbols are read from the memory.

Abstract: An image processing device includes: first to third address registers that store three addresses, respectively, the three addresses indicating three bank regions, respectively; an input image bank managing unit that, when the image processing device receives an image from an imaging device, switches, between the first address register and the second address register, and sets a flag and supplies the address stored in the first address register as an address for writing the received image; an imaging processing unit that performs image processing on the received image; and an image processing bank managing unit that, when the flag is in a set state and the processed image is switched to another image to be processed, switches, between the second address register and the third address register, resets the flag and supplies to the image processing unit the address stored in the third address register.

Abstract: A system, method, and computer program product are provided for changing a display refresh rate in an active period. In operation, a request is received to change a display refresh rate. Further, in response to the request, the display refresh rate is changed in an active period during which pixels are being written to a display device.

Abstract: A method for compressing normal maps in a computer system. The method includes accessing a map of input normals. A memory block having a first portion and a second portion is defined. A table of indices is stored in the first portion of the memory block and a table of normals is stored in the second portion of the memory block. The indices of the first portion of the memory block reference the normals of the second portion. The normals in the second portion of the memory block are unit normals of a sphere defined to represent the map of input normals.

Abstract: Each block of texture data elements is encoded as a block of texture data that includes a set of integer values to be used to generate a set of base data values for the block, and a set of index values indicating how to use the base data values to generate data values for the texture data elements that the block represents. The integer values and the index values are both encoded in an encoded texture data block using a combination of base-n values, where n is greater than two, and base-2 values. Predefined bit representations are used to represent plural base-n values (n>2) collectively, and the bits of the bit representations representing the base-n values are interleaved with bits representing the base-2 values in the encoded texture data block.

Abstract: An image processing apparatus which is allowed to achieve a higher speed of a labeling process than ever before is provided. Sequential scanning is performed on pixels in a picked-up image represented by binarized data Din. Moreover, during the sequential scanning, while label information representing an identification number for each connected region in the picked-up image is, as occasion arises, allocated to a target pixel based on values of pixel data of the target pixel and neighboring pixels thereof, additional information (position information and area information) for each connected region corresponding to each label information is updated as occasion arises. Thereby the label information, the position information and the area information about the whole picked-up image are obtained by one sequential scanning process.

Abstract: An apparatus configured to match an input frame rate of a video stream with an output frame rate of an output stream, the apparatus comprising, at least one memory buffer, an output frame generator, and a threshold measurement unit, the threshold measurement unit configured to generate a control feedback, wherein the box is configured to analyze the control feedback to monitor a state of the at least one memory buffer, the threshold measurement unit further configured analyze the control feedback to regulate between two or more different settings, wherein the two or more different settings include slowing down or speeding up the output frame, wherein the two or more different settings further include slowing down or speeding up of the line rate of the output stream.

Abstract: A telephone book data processor includes: a connection element for connecting to an external device via a short range communication manner to transfer a telephone book data; a telephone book data obtaining element for obtaining the telephone book data; a memory having multiple memory regions for storing the telephone book data; and a controller for executing a telephone book data transfer process and a telephone book data utilizing process. The controller defines one memory region as an object of the telephone book data transfer process and another memory region as an object of the telephone book data utilizing process. The controller executes the telephone book data utilizing process with using the telephone book data in the another memory region while the controller executes the telephone book data transfer process for storing a new telephone book data in the one memory region.

Abstract: A method and apparatus for display of a digital video signal includes a demodulator capable of receiving a major channel of the digital video signal. The major channel of the digital video signal includes one or more minor channels, wherein the minor channels are specific and separate channels of broadcast information. The method and apparatus for display of a digital video signal further includes decoders coupled to the demodulator, wherein the decoders receive the minor channels disposed within the major channel. The decoders thereupon generate minor channel video signals, wherein the minor channel video signal includes the video information for each associated channel. The method and apparatus further includes receiving the incoming video signals and format the video signals for simultaneous display of active video from multiple channels. A display configurator provides the minor channel video signals to an output display, to actively display the minor channels.

Abstract: An image processing apparatus according to the present invention includes a plurality of input units configured to correspond to respective image data items to be obtained, an obtaining unit configured to obtain the image data items corresponding to the input units when the input units are operated, a determination unit configured to determine, when one of the input units is operated within a predetermined period of time, layout for displaying a corresponding one of the image data items in a display unit, and configured to determine, when at least two of the input units are operated within the predetermined period of time, layout for displaying image data items corresponding to the operated input units in the display unit in parallel, and an output unit configured to generate display data for a single screen using at least one of the image data items obtained using the obtaining unit in accordance with the layout determined using the determination unit and output the display data to the display unit.

Abstract: A method for programming extended display identification data (EDID) adapted to a display device is provided. The display device has at least one EDID chip, a microcontroller unit chip, and a flash memory chip. in the method, a first EDID corresponding to the EDID chip is written into a firmware stored in the flash memory chip. The display device is powered on. The first EDID in the firmware is automatically written into the corresponding EDID chip as a second EDID by the microcontroller unit chip.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.

Abstract: The disclosure discloses an image copying method, which includes the steps of: copying, an image to be copied, to a destination address line by line, in the case of the image to be copied having a width of one pixel; copying, the image to be copied, to the destination address by a number of bytes according to a size of the image to be copied, in the case of the image to be copied not having a width of one pixel. The image copying method can save the image copying time and deduce the Central Processing Unit (CPU) occupation rate.

Abstract: A mechanism on a server divides a page of content into sections defined by dividers, and renders the page stream with dividers to a browser. The browser reads the web page with dividers, and partitions the DOM for the page to create partitions in the DOM according to the sections in the page. Partitioning the DOM allows scripts in each partition to be scoped according to defined access rights for each partition. In this manner, a script in one DOM partition cannot access information in another DOM partition unless the access rights for the partition that contains the script allow it. By scoping scripts to appropriate DOM partitions, potential hacker attacks may be prevented.

Abstract: A method, implemented by a computer system, and a system of organizing data of a wide area motion imagery frame and a method and a system of retrieving objects that match a user defined AOI from an image in a WAMI frame in a WAMI collection are described. The method of organizing includes dividing, by the computer system, an image of a WAMI frame into a plurality of tiles, each tile in the plurality of tiles comprising a plurality of pixels and having a pixel width and a pixel height; storing, by the computer system, the plurality of tiles as objects in an OSD, each object having an object identifier (OID); collecting, by the computer system, object identifiers (OIDs) of the objects; and storing, by the computer system, the OIDs in the OSD.

Abstract: A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Abstract: A data transfer circuit that transfers a first kind of data stored in an external memory circuit includes: an internal memory circuit that is capable of, by an external circuit, writing and/or rewriting a second kind of data including information for one region as a transfer source in the external memory circuit and another region as a transfer destination in the external memory circuit; a transfer circuit that transfer the first kind of data; and a control circuit that makes the transfer circuit transfer the first kind of data stored in the one region to the other region based on the second kind of data.

Abstract: A drawing processing apparatus is disclosed. A graphic index of a graphic included in a display screen or graphic description information which includes a setting parameter to be applied to the graphic is determined for each of regions dividing the display screen. A data size of the graphic description information is aggregated for the regions. A start address in a memory is determined to store the graphic description information into a successive storage area in the memory, based on the aggregated data size. The data size of an area of an overflow occurrence target is stored when the overflow occurs. The graphic description information of the regions is successively written from the start address when the overflow does not occur. A write process is stopped, and resumed from the area of the overflow occurrence target by using the data size when the overflow occurs.

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract: An apparatus and method of caching a frame is provided. The method of caching a frame includes receiving information on a frame to be cached from a main storage unit, setting an initial value of a specified mode using the received information, and caching the frame from the main storage unit using the specified mode.

Abstract: In an embodiment, a display pipe includes one or more translation units corresponding to images that the display pipe is reading for display. Each translation unit may be configured to prefetch translations ahead of the image data fetches, which may prevent translation misses in the display pipe (at least in most cases). The translation units may maintain translations in first-in, first-out (FIFO) fashion, and the display pipe fetch hardware may inform the translation unit when a given translation or translation is no longer needed. The translation unit may invalidate the identified translations and prefetch additional translation for virtual pages that are contiguous with the most recently prefetched virtual page.

Abstract: A method and device that allow picture slices of a video stream to be processed in an order different than the order they were received is disclosed. Information mapping the location of picture slices that are stored in the order they were received is stored to allow subsequent processing to access the picture slice in any order, including render order.

Abstract: An image processing system includes a memory for storing data associated with pixels of images, with the pixels having spatial coordinates in an image coordinate system having first and second axes; a processing device including a processor which processes the associated data; and an interface device which accesses in memory addresses associated with pixels of a block of pixels. In the interface device, access information is received indicating a base memory address, information regarding the dimensions of the block along the axes of the image coordinate system, and a storage method. At least one access rule is selected from multiple rules as a function of the storage method. The memory is accessed at the addresses associated with the pixels in the block, by applying the selected rule starting from the base address and taking into account the dimensions of the block.

Abstract: A reproducing apparatus and method includes a reproducing unit to reproduce mainstream data and sub audio data separately added in the mainstream data, wherein the reproducing unit comprises a counter used in reproducing the sub audio data. Accordingly, it is possible to more naturally reproduce still image data, such as a browsable slide show, to which sub audio data is additionally included, thus preventing an interruption in reproduction of the sub audio data even during a forward or reverse play.

Abstract: The invention discloses an image capturing device and an image delivery method which is suitably applied to a video conference. The video conference is held between a local terminal and a remote terminal through a network. The device comprises a processor, a video encoder, an encryption engine and a data transmitting interface. The processor is used to process an original video signal for generating a first video signal and a second video signal. The video encoder is for receiving and compressing the first video signal. The encryption engine is for encrypting the compressed first video signal. The data transfer interface is for transmitting the compressed and encrypted first video signal and the second video signal to the local terminal. Wherein, the first video signal is transmitted to the remote terminal by the local terminal through the network and recovered by the remote terminal, and the second video signal is presented at the local terminal.

Abstract: A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.

Abstract: A push buffer-related system, method and computer program product are provided. Initially, an entry is obtained from a buffer storage describing a size and location of a portion of a push buffer. To this end, the portion of the push buffer is capable of being retrieved, utilizing the entry from the buffer storage.

Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.

Abstract: Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented in raster order. The hardware adds algebraic noise to the image to be dithered, and thresholds the result.

Abstract: A “Variable-Rate Perfect Hasher” maps sparse variable-rate data of one or more dimensions into a hash table using a perfect hash function. In various embodiments, perfect hash tables are populated by first computing offset table address for each data point of a domain of sparse variable-rate data elements. Offset vectors are then computed for each offset table address based in part on the size of each data element by evaluating offset vectors in order of a sum of the data point addresses mapping to each offset vector. These offset vectors are then stored in the offset table. For each data point, the corresponding offset vector is then used to compute a hash table address. Data elements are then perfectly hashed into the hash table using the computed hash table addresses. The resulting hash tables support efficient random access of the variable-sized data elements stored therein.

Abstract: In a method of programming for image enhancement, a content addressable memory is accessed. At least one template is transferred into the content addressable memory. A random access memory is accessed. Enhancement data is transferred into the random access memory. Video data input is inputted into the content addressable memory. Enhancement data is outputted from the random access memory based on the video data matching at least one template.

Abstract: Presented herein are a system, method, and apparatus for retrieving an object from memory. The object can be stored in a manner, such that the first byte of the object and the last byte of the object are in the middle of the memory data words. The object is retrieved by a direct memory access controller. The direct memory access controller, when provided with a read transaction with the starting address and the ending address of the object, retrieves the data words storing the object, and overwrites the portions of the data word that precede and follow the object.

Abstract: A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in tiles or color data in tiles, and a mode for allocating tile data among partitions in a partitioned memory.

Abstract: A memory device, a signal processing apparatus, and an image signal processing apparatus and signal processing methods configured to perform matching processing with a small amount of calculation and accurately detecting motion vectors, provided with a memory for converting by using a feature including a pixel value in a certain block range having a focused pixel at its center as an address based on information of a reference frame stored in a second frame memory; and a matching portion for reading storage information of the ME memory by using a feature of a focused pixel included in information of a current frame supplied from a first frame memory as a feature address, calculating a distance between the focused pixel in the current frame and a feature address (position coordinates) read from the ME memory, and detecting differential coordinates based on position information having the minimum distance from a plurality of candidates as motion vectors of the focused pixel.

Abstract: The present invention provides a virtual machine system and a method of accessing a graphics card. The virtual machine system includes a VMM, an SOS and at least one GOS, and further includes a resource converting module for performing IO address converting on graphics card framebuffer accessing data from GOS(s) or mapping MMIO(s) to physical MMIO(s) of a graphics card based on a resource converting table, and sending the processed data to the graphics card; and a framebuffer allocating module for dividing a framebuffer resource of the graphics card into multiple blocks and allocating them respectively to corresponding GOS(s). The resource converting table(s) records correspondences between a resource allocation for the graphics card by SOS and a resource allocation for the graphics card by GOS(s). The framebuffer MMIO resource(s) allocated to the graphics card by GOS(s) is/are the framebuffer allocated to GOS(s) by the framebuffer allocating module.

Abstract: In a display device which arranges a memory part for every display pixel, an erroneous operation of the memory part and the power consumption can be reduced. In a display device provided with a display panel which includes a plurality of display pixels, video lines which apply video data to the display pixels, and scanning lines which apply a scanning voltage to the display pixels, the display pixel includes a memory part which stores the video data, a pixel electrode, and a switching part which selectively applies a first video voltage or a second video voltage which differs from the first video voltage to the pixel electrode in response to the video data stored in the memory part.

Abstract: A display controller includes a memory storing at least three frames of image data, a write starting address register to which a write starting address is set, a read starting address register to which a read starting address is set, and a rotation control section performing control for reading out from the memory image data corresponding to an image whose orientation is rotated. When writing of the image data to the area designated by the write starting address is completed, the write starting address is updated and the previous value of the updated write starting address is set to the read starting address register. The image data corresponding to the rotated image is read out by the rotation control section 40 from an area of the memory designated by the read starting address, and then supplied to a display driver.

Abstract: In one embodiment of the present invention, LUTs (T3) through (T5) are stored in a table memory. When an overshoot calculation section switches over from the LUT (T4), which is being used, to the LUT (T5), the overshoot calculation section obtains the LUT (T5) not out of an external memory but out of the table memory. At this time, in order that the overshoot calculation section can switch over quickly from the LUT (T5) to an LUT (T6) at the next time, a table managing section deletes, from the internal memory, the LUT (T3) to which the LUT (T5) does not switch over directly, meanwhile the table managing section obtains the LUT from the external memory so as to store the LUT (T6) in the table memory. With the arrangement, it becomes possible for a drive circuit to (i) operate at the same processing speed as a drive circuit in which all tables are stored in the internal memory, and simultaneously, (ii) reduce the amount of memory.

Abstract: A method and system for performing texture mapping across adjacent texture maps. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of determining whether a texel crosses a boundary of a first texture map, examining a first texture state identifier associated with the first texture map, and requesting for a second texture state identifier associated with a second texture map that is adjacent to the first texture map to enable traversal to the second texture map to access the texel if the first texture state identifier includes a mode indicative of wrapping to an adjacent texture map and texture adjacency information that points to a second texture map.

Abstract: A storage method for a gamma value look-up table comprises storing gamma values corresponding to grays exceeding or equaling a 33rd gray in the gamma value look-up table, and calculating gamma values corresponding to a 1st gray to a 32nd gray by a formula.

Abstract: A time for displaying bitmap data is shortened, and the volume of a font table is reduced. A table having all records from start 0000h to end FFFFh is used as a pointer table which imparts a start address of bitmap data. A start address of bitmap data is stored in each of the records. Thereby, the character code directly accesses a corresponding record, to thus acquire a start address. Further, the volume of a font table is diminished by means of combined use, as pointer tables, of a first pointer table from which unused character code areas are removed and a second pointer table which specifies an address positional relationship between the respective character code areas achieved before removal and the respective character codes achieved after removal.

Abstract: Circuits, methods, and apparatus that provide an L2 cache that services requests out of order. This L2 cache processes requests that are hits without waiting for data corresponding to requests that are misses to be returned from a graphics memory. A first auxiliary memory, referred to as a side pool, is used for holding subsequent requests for data at a specific address while a previous request for data at that address is serviced by a frame buffer interface and graphics memory. This L2 cache may also use a second auxiliary memory, referred to as a take pool, to store requests or pointers to data that is ready to be retrieved from an L2 cache.

Abstract: Performing color management of color image data using a device transform by generating an identifier key based on contents of a color measurement profile for a color device, the color measurement profile containing measurement data corresponding to the color device, determining if a device transform corresponding to the identifier key is present in a device transform cache disposed in a persistent memory, loading, in the case that it is determined that a device transform corresponding to the identifier key is present in the device transform cache, the device transform into a program-accessible transient memory, generating, in the case that it is determined that a device transform corresponding to the identifier key is not present in the device transform cache, a device transform based on the measurement data in the color measurement profile, and storing the generated device transform in the device transform cache in correspondence with the identifier key, and transforming the color image data based on the dev

Abstract: Methods are disclosed for selectively loading one control at a time based on the location of a selection component relative to a graphical representation of a user interface.