Abstract: Circuits, methods, and apparatus for efficiently storing page characteristics. Page characteristics for memory pages are stored post address translation using addresses for physical locations in memory, for example, in a bit vector. The characteristics may include access or dirty bits, as well as other types of information. These bit vectors can also be stored and accumulated to generate histogram data. Two bit vectors may be included, while a first bit vector is written to, another is used. After data has been written to the first, the bit vectors are flipped, and data is written to the second while the first is used.

Abstract: Provided are methods, systems, and graphics processing apparatus, for improving graphics system performance using a data dependent slot and set selection technique for receiving texture data into an L2 cache for providing a high utilization of system resources in a diverse texture processing environment.

Abstract: In a method and system for controlling rotation of a color image stored as sub-sampled image data in a memory, a controller includes a finite state machine (FSM) operable to fetch the sub-sampled image data and provide the sub-sampled data as a plurality of pixels to form the color image having a predefined angle of rotation. The FSM provides a predefined address of sub-sampled image data describing the color image stored in the memory to an addressing unit. The addressing unit is operable to read twice the sub-sampled image data located at the predefined address. A memory device is operable to push each read instance of the sub-sampled image data. A pipeline controlled by the FSM is operable to pull and selectively read the sub-sampled image data from the memory device for generating the plurality of pixels.

Abstract: Embodiments include storing graphics instructions at addresses in a memory in an original order, and storing in the memory pointers associated with each instruction pointing to the addresses of the instructions in the original order. A first pointer associated with a first graphics instruction may then be moved from pointing to a first address of the first graphics instruction to point to a second address of a second graphics instruction. Likewise, a second pointer associated with the second graphics instruction may be moved from pointing to the second address to point to the first address by accessing the first pointer before moving the first pointer to determine that the second pointer is to point to the first address (e.g., the address the first instruction points to before being moved). Afterwards, the instructions may be re-ordered into an optimized order for compiling, by switching them to different addresses according to the pointers.

Abstract: An image processing apparatus, able to improve the pixel fill rate and able to prevent an increase of memory resources and increase of memory access, provided with a color calculation circuit for performing pixel level processing based on supplied first attribute parameters of the Z and color (R, G, B) data and outputting second attribute parameters and (x, y) coordinate data supplied by a DDA circuit together with the results and a sub primitive generation circuit for expanding a plurality of stamps to a plurality of sub primitives (sub stamps) based on the second attribute parameters of the color calculation circuit, generating expanded coordinates corresponding to the expanded sub stamps based on the (x, y) coordinate data of the DDA circuit, and outputting the same as the drawing parameters after expansion and the expanded graphics drawing coordinates to a memory controller, and a method of the same.

Abstract: A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.

Abstract: A method and apparatus for eliminating artifacts in images formed using more than one image segment. A buffer region associated with two adjacent image segments is defined wherein the intensity levels of the pixels are attenuated. When image segments substantially overlap in the buffer region, the intensity in the buffer region substantially sums to full scale. The intensity of the pixels in the buffer region is preferably attenuated using a device to modulate the intensity of the source of radiation.

Abstract: A display driver, electro-optical device and electronic appliance are provided that make unnecessary processing that calculates positions in a RAM where display data is to be written according to a mounting state thereof. A display driver includes a mounting state setting register in which mounting state setting data showing a mounting state of the display driver is set, a RAM that stores display data, a row scanning flag generation circuit that generates a row scanning flag showing a scanning direction of row addresses based on the mounting state setting data, a row address decoder that decodes row addresses in accordance with the scanning direction designated by the row scanning flag, a column address decoder that decodes column addresses, a display address decoder that decodes display addresses, and a driving circuit that drives a display section based on display data read from the RAM in accordance with a decoding result of the display address decoder.

Abstract: A method and computer program are provided for controlling access to a memory device wherein, even with a complex data storage structure, access is made to memory areas within the memory device with a minimal number of selection inputs required for selection of a desired memory area.

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.

Abstract: In a postal information input apparatus in which when a postcode to be read by a reader of a postal matter sorting machine cannot be normally read, a correct postcode is reentered manually from an input device, a first display means which displays on a display device of the input apparatus a first display so as to indicate that the postal information input apparatus receives a data to be input from the postal matter sorting machine, and also displays an unprocessed number in the postal information input apparatus, is provided.

Abstract: A subdivision level determination unit (13) in a curved surface subdivision apparatus (10) accepts an input of information about control points that define a shape of a curved surface and determines the subdivision level for the surface. Next, it sets, for a subdivision processing operation control unit (16), a control table corresponding to the determined subdivision level. The subdivision processing operation control unit (16) executes the subdivision processing while controlling a work memory unit (14) and a subdivision processing operation unit (15) based on the set control table.

Abstract: An information storing medium storing coded data of a content in segment units stores data including information of a horizontal video size, a vertical video size, a video depth, a maximum video data size in data segments, and a maximum audio data size in data segments as header information corresponding to the content. The stored data also includes information of the first frame number within a data segment, the number of frames within the data segment, and the address of each delimiter relative to the start of the data as segment information. A content reproducing apparatus can perform FIFO setting, data reading, and reproduction processing applying these pieces of information in a cache.

Abstract: An image processing apparatus, able to improve the pixel fill rate and able to prevent an increase of memory resources and increase of memory access, provided with a color calculation circuit for performing pixel level processing based on supplied first attribute parameters of the Z and color (R, G, B) data and outputting second attribute parameters and (x, y) coordinate data supplied by a DDA circuit together with the results and a sub primitive generation circuit for expanding a plurality of stamps to a plurality of sub primitives (sub stamps) based on the second attribute parameters of the color calculation circuit, generating expanded coordinates corresponding to the expanded sub stamps based on the (x, y) coordinate data of the DDA circuit, and outputting the same as the drawing parameters after expansion and the expanded graphics drawing coordinates to a memory controller, and a method of the same.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: An address converting unit receives pixel coordinates of a display screen in sequence and converts the received pixel coordinates to addresses and offsets. The addresses and offsets obtained from the conversions are stored in buffers in sequence respectively. A buffer controlling unit detects that one of the buffers is full. In response to the detection by the buffer controlling unit, a pixel processing unit modifies pixel data corresponding to the plural addresses read from the memory device according to pixel information. The pixel data stored in the memory device are rewritten according to the pieces of pixel information inputted in correspondence with the pixel coordinates. Therefore, the pieces of pixel data corresponding to the plural addresses are rewritten at a time.

Abstract: A video display interface controller for a host video display unit in which control signals multiplexed with component video signals are extracted and routed according to included address information. Control data associated with one or more local addresses is used for initial processing of the component video signals while control data associated with one or more remote addresses is used for subsequent signal processing.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: An image processing apparatus, able to improve the pixel fill rate and able to prevent an increase of memory resources and increase of memory access, provided with a color calculation circuit for performing pixel level processing based on supplied first attribute parameters of the Z and color (R, G, B) data and outputting second attribute parameters and (x, y) coordinate data supplied by a DDA circuit together with the results and a sub primitive generation circuit for expanding a plurality of stamps to a plurality of sub primitives (sub stamps) based on the second attribute parameters of the color calculation circuit, generating expanded coordinates corresponding to the expanded sub stamps based on the (x, y) coordinate data of the DDA circuit, and outputting the same as the drawing parameters after expansion and the expanded graphics drawing coordinates to a memory controller, and a method of the same.

Abstract: The present invention is broadly directed to a system of components defining a plurality of nodes and a random access memory (RAM) connected to each node. The system comprises at least one producer functional unit configured to perform a predetermined processing function resulting in the creation of at least one producer message, a communication mechanism configured to manage and control communication of messages with other nodes, at least one pointer that is configurable to point to a storage location within the RAM, and a message logic configured to interpret content of the at least one producer message, the message logic further configured to associate the producer message with a subset of the at least one pointers based upon the content of the at least one producer message, the message logic further configured to store the at least one producer message within the RAM at the locations indicated by the associated subset of at least one pointer.

Abstract: A graphics memory architecture in which row addresses are permuted, in a basically tile-oriented storage architecture, so that fast parallel access is provided both by scanlines (for video operations) and also by tiles (for graphics operations).

Abstract: An initial address register holds a transfer destination address as an initial address. Data is written into an input data register to which a unique address is allocated. The written data is put together into a data block having a predetermined transfer destination data size. This enhances the efficiency of data transfer from a software program for processing data in several byte units to a memory and a coprocessor optimized for data transfer in block units of several tens of bytes, and thus improves system performance.

Abstract: A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Abstract: A vertex data access apparatus and method. The apparatus receives a vertex index, compares the vertex index with any vertices' indices used before, issues a request if necessary for fetching vertex data in system memory, stores the return vertex data in a vertex data queue and gets corresponding vertex data from the vertex data queue for further processing and, more particularly, if the vertex index is the same as one of those vertices' indices, the corresponding vertex data can be directly fetched from the vertex data queue. The vertex data queue performs the vertex cache function.

Abstract: Methods and apparatus for implementing a pixel page system providing pixel pages using combined addressing. In alternative implementations, the system stores and retrieves data other than pixel data.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: An image processor having a frame memory for storing image data to newly generate purposed image data to be displayed by processing the image data in the frame memory, in which a processing memory for previously storing reference pixel coordinates for processing the image data is included and the data for the reference pixel coordinates in the processing memory is provided for the frame memory as an image-data read address.

Abstract: A system and method for accessing a memory array where retrieved data is stored in a memory and upon the writing of the data in its modified form, the originally stored data is updated with the modification prior to being written back to the memory array. In this manner, a new error correction code can be calculated prior to writing the data without the need to access the memory array again.

Abstract: A system and method for storing data in memory in either a packed or unpacked format contiguously and providing retrieved data in an unpacked format. The memory system includes a memory having packed and unpacked data stored in lines of data and a register to store a line of data it receives from the memory. Further included in the system is a selection circuit coupled to receive data from both the memory and the register. The selection circuit selects a portion of data from the lines of data presented to it by the memory and the register to be provided to a data bus according to a select signal provided by a memory address generator. The select signal is calculated by the memory address generator from an expected address at which the data is expected to be located. A second register and a second selection circuit may also be included in the memory system.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A format varying computing system including a computer linked to a display and input device, the computer including memory devices linked to a processing unit and a set of counters residing in the processing unit and linked to the memory devices, the set of counters defining a symbol residing in the memory devices.

Abstract: A buffer facilitates reordering of incoming memory access commands so that the memory access commands may be associated automatically according to their row/bank addresses. The storage capacity in the buffer may be dynamically allocated among groups as needed. When the buffer is flushed, groups of memory access commands are selected for flushing whose row/bank addresses are associated, thereby creating page coherency in the flushed memory access commands. Batches of commands may be flushed from the buffer according to a sequence designed to minimize same-bank page changes in frame buffer memory devices. Good candidate groups for flushing may be chosen according to criteria based on the binary bank address for the group, the size of the group, and the age of the group. Groups may be partially flushed. If so, a subsequent flush operation may resume flushing a partially-flushed group when to do so would be more beneficial than flushing a different group chosen solely based on its bank address.

Abstract: A method and apparatus for antialiasing in a video graphics system is presented. This is accomplished by determining if a pixel sample set, which results from oversampling, can be reduced to a compressed sample set that includes a single color value and a single Z value that fully describes a corresponding pixel. When the pixel sample set can be reduced to the compressed sample set, the compressed sample set is stored in a frame buffer at a location corresponding to the particular pixel that the sample set describes. When the pixel sample set cannot be reduced to a compressed sample set, pointer information is stored at the frame buffer location corresponding to the particular pixel. The pointer information includes a pointer that points to a selected address in a sample memory at which the complete sample set for the pixel is stored.

Abstract: An integrated circuit device includes a first memory unit and a conversion part for converting the parallel data read from the first memory unit into serial data. The integrated circuit device also includes a second memory unit that can write and read the data indicating the order of reading the parallel data from the first memory unit and the order of converting the parallel data into the serial data.

Abstract: A system and method for decoupling graphics operations from a host processor to improve the efficiency of graphics rendering and free the host processor for other essential tasks. A processing system includes a host processor, a memory, a display list processor (DLP), graphics accelerators and display hardware. The host processor builds display lists generated by graphics applications and stores the display lists in the memory. The display lists include hardware function directives and control directives. The DLP accesses the memory to process the display lists, issuing the hardware function directives to the accelerators to generate display data.

Abstract: A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.

Abstract: A method and apparatus for antialiasing in a video graphics system is accomplished by determining if a pixel sample set, which results from oversampling, can be reduced to a compressed sample set, where the compressed sample set contains information describing a corresponding pixel. When the pixel sample set can be reduced to a compressed sample set, the compressed sample set is stored in a frame buffer at a location corresponding to the particular pixel that the sample set describes. When the pixel sample set cannot be reduced to a compressed sample set, a pointer is stored at the frame buffer location corresponding to the particular pixel. The pointer points to a selected address in a sample memory at which the complete sample set for the pixel is stored.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port (“AGP”) bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table (“GART table”) is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A display control apparatus and a display apparatus respectively include control units for controlling themselves. The display control apparatus reads or writes data in a memory that can be accessed by the control unit in the display apparatus. Accesses from the display control apparatus to the memory in the display apparatus are made via a bus arranged in addition to a display image data transfer bus.

Abstract: A graphics display command list handler and method requests allocation of memory, such as system memory, in the form of a circular FIFO which stores the display command list as a memory display list (MDL), such as a host memory display list. A processor, such as a graphics processor, communicates a host memory display list read pointer to the host processor to facilitate display list signaling by the graphics processor. The host processor (or other processor) maintains a write pointer which points to a last host memory entry in the display list. The read pointer is maintained by the graphics processor and written back to the host processor.

Abstract: The present invention relates to a display memory control apparatus which can shorten a waiting time in making an access to a VRAM from a CPU without making large a circuit scale and causing an increase of power consumption. A data width of a VRAM is previously set to plural times as much as a data bus width of a CPU. A write data from the CPU is temporarily stored in a pre-buffer, and is transferred to one of data buffers included in a write buffer. The data buffer is specified by a low-order address. A VRAM control circuit can write all data or data of arbitrary combinations from data buffers into an address of VRAM specified by a high-order address buffer by one-time access.

Abstract: A graphics accelerator including an address remapping memory which straddles slow address spaces and fast address spaces.

Abstract: A system which utilizes dual-port memory to seamlessly display video frames on a raster scanned display device. Dual port memory is partitioned into a ‘single frame buffer’ having sufficient capacity to buffer a full video frame, and an ‘extension buffer’ which is a contiguous extension of the single frame buffer. The two sections together comprise an ‘extended buffer’. As long as the video memory write and read addresses are sufficiently separated by a predetermined number of lines, video data is written and read using the single frame buffer for each frame. When the write and read addresses are closer than a predetermined number of lines, the incoming video data for the next several new frames is written using the ‘extended’ buffer, and also read therefrom. After the write and read addresses are again sufficiently separated, video data is written and read using only the single frame buffer.

Abstract: Two-dimensional addresses of lateral lines of a rectangular area are produced in a prescribed scanning order in a sender-memory control unit as readout addresses of a sender's memory, pieces of pixel data corresponding to the readout addresses are read out from the sender's memory, the pieces of pixel data read out are sub-sampled at a sample ratio of n:1 in a direction of each lateral line according to a quincunx method in a data transforming unit, two-dimensional write addresses of a receiver's memory are produced in a receiver-memory control unit, and pieces of sub-sampled pixel data are written in the receiver's memory. Accordingly, the pieces of pixel data can be sub-sampled and transferred at a high speed in a DMA transfer apparatus.