Abstract: A visual display is provided on a data processing apparatus by storing and retrieving display information. The display information is stored by receiving write access addresses (33), translating the write access addresses into write memory addresses (15) and using the write memory addresses to store the display information (11). The read operation includes providing read access addresses (37), translating the read access addresses into memory read addresses (19) and using the memory read addresses to retrieve the display information (11).

Abstract: A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.

Abstract: The method of one embodiment for the invention is for the CPU to read a subset of consecutive pixels from RAM and cache each such pixel in the WC Cache (and load corresponding blocks into the L2 Cache). These reads and loads continue until the capacity of the L2 Cache is reached, and then these blocks (a “band”) are iteratively processed until the entire band in the L2 Cache has been written to the frame buffer via the WC Cache. Once this is complete, the process then “dumps” the L2 Cache (that is, it ignores the existing blocks and allows them to be naturally pushed out with subsequent loads) and the next band of consecutive pixels is read (and their blocks loaded). This process continues until the portrait-oriented graphic is entirely loaded.

Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate is discussed.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A method and apparatus for virtual address translation include processing that begins by receiving a memory access request that includes a virtual address. The processing continues by determining whether a physical address translation has been performed for the virtual address. Note that a physical address translation translates the virtual address into an address. The address either corresponds to physical address of memory or is further translated into another physical address of memory. The processing continues when the address, which resulted from the physical address translation or the another physical address translation, is stored in a translation look aside table (TLB). When the physical address translation or the another physical address translation has not been performed, the processing retrieves a physical page address based on a portion of the virtual address.

Abstract: A method of buffer management and task scheduling for two-dimensional data transforming is described. The method includes the steps of reading out old data in a block-by-block pattern and immediately writing in new data in a line-by-line pattern in a buffer using a first mapping scheme. And reading out a following old data in a block-by-block pattern and immediately writing in a following new data in a line-by-line pattern in the buffer using a second mapping scheme. The first and second mapping schemes are interleaved to guarantee output sequences while the buffer is kept full all the time. The buffer thus is maximized, the output flow is continuous and the process loading is smoothed out without loading bursts.

Abstract: A method and apparatus for hardware rotation is described. In one embodiment, the invention is an apparatus. The apparatus includes a direct access address translation component. The apparatus also includes a frame buffer coupled to the direct access address translation component. The apparatus further includes a 2D coordinate translation component. The apparatus also includes a 2D engine coupled to the 2D coordinate translation component and to the frame buffer. The apparatus further includes a 3D engine. The apparatus also include a 3D coordinate translation component coupled to the 3D engine and the frame buffer. As will be appreciated, further embodiments of the invention are within the spirit and scope of the claimed invention, and the specific details of a specific embodiment as described need not be present in all embodiments of the invention.

Abstract: A method for antialiased imaging of graphical objects on a pixel oriented display by rasterizing input pixel data as virtual pixels into a memory with a virtual resolution that is a factor higher than the physically displayed pixel resolution. In accordance with the invention, the existing color value of the physical pixel that corresponds to a virtual pixel to be modified is retrieved from the memory, the input color value of said virtual pixel to be rasterized is derived from the pixel input data, and split in its basic red, green and blue color components. The existing and the input color value are linearly combined for each color component in accordance with: ((N−1)*existing color value+M*input color value)/N, in which M represents a value at least equal to one and N being R2, and the result thereof used to overwrite the existing color value of the physical pixel at the memory location of said physical pixel.

Abstract: At least one chip of a chipset in a computer system having at least one host processor and a host memory are described herein. In one aspect of the invention, an exemplary chip includes an interconnect, a memory interface coupled to the interconnect, the memory interface providing access to the host memory and controlling memory refresh and memory access, a host interface coupled to the interconnect, the host interface providing access to the host processor, and a programmable media processor coupled to the interconnect, the media processor accessing the host through the host interface and the media processor accessing the host memory through the memory interface, wherein the media processor processes time based media.

Abstract: A memory device (118) may use a burst access mode to access a number of consecutive data words by giving one read or write command. These data bursts represent non-overlapping data-units in the memory device which can only be accessed as a whole. Because a request for data may contain only a few bytes and can overlay more than one data-unit in the memory device, the amount of transfer overhead is significant. To minimize this overhead a good mapping from logical addresses to physical addresses is important. For the address translation, a logical array is partitioned into a set of rectangles called windows and each window is stored in a row of the memory device. Data request of data-blocks that are actually stored or retrieved, are analyzed during a predetermined period, to calculate the optimal window size. The memory address translation unit (102) performs the analysis and generates the mapping.

Abstract: In accordance with a first mode of operation of the present invention, a portrait image is received from a system device. The portrait image is translated and stored within the graphics engine memory such that it can be displayed on a landscape monitor that has been rotated 90 degrees. Likewise, when portrait data stored within the memory is sent to the system it is translated such that it is sent back in the same format received by the system. In a second mode of operation in accordance with the present invention, a landscape image received by the graphics adapter is stored in the graphics adapter memory without any translation.

Abstract: A three dimensional parallax drawing system for use in three dimensional graphics or virtual reality is disclosed. The parallax drawing system includes a three dimensional address generator which generates the original X-axis, Y-axis and Z-axis addresses of an image, and an address correction circuit for producing a corrected X-axis address in response to the original X-axis and Z-axis address outputs from the address generator. Also included is an address selection circuit for selecting either the original X-axis address supplied from the three dimensional address generator or the corrected X-axis address from the address correction circuit as a resultant X-axis address in response to a stereo graphic mode request signal. A frame buffer address generator is provided for converting the resultant X-axis address received from the address selection means and the Y-axis address received from the three dimensional address generator into the frame buffer linear address.

Abstract: A video memory manager manages and virtualizes memory so that an application or multiple applications can utilize both system memory and local video memory in processing graphics. The video memory manager allocates memory in either the system memory or the local video memory as appropriate. The video memory manager may also manage the system memory accessible to the graphics processing unit via an aperture of the graphics processing unit. The video memory manager may evict memory from the local video memory as appropriate, thereby freeing a portion of local video memory use by other applications. In this manner, a graphics processing unit and its local video memory may be more readily shared by multiple applications.

Abstract: A system for translating a portrait-oriented software address to a portrait-oriented yet landscape-configured display address. Based on the orientation of a display device, a address translation system either passes the software address “as is” or translates the address to represent a portrait-oriented display address.

Abstract: In the address translation, there is a region in which the translation having a common regularity is possible into a plurality of regions, and a region in which such a translation is not possible. An address translation circuit is disposed between a master circuit and a slave circuit. The address translation to the former region is performed by a first address translation system in which the translated address is produced by a manipulation including permutation of a part of the original address, and the address translation to the latter region is performed by a second address translation system in which a part of the original address is replaced with translated address information stored beforehand. The data processor includes the address translation circuit having both of the first and second address translation systems.

Abstract: A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: An intelligent network address translation system and methods for intelligent network address translation. The invention analyzes all data packets being communicated between the private address relam and the public address realm and performs a predefined mode of network address translation based on the packet type. By analyzing every packet that the network encounters and adjusting the network address translation mode based on the packet type, the system and method of the present invention is able to adjust the mode of network address translation dynamically during a network user's ongoing network session. Additionaly, by basing which mode of translation will be employed based on packet type the translation method of the present invention insures that IP addresses are distributed efficiently and distribution of the amount of addresses is minimized.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: Methods and apparatuses for mapping a logical address to a physical address, in a data processing system having at least one host processor with host processor cache and host memory. In one aspect of the invention, an exemplary method includes translating a memory access request from logical addresses to physical addresses through a memory mapping mechanism, determining whether the physical address is configured for cache coherent access, if so, transmitting the request to cache coherent interface, and otherwise, transmitting the request to cache non-coherent interface. Other methods and apparatuses are also described.

Abstract: A 3-D rendering engine with embedded memory a graphics engine. A graphics engine is disclosed that includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.

Abstract: A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory management process can be locked down.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: The present invention is a system and method that efficiently converts a linear configuration virtual memory address to a physical memory address via a tile XY coordinate configuration system. The system and method of the present invention facilitates access of tile configuration frame buffers in a physical memory by computer graphics applications that are designed to designate frame buffer addresses in a virtual linear configuration. A linear-address is converted to into a tile XY coordinate address. Then a memory stroing a descriptor table is utilized to identify a translation buffer base frame offset associated with the particular frame buffer comprising the information to be accessed. Based upon the translation buffer base frame offset, a tile offset into the actual frame buffer tile is generated. A translation buffer component maps a number of graphics tiles and determines the address of a physical memory location associated with a base pixel of a particular graphics tile.

Abstract: An address relocation cache includes a plurality of entries. Each of the plurality of entries is configured to store at least a portion of an input address, at least a portion of an output address to which the input address translates, and a destination identifier corresponding to the output address. An input address may be translated to the output address and the corresponding destination identifier may be obtained concurrently for input addresses which hit in the address relocation cache. If an input address misses in the address relocation cache, a translation corresponding to the address may be located for storing into the address relocation cache. The output address indicated by the translation may be passed through the address map to obtain the destination identifier, and the destination identifier may be stored in the address relocation cache along with the output address.

Abstract: A graphics accelerator which includes a dedicated virtual memory manager which manages at least some host memory, as well as dedicated graphics memory, and which manages memory during mipmapping using at least two separate pools of memory.

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract: A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.

Abstract: A display subsystem supports both normal mode and portrait mode displays. In normal mode, the scan starts at the upper left comer of the display. In portrait mode, the scan starts at the lower left comer of the display. The display subsystem includes a dual mapped display memory having a normal mode display area and a portrait mode display area. The portrait mode display area is defined by X-ofst(Virtual) and Y-ofst. X-ofst(Virtual) is a power of two that is greater than the real X-ofst supported by the display in portrait mode. Address requests from the CPU or software use high order bits to specify whether the address is in the normal or portrait mode display area. In addition, address requests to the portrait mode display area use the address space defined by X-ofst(Virtual) and Y-ofst. When the address request specifies the portrait mode display area, the address of the request is translated to account for the different mode of the display.

Abstract: A cache memory apparatus for graphics and other systems. The cache memory apparatus includes a cache memory having a first number of cache lines, each cache line addressable by a cache line address; a first plurality of storage elements coupled to a first address bus; and a second plurality of storage elements coupled to the first plurality of storage elements. The first plurality of storage elements holds a second number of cache line addresses, and the second plurality of storage elements holds a third number of cache line addresses.

Abstract: An embodiment of the invention is directed to a method including fetching address translations for a current group of scanlines of image data and prefetching address translations for a next group of scanlines of image data. The prefetching occurs while the current group of scanlines of image data is being rendered on a display. The current group of scanlines and the next group of scanlines may be the same size such that determining address translations for the next group of scanlines terminates at or before the time the current group of scanlines have been rendered on the display. A translation look aside buffer (TLB) controller may be used to implement the method. In a particular embodiment of the invention, a first buffer and a second buffer are used such that when one stores address translations for the current group of scanlines of image data, the other stores address translations for the next group of scanlines of image data.

Abstract: An embodiment of a memory controller that improves main memory bandwidth utilization during graphics translational lookaside buffer fetch cycles is disclosed. The memory controller includes a first request path and a second request path. The memory controller further includes a graphics translational lookaside buffer that includes a cache. The graphics translational lookaside buffer issues an address fetch request to a memory interface when a graphics memory request received from the first request path or from the second request path misses the cache. The memory controller also includes a memory arbiter that includes a first request path cycle tracker and a second request path cycle tracker. The memory arbiter allows a request received from the second request path to be issued to the memory interface when a graphics memory request received from the first request path is stalled due to a graphics translational lookaside buffer cache miss.

Abstract: A system for implementing a graphics address remapping table as a virtual register in system memory. The remappinig table includes virtual registers that each store a target index that references a block of the system memory that stores graphics data using an indirect addressing scheme that enables the individual virtual registers of the remapping table to be accessed in response to a transaction request. Accessing a selected virtual register indirectly requested by the transaction request enables the access to the graphics data pointed to by the selected virtual register.

Abstract: A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided into tiles, which may be composed of one or more regions, and data in the frame buffer represents pixels on the display screen. When data representing a pixel is modified in the frame buffer, the region or tile associated with the pixel is marked as dirty, and those tiles or regions that are dirty in the frame buffer are written to the display.

Abstract: A method and system for improving virtual memory performance, especially in the context of data processing systems utilizing the Accelerated Graphics Port (AGP) interface standard. In the method and system, a request to access a first virtual memory address, correspondent to a first physical memory location resident within a first page of physical memory, is received. In response to the request to access the first virtual memory address, a Graphics Translation Look Aside Buffer entry is created. In response to a request to access a second virtual memory address, correspondent to a second physical memory address resident within a second physical memory area non-overlapping with the first physical memory page, the second physical memory location is accessed via the Graphics Translation Look Aside Buffer entry. The Graphics Translation Look Aside Buffer entry is constructed such that it translates a number of virtual memory addresses corresponding to a number of physical memory addresses.

Abstract: A size of a tile of memory is determined, where a tile is a segment of the memory having a dimension that is less than a pitch of the memory. Data is then stored in the tile. To access the data, a graphics processor obtains an indication (from a configuration register) that the memory is tiled, and accesses the data stored in the tile before accessing other segments of the memory.

Abstract: There is provided a display controller which can execute, with the hardware process, the address conversion corresponding to each drawing format even when a plurality of display data which are different in drawing formats exist simultaneously on the video memory and thereby can simultaneously improve the memory access performance in the drawing process and reduce a load of the CPU. This display controller 1 comprises an input section to which a display data and an address data are inputted, a video memory interface for writing the input display data to a video memory corresponding to a physical address in which each pixel of a 2n×2m (n and m are natural numbers) rectangular area formed by dividing the display area is continuous and a drawing circuit for executing the designated drawing process by receiving a command code for drawing from an external circuit.

Abstract: A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.

Abstract: A data processing apparatus which processes data held in memory. The data processing apparatus includes an address operation unit which obtains an address to read one-word data from the memory, wherein the one-word data is a unit of data access to the memory, and a logical operation unit which determines a content of an operation on a field basis based on information which designates the number of bits per field to construct one-word data with a plurality of fields having a same number of bits. The logical operation unit, based on the content thus determined, performs the operation in parallel on the fields of the one-word data read from the memory by the address thus obtained.

Abstract: A method and apparatus is described in which a firmware causes display of a graphical screen with various images that are stored in a non-volatile memory wherein the images may be selectively updated. A memory is configured into a plurality of memory segments wherein each memory segment has a predetermined address thereby allowing the segment to be selectively addressed. A circuit is able to configure a display template having a plurality of display sections on a display wherein data stored in the mentioned memory segments is displayed on a predetermined display section.

Abstract: A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials.

Abstract: A memory device (118) may use a burst access mode to access a number of consecutive data words by giving one read or write command. These data bursts represent non-overlapping data-units in the memory device which can only be accessed as a whole. Because a request for data may contain only a few bytes and can overlay more than one data-unit in the memory device, the amount of transfer overhead is significant. To minimize this overhead a good mapping from logical addresses to physical addresses is important. For the address translation, a logical array is partitioned into a set of rectangles called windows and each window is stored in a row of the memory device. Data request of data-blocks that are actually stored or retrieved, are analyzed during a predetermined period, to calculate the optimal window size. The memory address translation unit (102) performs the analysis and generates the mapping.

Abstract: A method of buffer management and task scheduling for two-dimensional data transforming is described. The method includes the steps of reading out old data in a block-by-block pattern and immediately writing in new data in a line-by-line pattern in a buffer using a first mapping scheme. And reading out a following old data in a block-by-block pattern and immediately writing in a following new data in a line-by-line pattern in the buffer using a second mapping scheme. The first and second mapping schemes are interleaved to guarantee output sequences while the buffer is kept full all the time. The buffer thus is maximized, the output flow is continuous and the process loading is smoothed out without loading bursts.

Abstract: A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Abstract: A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port (“AGP”) bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table (“GART table”) is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.

Abstract: A modular architecture for storing, addressing and retrieving graphics data from main memory instead of expensive local frame buffer memory. A graphic address remapping table (GART), defined in software, is used to remap virtual addresses falling within a selected range, the GART range, to non-contiguous pages in main memory. Virtual address not within the selected range are passed without modification. The GART includes page table entries (PTEs) having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. The GART PTEs are of configurable length enabling optimization of GART size and the use of feature bits, such as status indicators, defined by software. The GART is implemented during system boot up by configuration registers. Similarly, the PTEs are configured using mask registers. The GART may be used in conjunction with a translation lookaside buffer (TLB) to improve address remapping performance.